| commit | ddc9b5ee13cd686c8674f92d46045563c06a23ea | |
| author | Richard Earnshaw <rearnsha@arm.com> | |
| Thu, 6 Apr 2023 13:44:30 +0000 (6 14:44 +0100) | ||
| committer | Richard Earnshaw <rearnsha@arm.com> | |
| Thu, 6 Apr 2023 14:21:42 +0000 (6 15:21 +0100) | ||
| tree | 40f2402eac2e02132aa951f07d32f5423c40bc75 | treesnapshot (tar.gz zip) |
| parent | 7f056d5f4a0b9e29561d0375d5b4ad42c9f3f61e | commitdiff |
arm: mve: fix auto-inc generation [PR107674]
My change r13-416-g485a0ae0982abe caused the compiler to stop
generating auto-inc operations on mve loads and stores. The fix
is to check whether there is a replacement register available
when in strict mode and the register is still a pseudo.
gcc:
PR target/107674
* config/arm/arm.cc (arm_effective_regno): New function.
(mve_vector_mem_operand): Use it.
My change r13-416-g485a0ae0982abe caused the compiler to stop
generating auto-inc operations on mve loads and stores. The fix
is to check whether there is a replacement register available
when in strict mode and the register is still a pseudo.
gcc:
PR target/107674
* config/arm/arm.cc (arm_effective_regno): New function.
(mve_vector_mem_operand): Use it.
| gcc/config/arm/arm.cc | diffblobblamehistory |