RISC-V: Fix for combine bug with shift and AND operations.

RISC-V: Fix for combine bug with shift and AND operations.

	PR rtl-optimization/84660
	gcc/
	* config/riscv/riscv.h (SHIFT_COUNT_TRUNCATED): Set to zero.
	* config/riscv/riscv.md (<optab>si3): Use QImode shift count.
	(<optab>di3, <optab>si3_extend): Likewise.
	(<optab>si3_mask, <optab>si3_mask_1): New.
	(<optab>di3_mask, <optab>di3_mask_1): New.
	(<optab>si3_extend_mask, <optab>si3_extend_mask_1): New.
	(lshrsi3_zero_extend_1): Use VOIDmode shift count.
	* config/riscv/sync.md (atomic_test_and_set): Emit QImode shift count.
	gcc/testsuite/
	* gcc.target/riscv/pr84660.c: New.
	* gcc.target/riscv/shift-and-1.c: New.
	* gcc.target/riscv/shift-and-2.c: New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@259019 138bc75d-0d04-0410-961f-82ee72b054a4