| commit | b2aa75ded65f8c0293d73371e1660e7aeebb1eb6 | |
| author | John David Anglin <danglin@gcc.gnu.org> | |
| Wed, 30 Nov 2022 18:40:10 +0000 (30 18:40 +0000) | ||
| committer | John David Anglin <danglin@gcc.gnu.org> | |
| Wed, 30 Nov 2022 18:40:10 +0000 (30 18:40 +0000) | ||
| tree | 80d9d6948e20adf6ddfc16dc89a216eb0bb54475 | treesnapshot (tar.gz zip) |
| parent | cbdffae5745327b0e5eb887afc512daf34b049b1 | commitdiff |
Fix addvdi3 and subvdi3 patterns
While most PA 2.0 instructions support both 32 and 64-bit traps
and conditions, the addi and subi instructions only support 32-bit
traps and conditions. Thus, we need to force immediate operands
to register operands on the 64-bit target and use the add/sub
instructions which can trap on 64-bit signed overflow.
2022-11-30 John David Anglin <danglin@gcc.gnu.org>
gcc/ChangeLog:
* config/pa/pa.md (addvdi3): Force operand 2 to a register.
Remove "addi,tsv,*" instruction from unamed pattern.
(subvdi3): Force operand 1 to a register.
Remove "subi,tsv" instruction from from unamed pattern.
While most PA 2.0 instructions support both 32 and 64-bit traps
and conditions, the addi and subi instructions only support 32-bit
traps and conditions. Thus, we need to force immediate operands
to register operands on the 64-bit target and use the add/sub
instructions which can trap on 64-bit signed overflow.
2022-11-30 John David Anglin <danglin@gcc.gnu.org>
gcc/ChangeLog:
* config/pa/pa.md (addvdi3): Force operand 2 to a register.
Remove "addi,tsv,*" instruction from unamed pattern.
(subvdi3): Force operand 1 to a register.
Remove "subi,tsv" instruction from from unamed pattern.
| gcc/config/pa/pa.md | diffblobblamehistory |