[AArch64][committed] Fix gcc.target/aarch64/vec_init_1.c for tiny and large mcmodels

[AArch64][committed] Fix gcc.target/aarch64/vec_init_1.c for tiny and large mcmodels

This recently-committed test fails the INS scan for tiny and large memory models.
That is because instead of the:
make_vector:
         adrp    x1, a
         adrp    x0, b
         movi    v0.4s, 0
         ldr     s2, [x1, #:lo12:a]
         ldr     s1, [x0, #:lo12:b]
         ins     v0.s[2], v2.s[0]
         ins     v0.s[3], v1.s[0]
         ret

That we generate for the default small model, we end up with a simple register
addressing mode with no addend/offset for the lane load:
make_vector:
         movi    v0.4s, 0
         adr     x1, a
         adr     x0, b
         ld1     {v0.s}[2], [x1]
         ld1     {v0.s}[3], [x0]
         ret

and

make_vector:
         movi    v0.4s, 0
         adrp    x0, .LC0
         ldr     x1, [x0, #:lo12:.LC0]
         adrp    x0, .LC1
         ldr     x0, [x0, #:lo12:.LC1]
         ld1     {v0.s}[2], [x1]
         ld1     {v0.s}[3], [x0]
         ret

So we end up merging the load and the lane insert.
This patch adjusts the testcase to scan for the right thing accordingly.
Checked that the testcase passes with -mcmodel=tiny, -mcmodel=small, -mcmodel=large.

	* gcc.target/aarch64/vec_init_1.c: Scan for LD1 instead of INS for
	tiny and large memory models.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260474 138bc75d-0d04-0410-961f-82ee72b054a4