RISC-V: Add xfail test case for indexed load overlap with SRC EEW < DEST EEW
commita367b99f916cb7d2d673180ace640096fd118950
authorPan Li <pan2.li@intel.com>
Mon, 22 Apr 2024 07:36:59 +0000 (22 15:36 +0800)
committerPan Li <pan2.li@intel.com>
Mon, 22 Apr 2024 07:45:44 +0000 (22 15:45 +0800)
treea86c455eb4c50327a3afd6689600c135f03189aa
parent9257c7a72059aba0df1684a0722c4d1538cbb6d4
RISC-V: Add xfail test case for indexed load overlap with SRC EEW < DEST EEW

Update in v2:
* Add change log to pr112431-34.c.

Original log:

We reverted below patch for register group overlap, add the related
insn test and mark it as xfail.  And we will remove the xfail
after we support the register overlap in GCC-15.

4418d55bcd1 RISC-V: Support highpart overlap for indexed load with SRC EEW < DEST EEW

The below test suites are passed.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pr112431-34.c: Remove xfail for vluxei8 check.
* gcc.target/riscv/rvv/base/pr112431-28.c: New test.
* gcc.target/riscv/rvv/base/pr112431-29.c: New test.
* gcc.target/riscv/rvv/base/pr112431-30.c: New test.
* gcc.target/riscv/rvv/base/pr112431-31.c: New test.
* gcc.target/riscv/rvv/base/pr112431-32.c: New test.
* gcc.target/riscv/rvv/base/pr112431-33.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-28.c [copied from gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c with 92% similarity]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-29.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-30.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-31.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-32.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-33.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-34.c