[Mechanical Patch ARM/AArch64 1/2] Rename load/store scheduling types to encode data...
commit89b2133e2b7ef072e5b378a82c697269d8cd1db9
authorJames Greenhalgh <james.greenhalgh@arm.com>
Tue, 12 Sep 2017 14:48:34 +0000 (12 14:48 +0000)
committerJames Greenhalgh <jgreenhalgh@gcc.gnu.org>
Tue, 12 Sep 2017 14:48:34 +0000 (12 14:48 +0000)
tree4f1d9f7cf8db1139f21324967536701523c026fe
parent5f33b353ea04335c7d1210eab3d4a46ec54f0633
[Mechanical Patch ARM/AArch64 1/2] Rename load/store scheduling types to encode data size

In the AArch64 backend and scheduling models there is some confusion as to
what the load1/load2 etc. scheduling types refer to. This leads to us using
load1/load2 in two contexts - for a variety of 32-bit, 64-bit and 128-bit
loads in AArch32 and 128-bit loads in AArch64. That leads to an undesirable
confusion in scheduling.

Fixing it is easy, but mechanical and boring. Essentially,

  s/load1/load_4/
  s/load2/load_8/
  s/load3/load_12/
  s/load4/load_16/
  s/store1/store_4/
  s/store2/store_8/
  s/store3/store_12/
  s/store4/store_16/

Across all sorts of pipeline models, and the two backends.

I have intentionally not modified any of the patterns which now look obviously
incorrect. I'll be doing a second pass over the AArch64 back-end in patch
2/2 which will fix these bugs.

---
gcc/

* config/arm/types.md (type): Rename load1/2/3/4 to load_4/8/12/16
and store1/2/3/4 to store_4/8/12/16.
* config/aarch64/aarch64.md: Update for rename.
* config/arm/arm.md: Likewise.: Likewise.
* config/arm/arm.c: Likewise.
* config/arm/thumb1.md: Likewise.
* config/arm/thumb2.md: Likewise.
* config/arm/vfp.md: Likewise.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1020e.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
* config/arm/arm1136jfs.md: Likewise.
* config/arm/arm926ejs.md: Likewise.
* config/arm/cortex-a15.md: Likewise.
* config/arm/cortex-a17.md: Likewise.
* config/arm/cortex-a5.md: Likewise.
* config/arm/cortex-a53.md: Likewise.
* config/arm/cortex-a57.md: Likewise.
* config/arm/cortex-a7.md: Likewise.
* config/arm/cortex-a8.md: Likewise.
* config/arm/cortex-a9.md: Likewise.
* config/arm/cortex-m4.md: Likewise.
* config/arm/cortex-m7.md: Likewise.
* config/arm/cortex-r4.md: Likewise.
* config/arm/exynos-m1.md: Likewise.
* config/arm/fa526.md: Likewise.
* config/arm/fa606te.md: Likewise.
* config/arm/fa626te.md: Likewise.
* config/arm/fa726te.md: Likewise.
* config/arm/fmp626.md: Likewise.
* config/arm/iwmmxt.md: Likewise.
* config/arm/ldmstm.md: Likewise.
* config/arm/marvell-pj4.md: Likewise.
* config/arm/xgene1.md: Likewise.
* config/aarch64/thunderx.md: Likewise.
* config/aarch64/thunderx2t99.md: Likewise.
* config/aarch64/falkor.md: Likewise.

From-SVN: r252025
37 files changed:
gcc/ChangeLog
gcc/config/aarch64/aarch64.md
gcc/config/aarch64/falkor.md
gcc/config/aarch64/thunderx.md
gcc/config/aarch64/thunderx2t99.md
gcc/config/arm/arm-generic.md
gcc/config/arm/arm.c
gcc/config/arm/arm.md
gcc/config/arm/arm1020e.md
gcc/config/arm/arm1026ejs.md
gcc/config/arm/arm1136jfs.md
gcc/config/arm/arm926ejs.md
gcc/config/arm/cortex-a15.md
gcc/config/arm/cortex-a17.md
gcc/config/arm/cortex-a5.md
gcc/config/arm/cortex-a53.md
gcc/config/arm/cortex-a57.md
gcc/config/arm/cortex-a7.md
gcc/config/arm/cortex-a8.md
gcc/config/arm/cortex-a9.md
gcc/config/arm/cortex-m4.md
gcc/config/arm/cortex-m7.md
gcc/config/arm/cortex-r4.md
gcc/config/arm/exynos-m1.md
gcc/config/arm/fa526.md
gcc/config/arm/fa606te.md
gcc/config/arm/fa626te.md
gcc/config/arm/fa726te.md
gcc/config/arm/fmp626.md
gcc/config/arm/iwmmxt.md
gcc/config/arm/ldmstm.md
gcc/config/arm/marvell-pj4.md
gcc/config/arm/thumb1.md
gcc/config/arm/thumb2.md
gcc/config/arm/types.md
gcc/config/arm/vfp.md
gcc/config/arm/xgene1.md