RISC-V: Allow register pairs for 64-bit target.
commit807f034ed9077ddc5b8163334acd506d33076ac6
authorwilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
Sat, 27 Jan 2018 00:00:11 +0000 (27 00:00 +0000)
committerwilson <wilson@138bc75d-0d04-0410-961f-82ee72b054a4>
Sat, 27 Jan 2018 00:00:11 +0000 (27 00:00 +0000)
tree6aacd69c700f38c060cba145fbc700ae7b2a8fe9
parentcd5e24c16302d9109c4b8cde8d5bbf40afdbb1e5
RISC-V: Allow register pairs for 64-bit target.

gcc/
* config/riscv/riscv.h (MAX_FIXED_MODE_SIZE): New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@257114 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/ChangeLog
gcc/config/riscv/riscv.h