ii386: Generate QImode binary ops with high-part input register [PR108831]

ii386: Generate QImode binary ops with high-part input register [PR108831]

Following testcase:

--cut here--
struct S
{
  unsigned char pad1;
  unsigned char val;
  unsigned short pad2;
};

unsigned char
test_add (unsigned char a, struct S b)
{
  a += b.val;

  return a;
}
--cut here--

should be compiled to something like:

        addb %dh, %al

but is currently compiled to:

        movzbl  %dh, %edx
        addl    %edx, %eax

The patch implements insn patterns that model QImode binary ops with
high-part QImode input register.  These ops can not be encoded with
REX prefix, so only Q registers and constant memory output operands
are allowed on x86_64 targets.

2023-02-17  Uroš Bizjak  <ubizjak@gmail.com>

gcc/ChangeLog:

	PR target/108831
	* config/i386/predicates.md
	(nonimm_x64constmem_operand): New predicate.
	* config/i386/i386.md (*addqi_ext<mode>_0): New insn pattern.
	(*subqi_ext<mode>_0): Ditto.
	(*andqi_ext<mode>_0): Ditto.
	(*<any_or:code>qi_ext<mode>_0): Ditto.

gcc/testsuite/ChangeLog:

	PR target/108831
	* gcc.target/i386/pr108831-1.c: New test.
	* gcc.target/i386/pr108831-2.c: Ditto.