Enable LRA for MIPS
commit3c0e3fb9717d9c1a7f34bd2608e8a6c116fd6887
authormpf <mpf@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 18 Jun 2014 20:40:34 +0000 (18 20:40 +0000)
committermpf <mpf@138bc75d-0d04-0410-961f-82ee72b054a4>
Wed, 18 Jun 2014 20:40:34 +0000 (18 20:40 +0000)
treee7d67181f5ba9b00489ae4d9406c02a1a047eb29
parent58b15582eee8bf8e5f31757bdea4de7121712ebf
Enable LRA for MIPS

gcc/

* config/mips/constraints.md ("d"): BASE_REG_CLASS replaced by
"TARGET_MIPS16 ? M16_REGS : GR_REGS".
* config/mips/mips.c (mips_regno_to_class): Update for M16_SP_REGS.
(mips_regno_mode_ok_for_base_p): Remove use of !strict_p for MIPS16.
(mips_register_priority): New function that implements the target
hook TARGET_REGISTER_PRIORITY.
(mips_spill_class): Likewise for TARGET_SPILL_CLASS.
(mips_lra_p): Likewise for TARGET_LRA_P.
(TARGET_REGISTER_PRIORITY): Define macro.
(TARGET_SPILL_CLASS): Likewise.
(TARGET_LRA_P): Likewise.
* config/mips/mips.h (reg_class): Add M16_SP_REGS and SPILL_REGS
classes.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(BASE_REG_CLASS): Use M16_SP_REGS.
* config/mips/mips.md (*mul_acc_si): Add alternative tuned for LRA.
New set attribute to enable alternatives depending on the register
allocator used.
(*mul_acc_si_r3900, *mul_sub_si): Likewise.
(*lea64): Disable pattern for MIPS16.
* config/mips/mips.opt (mlra): New option.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211805 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/ChangeLog
gcc/config/mips/constraints.md
gcc/config/mips/mips.c
gcc/config/mips/mips.h
gcc/config/mips/mips.md
gcc/config/mips/mips.opt