| commit | 32799ae17d9dd1e04e35e4bec90b25a40414c52a | |
| author | avieira <avieira@138bc75d-0d04-0410-961f-82ee72b054a4> | |
| Thu, 24 May 2018 08:53:39 +0000 (24 08:53 +0000) | ||
| committer | avieira <avieira@138bc75d-0d04-0410-961f-82ee72b054a4> | |
| Thu, 24 May 2018 08:53:39 +0000 (24 08:53 +0000) | ||
| tree | dbd76ddc29df4e2ed978b1568abe0eb8a84e7899 | treesnapshot (tar.gz zip) |
| parent | 49446baa4597e960867b8586ac220424b418b53f | commitdiff |
PR target/83009: Relax strict address checking for store pair lanes
The operand constraint for the memory address of store/load pair lanes was
enforcing strictly hardware registers be allowed as memory addresses. We want
to relax that such that these patterns can be used by combine. During register
allocation the register constraint will enforce the correct register is chosen.
gcc
2018-05-24 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/83009
* config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Make
address check not strict.
gcc/testsuite
2018-05-24 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/83009
* gcc/target/aarch64/store_v2vec_lanes.c: Add extra tests.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260635 138bc75d-0d04-0410-961f-82ee72b054a4
The operand constraint for the memory address of store/load pair lanes was
enforcing strictly hardware registers be allowed as memory addresses. We want
to relax that such that these patterns can be used by combine. During register
allocation the register constraint will enforce the correct register is chosen.
gcc
2018-05-24 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/83009
* config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Make
address check not strict.
gcc/testsuite
2018-05-24 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/83009
* gcc/target/aarch64/store_v2vec_lanes.c: Add extra tests.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@260635 138bc75d-0d04-0410-961f-82ee72b054a4