| commit | 318e0d44fe66ade59edb16a94565b3bfdc1883c6 | |
| author | Uros Bizjak <ubizjak@gmail.com> | |
| Sun, 3 Mar 2024 19:40:45 +0000 (3 20:40 +0100) | ||
| committer | Uros Bizjak <ubizjak@gmail.com> | |
| Sun, 3 Mar 2024 19:41:34 +0000 (3 20:41 +0100) | ||
| tree | ceb264059f869cfcc62f269da6e96157c1d64af3 | treesnapshot (tar.gz zip) |
| parent | c0f5b6caff669037444506cb6008a378356ec209 | commitdiff |
alpha: Introduce UMUL_HIGHPART rtx_code [PR113720]
umuldi3_highpart expander does:
if (REG_P (operands[2]))
operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
on register_operand predicate, which also allows SUBREG RTX. So,
subregs were emitted without ZERO_EXTEND RTX.
But nowadays we have UMUL_HIGHPART that allows us to fix this
issue while also simplifying the instruction RTX.
PR target/113720
gcc/ChangeLog:
* config/alpha/alpha.md (umuldi3_highpart): Remove expander.
(*umuldi3_highpart_reg): Rename to umuldi3_highpart and
simplify insn RTX using UMUL_HIGHPART rtx_code.
(*umuldi3_highpart_const): Remove.
umuldi3_highpart expander does:
if (REG_P (operands[2]))
operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
on register_operand predicate, which also allows SUBREG RTX. So,
subregs were emitted without ZERO_EXTEND RTX.
But nowadays we have UMUL_HIGHPART that allows us to fix this
issue while also simplifying the instruction RTX.
PR target/113720
gcc/ChangeLog:
* config/alpha/alpha.md (umuldi3_highpart): Remove expander.
(*umuldi3_highpart_reg): Rename to umuldi3_highpart and
simplify insn RTX using UMUL_HIGHPART rtx_code.
(*umuldi3_highpart_const): Remove.
| gcc/config/alpha/alpha.md | diffblobblamehistory |