| commit | 2680f5eec23805ab8a344f942ca5a7e180d57905 | |
| author | Uros Bizjak <ubizjak@gmail.com> | |
| Tue, 3 May 2022 15:59:40 +0000 (3 17:59 +0200) | ||
| committer | Uros Bizjak <ubizjak@gmail.com> | |
| Tue, 3 May 2022 16:00:25 +0000 (3 18:00 +0200) | ||
| tree | da322d19f3197b7717c54c8d10310d3927ad51e4 | treesnapshot (tar.gz zip) |
| parent | da6d834bc2188e36e876416f25a1aee528c3484d | commitdiff |
i386: Optimize _mm_storeu_si16 w/o SSE4 [PR105079]
Optimize _mm_storeu_si16 to use MOVD from a SSE to an integer register
instead of PEXTRW from a low word of the SSE register to an integer reg.
Avoid the transformation when optimizing for size for targets without
TARGET_INTER_UNIT_MOVES_FROM_VEC capability, where the transformation
results in two moves via a memory location.
2022-05-03 Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/105079
* config/i386/sse.md (*vec_extract<mode>_0_mem): New pre-reload
define_insn_and_split pattern.
gcc/testsuite/ChangeLog:
PR target/105079
* gcc.target/i386/pr105079.c: New test.
* gcc.target/i386/pr95483-1.c (dg-options): Use -msse4.1.
Optimize _mm_storeu_si16 to use MOVD from a SSE to an integer register
instead of PEXTRW from a low word of the SSE register to an integer reg.
Avoid the transformation when optimizing for size for targets without
TARGET_INTER_UNIT_MOVES_FROM_VEC capability, where the transformation
results in two moves via a memory location.
2022-05-03 Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/105079
* config/i386/sse.md (*vec_extract<mode>_0_mem): New pre-reload
define_insn_and_split pattern.
gcc/testsuite/ChangeLog:
PR target/105079
* gcc.target/i386/pr105079.c: New test.
* gcc.target/i386/pr95483-1.c (dg-options): Use -msse4.1.
| gcc/config/i386/sse.md | diffblobblamehistory | |
| gcc/testsuite/gcc.target/i386/pr105079.c | [new file with mode: 0644] | blob |
| gcc/testsuite/gcc.target/i386/pr95483-1.c | diffblobblamehistory |