RISC-V: Add VLS integer ABS support
commit1df81f01e45c8b16cf3995cf63c766124a0729ea
authorJuzhe-Zhong <juzhe.zhong@rivai.ai>
Thu, 21 Sep 2023 22:47:22 +0000 (22 06:47 +0800)
committerPan Li <pan2.li@intel.com>
Thu, 21 Sep 2023 22:58:37 +0000 (22 06:58 +0800)
treefe07f58d5ee4e0765204d2b4d79bc945f9f082e2
parent29862e21f6d656eca59284c927d0c4c0698eb99c
RISC-V: Add VLS integer ABS support

Regression passed.

Committed.

gcc/ChangeLog:

* config/riscv/autovec.md: Extend VLS modes.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls/abs-2.c: New test.
gcc/config/riscv/autovec.md
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c [new file with mode: 0644]