[Patch 5/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins
commit0b20e0f17b47a86cddba68a2e016be0132ae9b0a
authorHaochen Jiang <haochen.jiang@intel.com>
Thu, 17 Aug 2023 06:24:59 +0000 (17 14:24 +0800)
committerHaochen Jiang <haochen.jiang@intel.com>
Thu, 17 Aug 2023 06:24:59 +0000 (17 14:24 +0800)
treeeeba9809516409b8a037ee2bc531e940c4fdd00d
parentaba10895052fcb2ab3c6d53ad98c855509877555
[Patch 5/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins

gcc/ChangeLog:

* config/i386/avx512vldqintrin.h: Remove target attribute.
* config/i386/i386-builtin.def (BDESC):
Add OPTION_MASK_ISA2_AVX10_1.
* config/i386/sse.md (VF_AVX512VLDQ_AVX10_1): New.
(VFH_AVX512VLDQ_AVX10_1): Ditto.
(VF1_AVX512VLDQ_AVX10_1): Ditto.
(<mask_codefor>reducep<mode><mask_name><round_saeonly_name>):
Change iterator to VFH_AVX512VLDQ_AVX10_1. Remove target check.
(vec_pack<floatprefix>_float_<mode>): Change iterator to
VI8_AVX512VLDQ_AVX10_1. Remove target check.
(vec_unpack_<fixprefix>fix_trunc_lo_<mode>): Change iterator to
VF1_AVX512VLDQ_AVX10_1. Remove target check.
(vec_unpack_<fixprefix>fix_trunc_hi_<mode>): Ditto.
(VI48F_256_DQVL_AVX10_1): Rename from VI48F_256_DQ.
(avx512vl_vextractf128<mode>): Change iterator to
VI48F_256_DQVL_AVX10_1. Remove target check.
(vec_extract_hi_<mode>_mask): Add TARGET_AVX10_1.
(vec_extract_hi_<mode>): Ditto.
(avx512vl_vinsert<mode>): Ditto.
(vec_set_lo_<mode><mask_name>): Ditto.
(vec_set_hi_<mode><mask_name>): Ditto.
(avx512dq_rangep<mode><mask_name><round_saeonly_name>): Change
iterator to VF_AVX512VLDQ_AVX10_1. Remove target check.
(avx512dq_fpclass<mode><mask_scalar_merge_name>): Change
iterator to VFH_AVX512VLDQ_AVX10_1. Remove target check.
* config/i386/subst.md (mask_avx512dq_condition): Add
TARGET_AVX10_1.
(mask_scalar_merge): Ditto.
gcc/config/i386/avx512vldqintrin.h
gcc/config/i386/i386-builtin.def
gcc/config/i386/sse.md
gcc/config/i386/subst.md