[AArch64] Fix ICE due to store_pair_lanes

[AArch64] Fix ICE due to store_pair_lanes

The recently added store_pair_lanes causes ICEs in output_operand.
This is due to aarch64_classify_address treating it like a 128-bit STR
rather than a STP.  The valid immediate offsets don't fully overlap,
causing it to return false.  Eg. offset 264 is a valid 8-byte STP offset
but not a valid 16-byte STR offset since it isn't a multiple of 16.

The original instruction isn't passed in the printing code, so the context
is unclear.  The solution is to add a new operand formatting specifier
which is used for LDP/STP instructions like this.  This, like the Uml
constraint that applies to store_pair_lanes, uses PARALLEL when calling
aarch64_classify_address so that it knows it is an STP.
Also add the 'z' specifier for future use by load/store pair instructions.

    gcc/
	* config/aarch64/aarch64.c (aarch64_print_operand): Add new
	cases for printing LDP/STP memory addresses.
	(aarch64_print_address_internal): Renamed from
	aarch64_print_operand_address, added parameter, add Pmode check.
	(aarch64_print_ldpstp_address): New function for LDP/STP addresses.
	(aarch64_print_operand_address): Indirect to
	aarch64_print_address_internal.
	* config/aarch64/aarch64-simd.md (store_pair_lanes): Use new
	'y' operand output specifier.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@255230 138bc75d-0d04-0410-961f-82ee72b054a4