sys/arch/i386/pci/gscpcib.c

   1 /*      $NetBSD: gscpcib.c,v 1.14 2009/08/18 19:51:45 dyoung Exp $      */
   2 /*      $OpenBSD: gscpcib.c,v 1.3 2004/10/05 19:02:33 grange Exp $      */
   3 /*
   4  * Copyright (c) 2004 Alexander Yurchenko <grange@openbsd.org>
   5  *
   6  * Permission to use, copy, modify, and distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  */
  18
  19 /*
  20  * Special driver for the National Semiconductor Geode SC1100 PCI-ISA bridge
  21  * that attaches instead of pcib(4). In addition to the core pcib(4)
  22  * functionality this driver provides support for the GPIO interface.
  23  */
  24
  25 #include <sys/cdefs.h>
  26 __KERNEL_RCSID(0, "$NetBSD: gscpcib.c,v 1.14 2009/08/18 19:51:45 dyoung Exp $");
  27
  28 #include <sys/param.h>
  29 #include <sys/systm.h>
  30 #include <sys/device.h>
  31 #include <sys/gpio.h>
  32 #include <sys/kernel.h>
  33
  34 #include <machine/bus.h>
  35
  36 #include <dev/pci/pcireg.h>
  37 #include <dev/pci/pcivar.h>
  38 #include <dev/pci/pcidevs.h>
  39
  40 #include <dev/gpio/gpiovar.h>
  41
  42 #include <i386/pci/gscpcibreg.h>
  43 #include <arch/x86/pci/pcibvar.h>
  44
  45 struct gscpcib_softc {
  46         struct pcib_softc sc_pcib;
  47
  48         bool sc_gpio_present;
  49         device_t sc_gpiobus;
  50
  51         /* GPIO interface */
  52         bus_space_tag_t sc_gpio_iot;
  53         bus_space_handle_t sc_gpio_ioh;
  54         struct gpio_chipset_tag sc_gpio_gc;
  55         gpio_pin_t sc_gpio_pins[GSCGPIO_NPINS];
  56 };
  57
  58 int     gscpcib_match(device_t, cfdata_t, void *);
  59 void    gscpcib_attach(device_t, device_t, void *);
  60 int     gscpcib_detach(device_t, int);
  61 int     gscpcib_rescan(device_t, const char *, const int *);
  62 void    gscpcib_childdetached(device_t, device_t);
  63
  64 int     gscpcib_gpio_pin_read(void *, int);
  65 void    gscpcib_gpio_pin_write(void *, int, int);
  66 void    gscpcib_gpio_pin_ctl(void *, int, int);
  67
  68 CFATTACH_DECL3_NEW(gscpcib, sizeof(struct gscpcib_softc),
  69         gscpcib_match, gscpcib_attach, gscpcib_detach, NULL, gscpcib_rescan,
  70         gscpcib_childdetached, DVF_DETACH_SHUTDOWN);
  71
  72 extern struct cfdriver gscpcib_cd;
  73
  74 void
  75 gscpcib_childdetached(device_t self, device_t child)
  76 {
  77         struct gscpcib_softc *sc = device_private(self);
  78
  79         if (sc->sc_gpiobus == child)
  80                 sc->sc_gpiobus = NULL;
  81         else
  82                 pcibchilddet(self, child);
  83 }
  84
  85 int
  86 gscpcib_rescan(device_t self, const char *ifattr, const int *loc)
  87 {
  88         struct gscpcib_softc *sc = device_private(self);
  89
  90         /* Attach GPIO framework */
  91         if (sc->sc_gpio_present && ifattr_match(ifattr, "gpiobus") &&
  92             sc->sc_gpiobus == NULL) {
  93                 struct gpiobus_attach_args gba;
  94
  95                 gba.gba_gc = &sc->sc_gpio_gc;
  96                 gba.gba_pins = sc->sc_gpio_pins;
  97                 gba.gba_npins = GSCGPIO_NPINS;
  98
  99                 sc->sc_gpiobus = config_found_sm_loc(self, "gpiobus", loc,
 100                     &gba, gpiobus_print, NULL);
 101                 return 0;
 102         }
 103         return pcibrescan(self, ifattr, loc);
 104 }
 105
 106 int
 107 gscpcib_match(device_t parent, cfdata_t match, void *aux)
 108 {
 109         struct pci_attach_args *pa = aux;
 110
 111         if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE ||
 112             PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA)
 113                 return (0);
 114
 115         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS &&
 116             PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SC1100_ISA)
 117                 return (2);     /* supersede pcib(4) */
 118
 119         return (0);
 120 }
 121
 122 void
 123 gscpcib_attach(device_t parent, device_t self, void *aux)
 124 {
 125         struct gscpcib_softc *sc = device_private(self);
 126         struct pci_attach_args *pa = aux;
 127         pcireg_t gpiobase;
 128         int i;
 129
 130         /* Map GPIO I/O space */
 131         gpiobase = pci_conf_read(pa->pa_pc, pa->pa_tag, GSCGPIO_BASE);
 132         sc->sc_gpio_iot = pa->pa_iot;
 133         if (bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(gpiobase),
 134             GSCGPIO_SIZE, 0, &sc->sc_gpio_ioh)) {
 135                 printf(": failed to map GPIO I/O space");
 136                 goto corepcib;
 137         }
 138
 139         /* Initialize pins array */
 140         for (i = 0; i < GSCGPIO_NPINS; i++) {
 141                 sc->sc_gpio_pins[i].pin_num = i;
 142                 sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT |
 143                     GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN |
 144                     GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE |
 145                     GPIO_PIN_PULLUP;
 146
 147                 /* safe defaults */
 148                 sc->sc_gpio_pins[i].pin_flags = GPIO_PIN_TRISTATE;
 149                 sc->sc_gpio_pins[i].pin_state = GPIO_PIN_LOW;
 150                 gscpcib_gpio_pin_ctl(sc, i, sc->sc_gpio_pins[i].pin_flags);
 151                 gscpcib_gpio_pin_write(sc, i, sc->sc_gpio_pins[i].pin_state);
 152         }
 153
 154         /* Create controller tag */
 155         sc->sc_gpio_gc.gp_cookie = sc;
 156         sc->sc_gpio_gc.gp_pin_read = gscpcib_gpio_pin_read;
 157         sc->sc_gpio_gc.gp_pin_write = gscpcib_gpio_pin_write;
 158         sc->sc_gpio_gc.gp_pin_ctl = gscpcib_gpio_pin_ctl;
 159
 160         sc->sc_gpio_present = true;
 161
 162 corepcib:
 163         /* Provide core pcib(4) functionality */
 164         pcibattach(parent, self, aux);
 165
 166         gscpcib_rescan(self, "gpiobus", NULL);
 167 }
 168
 169 int
 170 gscpcib_detach(device_t self, int flags)
 171 {
 172         int rc;
 173         struct gscpcib_softc *sc = device_private(self);
 174
 175         if ((rc = config_detach_children(self, flags)) != 0)
 176                 return rc;
 177
 178         if ((rc = pcibdetach(self, flags)) != 0)
 179                 return rc;
 180
 181         if (sc->sc_gpio_present)
 182                 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, GSCGPIO_SIZE);
 183
 184         return rc;
 185 }
 186
 187 static inline void
 188 gscpcib_gpio_pin_select(struct gscpcib_softc *sc, int pin)
 189 {
 190         bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, GSCGPIO_SEL, pin);
 191 }
 192
 193 int
 194 gscpcib_gpio_pin_read(void *arg, int pin)
 195 {
 196         struct gscpcib_softc *sc = arg;
 197         int reg, shift;
 198         uint32_t data;
 199
 200         reg = (pin < 32 ? GSCGPIO_GPDI0 : GSCGPIO_GPDI1);
 201         shift = pin % 32;
 202         data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);
 203
 204         return ((data >> shift) & 0x1);
 205 }
 206
 207 void
 208 gscpcib_gpio_pin_write(void *arg, int pin, int value)
 209 {
 210         struct gscpcib_softc *sc = arg;
 211         int reg, shift;
 212         uint32_t data;
 213
 214         reg = (pin < 32 ? GSCGPIO_GPDO0 : GSCGPIO_GPDO1);
 215         shift = pin % 32;
 216         data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg);
 217         if (value == 0)
 218                 data &= ~(1 << shift);
 219         else if (value == 1)
 220                 data |= (1 << shift);
 221
 222         bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data);
 223 }
 224
 225 void
 226 gscpcib_gpio_pin_ctl(void *arg, int pin, int flags)
 227 {
 228         struct gscpcib_softc *sc = arg;
 229         uint32_t conf;
 230
 231         gscpcib_gpio_pin_select(sc, pin);
 232         conf = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh,
 233             GSCGPIO_CONF);
 234
 235         conf &= ~(GSCGPIO_CONF_OUTPUTEN | GSCGPIO_CONF_PUSHPULL |
 236             GSCGPIO_CONF_PULLUP);
 237         if ((flags & GPIO_PIN_TRISTATE) == 0)
 238                 conf |= GSCGPIO_CONF_OUTPUTEN;
 239         if (flags & GPIO_PIN_PUSHPULL)
 240                 conf |= GSCGPIO_CONF_PUSHPULL;
 241         if (flags & GPIO_PIN_PULLUP)
 242                 conf |= GSCGPIO_CONF_PULLUP;
 243         bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh,
 244             GSCGPIO_CONF, conf);
 245 }