1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2010 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
53 * Flags that go into the `segment' field of `insn' structures
56 #define SEG_RELATIVE 1
63 #define SEG_SIGNED 128
70 uint8_t osize
; /* Operand size */
71 uint8_t asize
; /* Address size */
72 uint8_t osp
; /* Operand size prefix present */
73 uint8_t asp
; /* Address size prefix present */
74 uint8_t rep
; /* Rep prefix present */
75 uint8_t seg
; /* Segment override prefix present */
76 uint8_t wait
; /* WAIT "prefix" present */
77 uint8_t lock
; /* Lock prefix present */
78 uint8_t vex
[3]; /* VEX prefix present */
79 uint8_t vex_c
; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m
; /* VEX.M field */
82 uint8_t vex_lp
; /* VEX.LP fields */
83 uint32_t rex
; /* REX prefix present */
86 #define getu8(x) (*(uint8_t *)(x))
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
93 static uint16_t getu16(uint8_t *data
)
95 return (uint16_t)data
[0] + ((uint16_t)data
[1] << 8);
97 static uint32_t getu32(uint8_t *data
)
99 return (uint32_t)getu16(data
) + ((uint32_t)getu16(data
+2) << 16);
101 static uint64_t getu64(uint8_t *data
)
103 return (uint64_t)getu32(data
) + ((uint64_t)getu32(data
+4) << 32);
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum
whichreg(opflags_t regflags
, int regval
, int rex
)
115 if (!(regflags
& (REGISTER
|REGMEM
)))
116 return 0; /* Registers not permissible?! */
118 regflags
|= REGISTER
;
120 if (!(REG_AL
& ~regflags
))
122 if (!(REG_AX
& ~regflags
))
124 if (!(REG_EAX
& ~regflags
))
126 if (!(REG_RAX
& ~regflags
))
128 if (!(REG_DL
& ~regflags
))
130 if (!(REG_DX
& ~regflags
))
132 if (!(REG_EDX
& ~regflags
))
134 if (!(REG_RDX
& ~regflags
))
136 if (!(REG_CL
& ~regflags
))
138 if (!(REG_CX
& ~regflags
))
140 if (!(REG_ECX
& ~regflags
))
142 if (!(REG_RCX
& ~regflags
))
144 if (!(FPU0
& ~regflags
))
146 if (!(XMM0
& ~regflags
))
148 if (!(YMM0
& ~regflags
))
150 if (!(REG_CS
& ~regflags
))
151 return (regval
== 1) ? R_CS
: 0;
152 if (!(REG_DESS
& ~regflags
))
153 return (regval
== 0 || regval
== 2
154 || regval
== 3 ? nasm_rd_sreg
[regval
] : 0);
155 if (!(REG_FSGS
& ~regflags
))
156 return (regval
== 4 || regval
== 5 ? nasm_rd_sreg
[regval
] : 0);
157 if (!(REG_SEG67
& ~regflags
))
158 return (regval
== 6 || regval
== 7 ? nasm_rd_sreg
[regval
] : 0);
160 /* All the entries below look up regval in an 16-entry array */
161 if (regval
< 0 || regval
> 15)
164 if (!(REG8
& ~regflags
)) {
165 if (rex
& (REX_P
|REX_NH
))
166 return nasm_rd_reg8_rex
[regval
];
168 return nasm_rd_reg8
[regval
];
170 if (!(REG16
& ~regflags
))
171 return nasm_rd_reg16
[regval
];
172 if (!(REG32
& ~regflags
))
173 return nasm_rd_reg32
[regval
];
174 if (!(REG64
& ~regflags
))
175 return nasm_rd_reg64
[regval
];
176 if (!(REG_SREG
& ~regflags
))
177 return nasm_rd_sreg
[regval
& 7]; /* Ignore REX */
178 if (!(REG_CREG
& ~regflags
))
179 return nasm_rd_creg
[regval
];
180 if (!(REG_DREG
& ~regflags
))
181 return nasm_rd_dreg
[regval
];
182 if (!(REG_TREG
& ~regflags
)) {
184 return 0; /* TR registers are ill-defined with rex */
185 return nasm_rd_treg
[regval
];
187 if (!(FPUREG
& ~regflags
))
188 return nasm_rd_fpureg
[regval
& 7]; /* Ignore REX */
189 if (!(MMXREG
& ~regflags
))
190 return nasm_rd_mmxreg
[regval
& 7]; /* Ignore REX */
191 if (!(XMMREG
& ~regflags
))
192 return nasm_rd_xmmreg
[regval
];
193 if (!(YMMREG
& ~regflags
))
194 return nasm_rd_ymmreg
[regval
];
200 * Process an effective address (ModRM) specification.
202 static uint8_t *do_ea(uint8_t *data
, int modrm
, int asize
,
203 int segsize
, enum ea_type type
,
204 operand
*op
, insn
*ins
)
206 int mod
, rm
, scale
, index
, base
;
210 mod
= (modrm
>> 6) & 03;
213 if (mod
!= 3 && asize
!= 16 && rm
== 4)
218 if (mod
== 3) { /* pure register version */
219 op
->basereg
= rm
+(rex
& REX_B
? 8 : 0);
220 op
->segment
|= SEG_RMREG
;
229 * <mod> specifies the displacement size (none, byte or
230 * word), and <rm> specifies the register combination.
231 * Exception: mod=0,rm=6 does not specify [BP] as one might
232 * expect, but instead specifies [disp16].
235 if (type
!= EA_SCALAR
)
238 op
->indexreg
= op
->basereg
= -1;
239 op
->scale
= 1; /* always, in 16 bits */
270 if (rm
== 6 && mod
== 0) { /* special case */
274 mod
= 2; /* fake disp16 */
278 op
->segment
|= SEG_NODISP
;
281 op
->segment
|= SEG_DISP8
;
282 op
->offset
= (int8_t)*data
++;
285 op
->segment
|= SEG_DISP16
;
286 op
->offset
= *data
++;
287 op
->offset
|= ((unsigned)*data
++) << 8;
293 * Once again, <mod> specifies displacement size (this time
294 * none, byte or *dword*), while <rm> specifies the base
295 * register. Again, [EBP] is missing, replaced by a pure
296 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
297 * and RIP-relative addressing in 64-bit mode.
300 * indicates not a single base register, but instead the
301 * presence of a SIB byte...
303 int a64
= asize
== 64;
308 op
->basereg
= nasm_rd_reg64
[rm
| ((rex
& REX_B
) ? 8 : 0)];
310 op
->basereg
= nasm_rd_reg32
[rm
| ((rex
& REX_B
) ? 8 : 0)];
312 if (rm
== 5 && mod
== 0) {
314 op
->eaflags
|= EAF_REL
;
315 op
->segment
|= SEG_RELATIVE
;
316 mod
= 2; /* fake disp32 */
320 op
->disp_size
= asize
;
323 mod
= 2; /* fake disp32 */
327 if (rm
== 4) { /* process SIB */
328 scale
= (sib
>> 6) & 03;
329 index
= (sib
>> 3) & 07;
332 op
->scale
= 1 << scale
;
334 if (index
== 4 && !(rex
& REX_X
))
335 op
->indexreg
= -1; /* ESP/RSP cannot be an index */
336 else if (type
== EA_XMMVSIB
)
337 op
->indexreg
= nasm_rd_xmmreg
[index
| ((rex
& REX_X
) ? 8 : 0)];
338 else if (type
== EA_YMMVSIB
)
339 op
->indexreg
= nasm_rd_ymmreg
[index
| ((rex
& REX_X
) ? 8 : 0)];
341 op
->indexreg
= nasm_rd_reg64
[index
| ((rex
& REX_X
) ? 8 : 0)];
343 op
->indexreg
= nasm_rd_reg32
[index
| ((rex
& REX_X
) ? 8 : 0)];
345 if (base
== 5 && mod
== 0) {
347 mod
= 2; /* Fake disp32 */
349 op
->basereg
= nasm_rd_reg64
[base
| ((rex
& REX_B
) ? 8 : 0)];
351 op
->basereg
= nasm_rd_reg32
[base
| ((rex
& REX_B
) ? 8 : 0)];
355 } else if (type
!= EA_SCALAR
) {
356 /* Can't have VSIB without SIB */
362 op
->segment
|= SEG_NODISP
;
365 op
->segment
|= SEG_DISP8
;
366 op
->offset
= gets8(data
);
370 op
->segment
|= SEG_DISP32
;
371 op
->offset
= gets32(data
);
380 * Determine whether the instruction template in t corresponds to the data
381 * stream in data. Return the number of bytes matched if so.
383 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
385 static int matches(const struct itemplate
*t
, uint8_t *data
,
386 const struct prefix_info
*prefix
, int segsize
, insn
*ins
)
388 uint8_t *r
= (uint8_t *)(t
->code
);
389 uint8_t *origdata
= data
;
390 bool a_used
= false, o_used
= false;
391 enum prefixes drep
= 0;
392 enum prefixes dwait
= 0;
393 uint8_t lock
= prefix
->lock
;
394 int osize
= prefix
->osize
;
395 int asize
= prefix
->asize
;
398 struct operand
*opx
, *opy
;
400 int s_field_for
= -1; /* No 144/154 series code encountered */
402 int regmask
= (segsize
== 64) ? 15 : 7;
403 enum ea_type eat
= EA_SCALAR
;
405 for (i
= 0; i
< MAX_OPERANDS
; i
++) {
406 ins
->oprs
[i
].segment
= ins
->oprs
[i
].disp_size
=
407 (segsize
== 64 ? SEG_64BIT
: segsize
== 32 ? SEG_32BIT
: 0);
410 ins
->rex
= prefix
->rex
;
411 memset(ins
->prefixes
, 0, sizeof ins
->prefixes
);
413 if (t
->flags
& (segsize
== 64 ? IF_NOLONG
: IF_LONG
))
416 if (prefix
->rep
== 0xF2)
418 else if (prefix
->rep
== 0xF3)
421 dwait
= prefix
->wait
? P_WAIT
: 0;
423 while ((c
= *r
++) != 0) {
424 op1
= (c
& 3) + ((opex
& 1) << 2);
425 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
426 opx
= &ins
->oprs
[op1
];
427 opy
= &ins
->oprs
[op2
];
448 int t
= *r
++, d
= *data
++;
449 if (d
< t
|| d
> t
+ 7)
452 opx
->basereg
= (d
-t
)+
453 (ins
->rex
& REX_B
? 8 : 0);
454 opx
->segment
|= SEG_RMREG
;
461 opx
->offset
= (int8_t)*data
++;
462 opx
->segment
|= SEG_SIGNED
;
466 opx
->offset
= *data
++;
470 opx
->offset
= *data
++;
474 opx
->offset
= getu16(data
);
480 opx
->offset
= getu32(data
);
483 opx
->offset
= getu16(data
);
486 if (segsize
!= asize
)
487 opx
->disp_size
= asize
;
492 opx
->offset
= getu32(data
);
499 opx
->offset
= getu16(data
);
505 opx
->offset
= getu32(data
);
511 opx
->offset
= getu64(data
);
519 opx
->offset
= gets8(data
++);
520 opx
->segment
|= SEG_RELATIVE
;
524 opx
->offset
= getu64(data
);
529 opx
->offset
= gets16(data
);
531 opx
->segment
|= SEG_RELATIVE
;
532 opx
->segment
&= ~SEG_32BIT
;
536 opx
->segment
|= SEG_RELATIVE
;
538 opx
->offset
= gets16(data
);
540 opx
->segment
&= ~(SEG_32BIT
|SEG_64BIT
);
541 } else if (osize
== 32) {
542 opx
->offset
= gets32(data
);
544 opx
->segment
&= ~SEG_64BIT
;
545 opx
->segment
|= SEG_32BIT
;
547 if (segsize
!= osize
) {
549 (opx
->type
& ~SIZE_MASK
)
550 | ((osize
== 16) ? BITS16
: BITS32
);
555 opx
->offset
= gets32(data
);
557 opx
->segment
|= SEG_32BIT
| SEG_RELATIVE
;
566 opx
->segment
|= SEG_RMREG
;
567 data
= do_ea(data
, modrm
, asize
, segsize
, eat
, opy
, ins
);
570 opx
->basereg
= ((modrm
>> 3) & 7) + (ins
->rex
& REX_R
? 8 : 0);
575 if (s_field_for
== op1
) {
576 opx
->offset
= gets8(data
);
579 opx
->offset
= getu16(data
);
586 s_field_for
= (*data
& 0x02) ? op1
: -1;
587 if ((*data
++ & ~0x02) != *r
++)
592 if (s_field_for
== op1
) {
593 opx
->offset
= gets8(data
);
596 opx
->offset
= getu32(data
);
603 uint8_t ximm
= *data
++;
605 ins
->oprs
[c
>> 3].basereg
= (ximm
>> 4) & regmask
;
606 ins
->oprs
[c
>> 3].segment
|= SEG_RMREG
;
607 ins
->oprs
[c
& 7].offset
= ximm
& 15;
613 uint8_t ximm
= *data
++;
619 ins
->oprs
[c
>> 4].basereg
= (ximm
>> 4) & regmask
;
620 ins
->oprs
[c
>> 4].segment
|= SEG_RMREG
;
626 uint8_t ximm
= *data
++;
629 ins
->oprs
[c
].basereg
= (ximm
>> 4) & regmask
;
630 ins
->oprs
[c
].segment
|= SEG_RMREG
;
644 if (((modrm
>> 3) & 07) != (c
& 07))
645 return false; /* spare field doesn't match up */
646 data
= do_ea(data
, modrm
, asize
, segsize
, eat
, opy
, ins
);
653 if (s_field_for
== op1
) {
654 opx
->offset
= gets8(data
);
657 opx
->offset
= gets32(data
);
669 if ((prefix
->rex
& (REX_V
|REX_P
)) != REX_V
)
672 if ((vexm
& 0x1f) != prefix
->vex_m
)
675 switch (vexwlp
& 060) {
677 if (prefix
->rex
& REX_W
)
681 if (!(prefix
->rex
& REX_W
))
685 case 040: /* VEX.W is a don't care */
692 /* The 010 bit of vexwlp is set if VEX.L is ignored */
693 if ((vexwlp
^ prefix
->vex_lp
) & ((vexwlp
& 010) ? 03 : 07))
697 if (prefix
->vex_v
!= 0)
700 opx
->segment
|= SEG_RMREG
;
701 opx
->basereg
= prefix
->vex_v
;
722 if (asize
!= segsize
)
736 if (prefix
->rex
& REX_B
)
741 if (prefix
->rex
& REX_X
)
746 if (prefix
->rex
& REX_R
)
751 if (prefix
->rex
& REX_W
)
770 if (osize
!= (segsize
== 16) ? 16 : 32)
777 ins
->rex
|= REX_W
; /* 64-bit only instruction */
794 int t
= *r
++, d
= *data
++;
795 if (d
< t
|| d
> t
+ 15)
798 ins
->condition
= d
- t
;
808 if (prefix
->rep
!= 0xF2)
814 if (prefix
->rep
!= 0xF3)
839 if (prefix
->wait
!= 0x9B)
845 ins
->oprs
[0].basereg
= (*data
++ >> 3) & 7;
849 if (prefix
->osp
|| prefix
->rep
)
854 if (!prefix
->osp
|| prefix
->rep
)
860 if (prefix
->osp
|| prefix
->rep
!= 0xf2)
866 if (prefix
->osp
|| prefix
->rep
!= 0xf3)
902 return false; /* Unknown code */
906 if (!vex_ok
&& (ins
->rex
& REX_V
))
909 /* REX cannot be combined with VEX */
910 if ((ins
->rex
& REX_V
) && (prefix
->rex
& REX_P
))
914 * Check for unused rep or a/o prefixes.
916 for (i
= 0; i
< t
->operands
; i
++) {
917 if (ins
->oprs
[i
].segment
!= SEG_RMREG
)
922 if (ins
->prefixes
[PPS_LREP
])
924 ins
->prefixes
[PPS_LREP
] = P_LOCK
;
927 if (ins
->prefixes
[PPS_LREP
])
929 ins
->prefixes
[PPS_LREP
] = drep
;
931 ins
->prefixes
[PPS_WAIT
] = dwait
;
933 if (osize
!= ((segsize
== 16) ? 16 : 32)) {
934 enum prefixes pfx
= 0;
948 if (ins
->prefixes
[PPS_OSIZE
])
950 ins
->prefixes
[PPS_OSIZE
] = pfx
;
953 if (!a_used
&& asize
!= segsize
) {
954 if (ins
->prefixes
[PPS_ASIZE
])
956 ins
->prefixes
[PPS_ASIZE
] = asize
== 16 ? P_A16
: P_A32
;
959 /* Fix: check for redundant REX prefixes */
961 return data
- origdata
;
964 /* Condition names for disassembly, sorted by x86 code */
965 static const char * const condition_name
[16] = {
966 "o", "no", "c", "nc", "z", "nz", "na", "a",
967 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
970 int32_t disasm(uint8_t *data
, char *output
, int outbufsize
, int segsize
,
971 int32_t offset
, int autosync
, uint32_t prefer
)
973 const struct itemplate
* const *p
, * const *best_p
;
974 const struct disasm_index
*ix
;
976 int length
, best_length
= 0;
978 int i
, slen
, colon
, n
;
982 uint32_t goodness
, best
;
984 struct prefix_info prefix
;
987 memset(&ins
, 0, sizeof ins
);
992 memset(&prefix
, 0, sizeof prefix
);
993 prefix
.asize
= segsize
;
994 prefix
.osize
= (segsize
== 64) ? 32 : segsize
;
1001 while (!end_prefix
) {
1005 prefix
.rep
= *data
++;
1009 prefix
.wait
= *data
++;
1013 prefix
.lock
= *data
++;
1017 segover
= "cs", prefix
.seg
= *data
++;
1020 segover
= "ss", prefix
.seg
= *data
++;
1023 segover
= "ds", prefix
.seg
= *data
++;
1026 segover
= "es", prefix
.seg
= *data
++;
1029 segover
= "fs", prefix
.seg
= *data
++;
1032 segover
= "gs", prefix
.seg
= *data
++;
1036 prefix
.osize
= (segsize
== 16) ? 32 : 16;
1037 prefix
.osp
= *data
++;
1040 prefix
.asize
= (segsize
== 32) ? 16 : 32;
1041 prefix
.asp
= *data
++;
1046 if (segsize
== 64 || (data
[1] & 0xc0) == 0xc0) {
1047 prefix
.vex
[0] = *data
++;
1048 prefix
.vex
[1] = *data
++;
1051 prefix
.vex_c
= RV_VEX
;
1053 if (prefix
.vex
[0] == 0xc4) {
1054 prefix
.vex
[2] = *data
++;
1055 prefix
.rex
|= (~prefix
.vex
[1] >> 5) & 7; /* REX_RXB */
1056 prefix
.rex
|= (prefix
.vex
[2] >> (7-3)) & REX_W
;
1057 prefix
.vex_m
= prefix
.vex
[1] & 0x1f;
1058 prefix
.vex_v
= (~prefix
.vex
[2] >> 3) & 15;
1059 prefix
.vex_lp
= prefix
.vex
[2] & 7;
1061 prefix
.rex
|= (~prefix
.vex
[1] >> (7-2)) & REX_R
;
1063 prefix
.vex_v
= (~prefix
.vex
[1] >> 3) & 15;
1064 prefix
.vex_lp
= prefix
.vex
[1] & 7;
1067 ix
= itable_vex
[RV_VEX
][prefix
.vex_m
][prefix
.vex_lp
& 3];
1073 if ((data
[1] & 030) != 0 &&
1074 (segsize
== 64 || (data
[1] & 0xc0) == 0xc0)) {
1075 prefix
.vex
[0] = *data
++;
1076 prefix
.vex
[1] = *data
++;
1077 prefix
.vex
[2] = *data
++;
1080 prefix
.vex_c
= RV_XOP
;
1082 prefix
.rex
|= (~prefix
.vex
[1] >> 5) & 7; /* REX_RXB */
1083 prefix
.rex
|= (prefix
.vex
[2] >> (7-3)) & REX_W
;
1084 prefix
.vex_m
= prefix
.vex
[1] & 0x1f;
1085 prefix
.vex_v
= (~prefix
.vex
[2] >> 3) & 15;
1086 prefix
.vex_lp
= prefix
.vex
[2] & 7;
1088 ix
= itable_vex
[RV_XOP
][prefix
.vex_m
][prefix
.vex_lp
& 3];
1109 if (segsize
== 64) {
1110 prefix
.rex
= *data
++;
1111 if (prefix
.rex
& REX_W
)
1123 best
= -1; /* Worst possible */
1125 best_pref
= INT_MAX
;
1128 return 0; /* No instruction table at all... */
1132 while (ix
->n
== -1) {
1133 ix
= (const struct disasm_index
*)ix
->p
+ *dp
++;
1136 p
= (const struct itemplate
* const *)ix
->p
;
1137 for (n
= ix
->n
; n
; n
--, p
++) {
1138 if ((length
= matches(*p
, data
, &prefix
, segsize
, &tmp_ins
))) {
1141 * Final check to make sure the types of r/m match up.
1142 * XXX: Need to make sure this is actually correct.
1144 for (i
= 0; i
< (*p
)->operands
; i
++) {
1145 if (!((*p
)->opd
[i
] & SAME_AS
) &&
1147 /* If it's a mem-only EA but we have a
1149 ((tmp_ins
.oprs
[i
].segment
& SEG_RMREG
) &&
1150 is_class(MEMORY
, (*p
)->opd
[i
])) ||
1151 /* If it's a reg-only EA but we have a memory
1153 (!(tmp_ins
.oprs
[i
].segment
& SEG_RMREG
) &&
1154 !(REG_EA
& ~(*p
)->opd
[i
]) &&
1155 !((*p
)->opd
[i
] & REG_SMASK
)) ||
1156 /* Register type mismatch (eg FS vs REG_DESS):
1158 ((((*p
)->opd
[i
] & (REGISTER
| FPUREG
)) ||
1159 (tmp_ins
.oprs
[i
].segment
& SEG_RMREG
)) &&
1160 !whichreg((*p
)->opd
[i
],
1161 tmp_ins
.oprs
[i
].basereg
, tmp_ins
.rex
))
1169 * Note: we always prefer instructions which incorporate
1170 * prefixes in the instructions themselves. This is to allow
1171 * e.g. PAUSE to be preferred to REP NOP, and deal with
1172 * MMX/SSE instructions where prefixes are used to select
1173 * between MMX and SSE register sets or outright opcode
1178 goodness
= ((*p
)->flags
& IF_PFMASK
) ^ prefer
;
1180 for (i
= 0; i
< MAXPREFIX
; i
++)
1181 if (tmp_ins
.prefixes
[i
])
1183 if (nprefix
< best_pref
||
1184 (nprefix
== best_pref
&& goodness
< best
)) {
1185 /* This is the best one found so far */
1188 best_pref
= nprefix
;
1189 best_length
= length
;
1197 return 0; /* no instruction was matched */
1199 /* Pick the best match */
1201 length
= best_length
;
1205 /* TODO: snprintf returns the value that the string would have if
1206 * the buffer were long enough, and not the actual length of
1207 * the returned string, so each instance of using the return
1208 * value of snprintf should actually be checked to assure that
1209 * the return value is "sane." Maybe a macro wrapper could
1210 * be used for that purpose.
1212 for (i
= 0; i
< MAXPREFIX
; i
++) {
1213 const char *prefix
= prefix_name(ins
.prefixes
[i
]);
1215 slen
+= snprintf(output
+slen
, outbufsize
-slen
, "%s ", prefix
);
1219 if (i
>= FIRST_COND_OPCODE
)
1220 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s%s",
1221 nasm_insn_names
[i
], condition_name
[ins
.condition
]);
1223 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
1224 nasm_insn_names
[i
]);
1227 length
+= data
- origdata
; /* fix up for prefixes */
1228 for (i
= 0; i
< (*p
)->operands
; i
++) {
1229 opflags_t t
= (*p
)->opd
[i
];
1230 const operand
*o
= &ins
.oprs
[i
];
1234 o
= &ins
.oprs
[t
& ~SAME_AS
];
1235 t
= (*p
)->opd
[t
& ~SAME_AS
];
1238 output
[slen
++] = (colon
? ':' : i
== 0 ? ' ' : ',');
1241 if (o
->segment
& SEG_RELATIVE
) {
1242 offs
+= offset
+ length
;
1244 * sort out wraparound
1246 if (!(o
->segment
& (SEG_32BIT
|SEG_64BIT
)))
1248 else if (segsize
!= 64)
1252 * add sync marker, if autosync is on
1263 if ((t
& (REGISTER
| FPUREG
)) ||
1264 (o
->segment
& SEG_RMREG
)) {
1266 reg
= whichreg(t
, o
->basereg
, ins
.rex
);
1268 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "to ");
1269 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
1270 nasm_reg_names
[reg
-EXPR_REG_START
]);
1271 } else if (!(UNITY
& ~t
)) {
1272 output
[slen
++] = '1';
1273 } else if (t
& IMMEDIATE
) {
1276 snprintf(output
+ slen
, outbufsize
- slen
, "byte ");
1277 if (o
->segment
& SEG_SIGNED
) {
1280 output
[slen
++] = '-';
1282 output
[slen
++] = '+';
1284 } else if (t
& BITS16
) {
1286 snprintf(output
+ slen
, outbufsize
- slen
, "word ");
1287 } else if (t
& BITS32
) {
1289 snprintf(output
+ slen
, outbufsize
- slen
, "dword ");
1290 } else if (t
& BITS64
) {
1292 snprintf(output
+ slen
, outbufsize
- slen
, "qword ");
1293 } else if (t
& NEAR
) {
1295 snprintf(output
+ slen
, outbufsize
- slen
, "near ");
1296 } else if (t
& SHORT
) {
1298 snprintf(output
+ slen
, outbufsize
- slen
, "short ");
1301 snprintf(output
+ slen
, outbufsize
- slen
, "0x%"PRIx64
"",
1303 } else if (!(MEM_OFFS
& ~t
)) {
1305 snprintf(output
+ slen
, outbufsize
- slen
,
1306 "[%s%s%s0x%"PRIx64
"]",
1307 (segover
? segover
: ""),
1308 (segover
? ":" : ""),
1309 (o
->disp_size
== 64 ? "qword " :
1310 o
->disp_size
== 32 ? "dword " :
1311 o
->disp_size
== 16 ? "word " : ""), offs
);
1313 } else if (is_class(REGMEM
, t
)) {
1314 int started
= false;
1317 snprintf(output
+ slen
, outbufsize
- slen
, "byte ");
1320 snprintf(output
+ slen
, outbufsize
- slen
, "word ");
1323 snprintf(output
+ slen
, outbufsize
- slen
, "dword ");
1326 snprintf(output
+ slen
, outbufsize
- slen
, "qword ");
1329 snprintf(output
+ slen
, outbufsize
- slen
, "tword ");
1332 snprintf(output
+ slen
, outbufsize
- slen
, "oword ");
1335 snprintf(output
+ slen
, outbufsize
- slen
, "yword ");
1337 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "far ");
1340 snprintf(output
+ slen
, outbufsize
- slen
, "near ");
1341 output
[slen
++] = '[';
1343 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
1344 (o
->disp_size
== 64 ? "qword " :
1345 o
->disp_size
== 32 ? "dword " :
1346 o
->disp_size
== 16 ? "word " :
1348 if (o
->eaflags
& EAF_REL
)
1349 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "rel ");
1352 snprintf(output
+ slen
, outbufsize
- slen
, "%s:",
1356 if (o
->basereg
!= -1) {
1357 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
1358 nasm_reg_names
[(o
->basereg
-EXPR_REG_START
)]);
1361 if (o
->indexreg
!= -1) {
1363 output
[slen
++] = '+';
1364 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
1365 nasm_reg_names
[(o
->indexreg
-EXPR_REG_START
)]);
1368 snprintf(output
+ slen
, outbufsize
- slen
, "*%d",
1374 if (o
->segment
& SEG_DISP8
) {
1376 uint8_t offset
= offs
;
1377 if ((int8_t)offset
< 0) {
1384 snprintf(output
+ slen
, outbufsize
- slen
, "%s0x%"PRIx8
"",
1386 } else if (o
->segment
& SEG_DISP16
) {
1388 uint16_t offset
= offs
;
1389 if ((int16_t)offset
< 0 && started
) {
1393 prefix
= started
? "+" : "";
1396 snprintf(output
+ slen
, outbufsize
- slen
,
1397 "%s0x%"PRIx16
"", prefix
, offset
);
1398 } else if (o
->segment
& SEG_DISP32
) {
1399 if (prefix
.asize
== 64) {
1401 uint64_t offset
= (int64_t)(int32_t)offs
;
1402 if ((int32_t)offs
< 0 && started
) {
1406 prefix
= started
? "+" : "";
1409 snprintf(output
+ slen
, outbufsize
- slen
,
1410 "%s0x%"PRIx64
"", prefix
, offset
);
1413 uint32_t offset
= offs
;
1414 if ((int32_t) offset
< 0 && started
) {
1418 prefix
= started
? "+" : "";
1421 snprintf(output
+ slen
, outbufsize
- slen
,
1422 "%s0x%"PRIx32
"", prefix
, offset
);
1425 output
[slen
++] = ']';
1428 snprintf(output
+ slen
, outbufsize
- slen
, "<operand%d>",
1432 output
[slen
] = '\0';
1433 if (segover
) { /* unused segment override */
1435 int count
= slen
+ 1;
1437 p
[count
+ 3] = p
[count
];
1438 strncpy(output
, segover
, 2);
1445 * This is called when we don't have a complete instruction. If it
1446 * is a standalone *single-byte* prefix show it as such, otherwise
1447 * print it as a literal.
1449 int32_t eatbyte(uint8_t *data
, char *output
, int outbufsize
, int segsize
)
1451 uint8_t byte
= *data
;
1452 const char *str
= NULL
;
1486 str
= (segsize
== 16) ? "o32" : "o16";
1489 str
= (segsize
== 32) ? "a16" : "a32";
1507 if (segsize
== 64) {
1508 snprintf(output
, outbufsize
, "rex%s%s%s%s%s",
1509 (byte
== REX_P
) ? "" : ".",
1510 (byte
& REX_W
) ? "w" : "",
1511 (byte
& REX_R
) ? "r" : "",
1512 (byte
& REX_X
) ? "x" : "",
1513 (byte
& REX_B
) ? "b" : "");
1516 /* else fall through */
1518 snprintf(output
, outbufsize
, "db 0x%02x", byte
);
1523 snprintf(output
, outbufsize
, "%s", str
);