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[nasm/nasm.git] / assemble.c
blob97c33d3a3fa333a9f344d2f31420274279344255
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2011 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - a signed byte immediate operand, from operand 0..3
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \140..\143 - an immediate word or signed byte for operand 0..3
64 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
65 * is a signed byte rather than a word. Opcode byte follows.
66 * \150..\153 - an immediate dword or signed byte for operand 0..3
67 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
68 * is a signed byte rather than a dword. Opcode byte follows.
69 * \172\ab - the register number from operand a in bits 7..4, with
70 * the 4-bit immediate from operand b in bits 3..0.
71 * \173\xab - the register number from operand a in bits 7..4, with
72 * the value b in bits 3..0.
73 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
74 * an arbitrary value in bits 3..0 (assembled as zero.)
75 * \2ab - a ModRM, calculated on EA in operand a, with the spare
76 * field equal to digit b.
77 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
78 * is not equal to the truncated and sign-extended 32-bit
79 * operand; used for 32-bit immediates in 64-bit mode.
80 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
81 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
82 * V field taken from operand 0..3.
83 * \270 - this instruction uses VEX/XOP rather than REX, with the
84 * V field set to 1111b.
85 *
86 * VEX/XOP prefixes are followed by the sequence:
87 * \tmm\wlp where mm is the M field; and wlp is:
88 * 00 wwl lpp
89 * [l0] ll = 0 for L = 0 (.128, .lz)
90 * [l1] ll = 1 for L = 1 (.256)
91 * [lig] ll = 2 for L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1 ] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
99 *
100 * \274..\277 - a signed byte immediate operand, from operand 0..3,
101 * which is to be extended to the operand size.
102 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
103 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
104 * \312 - (disassembler only) invalid with non-default address size.
105 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
106 * \314 - (disassembler only) invalid with REX.B
107 * \315 - (disassembler only) invalid with REX.X
108 * \316 - (disassembler only) invalid with REX.R
109 * \317 - (disassembler only) invalid with REX.W
110 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
111 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
112 * \322 - indicates that this instruction is only valid when the
113 * operand size is the default (instruction to disassembler,
114 * generates no code in the assembler)
115 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
116 * \324 - indicates 64-bit operand size requiring REX prefix.
117 * \325 - instruction which always uses spl/bpl/sil/dil
118 * \330 - a literal byte follows in the code stream, to be added
119 * to the condition code value of the instruction.
120 * \331 - instruction not valid with REP prefix. Hint for
121 * disassembler only; for SSE instructions.
122 * \332 - REP prefix (0xF2 byte) used as opcode extension.
123 * \333 - REP prefix (0xF3 byte) used as opcode extension.
124 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
125 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
126 * \336 - force a REP(E) prefix (0xF2) even if not specified.
127 * \337 - force a REPNE prefix (0xF3) even if not specified.
128 * \336-\337 are still listed as prefixes in the disassembler.
129 * \340 - reserve <operand 0> bytes of uninitialized storage.
130 * Operand 0 had better be a segmentless constant.
131 * \341 - this instruction needs a WAIT "prefix"
132 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
133 * (POP is never used for CS) depending on operand 0
134 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
135 * on operand 0
136 * \360 - no SSE prefix (== \364\331)
137 * \361 - 66 SSE prefix (== \366\331)
138 * \362 - F2 SSE prefix (== \364\332)
139 * \363 - F3 SSE prefix (== \364\333)
140 * \364 - operand-size prefix (0x66) not permitted
141 * \365 - address-size prefix (0x67) not permitted
142 * \366 - operand-size prefix (0x66) used as opcode extension
143 * \367 - address-size prefix (0x67) used as opcode extension
144 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
145 * 370 is used for Jcc, 371 is used for JMP.
146 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
147 * used for conditional jump over longer jump
148 * \374 - this instruction takes an XMM VSIB memory EA
149 * \375 - this instruction takes an YMM VSIB memory EA
150 */
151
152 #include "compiler.h"
153
154 #include <stdio.h>
155 #include <string.h>
156 #include <inttypes.h>
157
158 #include "nasm.h"
159 #include "nasmlib.h"
160 #include "assemble.h"
161 #include "insns.h"
162 #include "tables.h"
163
164 enum match_result {
165 /*
166 * Matching errors. These should be sorted so that more specific
167 * errors come later in the sequence.
168 */
169 MERR_INVALOP,
170 MERR_OPSIZEMISSING,
171 MERR_OPSIZEMISMATCH,
172 MERR_BADCPU,
173 MERR_BADMODE,
174 /*
175 * Matching success; the conditional ones first
176 */
177 MOK_JUMP, /* Matching OK but needs jmp_match() */
178 MOK_GOOD /* Matching unconditionally OK */
179 };
180
181 typedef struct {
182 enum ea_type type; /* what kind of EA is this? */
183 int sib_present; /* is a SIB byte necessary? */
184 int bytes; /* # of bytes of offset needed */
185 int size; /* lazy - this is sib+bytes+1 */
186 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
187 } ea;
188
189 static uint32_t cpu; /* cpu level received from nasm.c */
190 static efunc errfunc;
191 static struct ofmt *outfmt;
192 static ListGen *list;
193
194 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
195 static void gencode(int32_t segment, int64_t offset, int bits,
196 insn * ins, const struct itemplate *temp,
197 int64_t insn_end);
198 static enum match_result find_match(const struct itemplate **tempp,
199 insn *instruction,
200 int32_t segment, int64_t offset, int bits);
201 static enum match_result matches(const struct itemplate *, insn *, int bits);
202 static opflags_t regflag(const operand *);
203 static int32_t regval(const operand *);
204 static int rexflags(int, opflags_t, int);
205 static int op_rexflags(const operand *, int);
206 static void add_asp(insn *, int);
207
208 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
209
210 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
211 {
212 return ins->prefixes[pos] == prefix;
213 }
214
215 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
216 {
217 if (ins->prefixes[pos])
218 errfunc(ERR_NONFATAL, "invalid %s prefix",
219 prefix_name(ins->prefixes[pos]));
220 }
221
222 static const char *size_name(int size)
223 {
224 switch (size) {
225 case 1:
226 return "byte";
227 case 2:
228 return "word";
229 case 4:
230 return "dword";
231 case 8:
232 return "qword";
233 case 10:
234 return "tword";
235 case 16:
236 return "oword";
237 case 32:
238 return "yword";
239 default:
240 return "???";
241 }
242 }
243
244 static void warn_overflow(int pass, int size)
245 {
246 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
247 "%s data exceeds bounds", size_name(size));
248 }
249
250 static void warn_overflow_const(int64_t data, int size)
251 {
252 if (overflow_general(data, size))
253 warn_overflow(ERR_PASS1, size);
254 }
255
256 static void warn_overflow_opd(const struct operand *o, int size)
257 {
258 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
259 if (overflow_general(o->offset, size))
260 warn_overflow(ERR_PASS2, size);
261 }
262 }
263
264 /*
265 * This routine wrappers the real output format's output routine,
266 * in order to pass a copy of the data off to the listing file
267 * generator at the same time.
268 */
269 static void out(int64_t offset, int32_t segto, const void *data,
270 enum out_type type, uint64_t size,
271 int32_t segment, int32_t wrt)
272 {
273 static int32_t lineno = 0; /* static!!! */
274 static char *lnfname = NULL;
275 uint8_t p[8];
276
277 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
278 /*
279 * This is a non-relocated address, and we're going to
280 * convert it into RAWDATA format.
281 */
282 uint8_t *q = p;
283
284 if (size > 8) {
285 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
286 return;
287 }
288
289 WRITEADDR(q, *(int64_t *)data, size);
290 data = p;
291 type = OUT_RAWDATA;
292 }
293
294 list->output(offset, data, type, size);
295
296 /*
297 * this call to src_get determines when we call the
298 * debug-format-specific "linenum" function
299 * it updates lineno and lnfname to the current values
300 * returning 0 if "same as last time", -2 if lnfname
301 * changed, and the amount by which lineno changed,
302 * if it did. thus, these variables must be static
303 */
304
305 if (src_get(&lineno, &lnfname))
306 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
307
308 outfmt->output(segto, data, type, size, segment, wrt);
309 }
310
311 static bool jmp_match(int32_t segment, int64_t offset, int bits,
312 insn * ins, const uint8_t *code)
313 {
314 int64_t isize;
315 uint8_t c = code[0];
316
317 if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT))
318 return false;
319 if (!optimizing)
320 return false;
321 if (optimizing < 0 && c == 0371)
322 return false;
323
324 isize = calcsize(segment, offset, bits, ins, code);
325
326 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
327 /* Be optimistic in pass 1 */
328 return true;
329
330 if (ins->oprs[0].segment != segment)
331 return false;
332
333 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
334 return (isize >= -128 && isize <= 127); /* is it byte size? */
335 }
336
337 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
338 insn * instruction, struct ofmt *output, efunc error,
339 ListGen * listgen)
340 {
341 const struct itemplate *temp;
342 int j;
343 enum match_result m;
344 int64_t insn_end;
345 int32_t itimes;
346 int64_t start = offset;
347 int64_t wsize; /* size for DB etc. */
348
349 errfunc = error; /* to pass to other functions */
350 cpu = cp;
351 outfmt = output; /* likewise */
352 list = listgen; /* and again */
353
354 wsize = idata_bytes(instruction->opcode);
355 if (wsize == -1)
356 return 0;
357
358 if (wsize) {
359 extop *e;
360 int32_t t = instruction->times;
361 if (t < 0)
362 errfunc(ERR_PANIC,
363 "instruction->times < 0 (%ld) in assemble()", t);
364
365 while (t--) { /* repeat TIMES times */
366 list_for_each(e, instruction->eops) {
367 if (e->type == EOT_DB_NUMBER) {
368 if (wsize > 8) {
369 errfunc(ERR_NONFATAL,
370 "integer supplied to a DT, DO or DY"
371 " instruction");
372 } else {
373 out(offset, segment, &e->offset,
374 OUT_ADDRESS, wsize, e->segment, e->wrt);
375 offset += wsize;
376 }
377 } else if (e->type == EOT_DB_STRING ||
378 e->type == EOT_DB_STRING_FREE) {
379 int align;
380
381 out(offset, segment, e->stringval,
382 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
383 align = e->stringlen % wsize;
384
385 if (align) {
386 align = wsize - align;
387 out(offset, segment, zero_buffer,
388 OUT_RAWDATA, align, NO_SEG, NO_SEG);
389 }
390 offset += e->stringlen + align;
391 }
392 }
393 if (t > 0 && t == instruction->times - 1) {
394 /*
395 * Dummy call to list->output to give the offset to the
396 * listing module.
397 */
398 list->output(offset, NULL, OUT_RAWDATA, 0);
399 list->uplevel(LIST_TIMES);
400 }
401 }
402 if (instruction->times > 1)
403 list->downlevel(LIST_TIMES);
404 return offset - start;
405 }
406
407 if (instruction->opcode == I_INCBIN) {
408 const char *fname = instruction->eops->stringval;
409 FILE *fp;
410
411 fp = fopen(fname, "rb");
412 if (!fp) {
413 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
414 fname);
415 } else if (fseek(fp, 0L, SEEK_END) < 0) {
416 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
417 fname);
418 } else {
419 static char buf[4096];
420 size_t t = instruction->times;
421 size_t base = 0;
422 size_t len;
423
424 len = ftell(fp);
425 if (instruction->eops->next) {
426 base = instruction->eops->next->offset;
427 len -= base;
428 if (instruction->eops->next->next &&
429 len > (size_t)instruction->eops->next->next->offset)
430 len = (size_t)instruction->eops->next->next->offset;
431 }
432 /*
433 * Dummy call to list->output to give the offset to the
434 * listing module.
435 */
436 list->output(offset, NULL, OUT_RAWDATA, 0);
437 list->uplevel(LIST_INCBIN);
438 while (t--) {
439 size_t l;
440
441 fseek(fp, base, SEEK_SET);
442 l = len;
443 while (l > 0) {
444 int32_t m;
445 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
446 if (!m) {
447 /*
448 * This shouldn't happen unless the file
449 * actually changes while we are reading
450 * it.
451 */
452 error(ERR_NONFATAL,
453 "`incbin': unexpected EOF while"
454 " reading file `%s'", fname);
455 t = 0; /* Try to exit cleanly */
456 break;
457 }
458 out(offset, segment, buf, OUT_RAWDATA, m,
459 NO_SEG, NO_SEG);
460 l -= m;
461 }
462 }
463 list->downlevel(LIST_INCBIN);
464 if (instruction->times > 1) {
465 /*
466 * Dummy call to list->output to give the offset to the
467 * listing module.
468 */
469 list->output(offset, NULL, OUT_RAWDATA, 0);
470 list->uplevel(LIST_TIMES);
471 list->downlevel(LIST_TIMES);
472 }
473 fclose(fp);
474 return instruction->times * len;
475 }
476 return 0; /* if we're here, there's an error */
477 }
478
479 /* Check to see if we need an address-size prefix */
480 add_asp(instruction, bits);
481
482 m = find_match(&temp, instruction, segment, offset, bits);
483
484 if (m == MOK_GOOD) {
485 /* Matches! */
486 int64_t insn_size = calcsize(segment, offset, bits,
487 instruction, temp->code);
488 itimes = instruction->times;
489 if (insn_size < 0) /* shouldn't be, on pass two */
490 error(ERR_PANIC, "errors made it through from pass one");
491 else
492 while (itimes--) {
493 for (j = 0; j < MAXPREFIX; j++) {
494 uint8_t c = 0;
495 switch (instruction->prefixes[j]) {
496 case P_WAIT:
497 c = 0x9B;
498 break;
499 case P_LOCK:
500 c = 0xF0;
501 break;
502 case P_REPNE:
503 case P_REPNZ:
504 c = 0xF2;
505 break;
506 case P_REPE:
507 case P_REPZ:
508 case P_REP:
509 c = 0xF3;
510 break;
511 case R_CS:
512 if (bits == 64) {
513 error(ERR_WARNING | ERR_PASS2,
514 "cs segment base generated, but will be ignored in 64-bit mode");
515 }
516 c = 0x2E;
517 break;
518 case R_DS:
519 if (bits == 64) {
520 error(ERR_WARNING | ERR_PASS2,
521 "ds segment base generated, but will be ignored in 64-bit mode");
522 }
523 c = 0x3E;
524 break;
525 case R_ES:
526 if (bits == 64) {
527 error(ERR_WARNING | ERR_PASS2,
528 "es segment base generated, but will be ignored in 64-bit mode");
529 }
530 c = 0x26;
531 break;
532 case R_FS:
533 c = 0x64;
534 break;
535 case R_GS:
536 c = 0x65;
537 break;
538 case R_SS:
539 if (bits == 64) {
540 error(ERR_WARNING | ERR_PASS2,
541 "ss segment base generated, but will be ignored in 64-bit mode");
542 }
543 c = 0x36;
544 break;
545 case R_SEGR6:
546 case R_SEGR7:
547 error(ERR_NONFATAL,
548 "segr6 and segr7 cannot be used as prefixes");
549 break;
550 case P_A16:
551 if (bits == 64) {
552 error(ERR_NONFATAL,
553 "16-bit addressing is not supported "
554 "in 64-bit mode");
555 } else if (bits != 16)
556 c = 0x67;
557 break;
558 case P_A32:
559 if (bits != 32)
560 c = 0x67;
561 break;
562 case P_A64:
563 if (bits != 64) {
564 error(ERR_NONFATAL,
565 "64-bit addressing is only supported "
566 "in 64-bit mode");
567 }
568 break;
569 case P_ASP:
570 c = 0x67;
571 break;
572 case P_O16:
573 if (bits != 16)
574 c = 0x66;
575 break;
576 case P_O32:
577 if (bits == 16)
578 c = 0x66;
579 break;
580 case P_O64:
581 /* REX.W */
582 break;
583 case P_OSP:
584 c = 0x66;
585 break;
586 case P_none:
587 break;
588 default:
589 error(ERR_PANIC, "invalid instruction prefix");
590 }
591 if (c != 0) {
592 out(offset, segment, &c, OUT_RAWDATA, 1,
593 NO_SEG, NO_SEG);
594 offset++;
595 }
596 }
597 insn_end = offset + insn_size;
598 gencode(segment, offset, bits, instruction,
599 temp, insn_end);
600 offset += insn_size;
601 if (itimes > 0 && itimes == instruction->times - 1) {
602 /*
603 * Dummy call to list->output to give the offset to the
604 * listing module.
605 */
606 list->output(offset, NULL, OUT_RAWDATA, 0);
607 list->uplevel(LIST_TIMES);
608 }
609 }
610 if (instruction->times > 1)
611 list->downlevel(LIST_TIMES);
612 return offset - start;
613 } else {
614 /* No match */
615 switch (m) {
616 case MERR_OPSIZEMISSING:
617 error(ERR_NONFATAL, "operation size not specified");
618 break;
619 case MERR_OPSIZEMISMATCH:
620 error(ERR_NONFATAL, "mismatch in operand sizes");
621 break;
622 case MERR_BADCPU:
623 error(ERR_NONFATAL, "no instruction for this cpu level");
624 break;
625 case MERR_BADMODE:
626 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
627 bits);
628 break;
629 default:
630 error(ERR_NONFATAL,
631 "invalid combination of opcode and operands");
632 break;
633 }
634 }
635 return 0;
636 }
637
638 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
639 insn * instruction, efunc error)
640 {
641 const struct itemplate *temp;
642 enum match_result m;
643
644 errfunc = error; /* to pass to other functions */
645 cpu = cp;
646
647 if (instruction->opcode == I_none)
648 return 0;
649
650 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
651 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
652 instruction->opcode == I_DT || instruction->opcode == I_DO ||
653 instruction->opcode == I_DY) {
654 extop *e;
655 int32_t isize, osize, wsize;
656
657 isize = 0;
658 wsize = idata_bytes(instruction->opcode);
659
660 list_for_each(e, instruction->eops) {
661 int32_t align;
662
663 osize = 0;
664 if (e->type == EOT_DB_NUMBER) {
665 osize = 1;
666 warn_overflow_const(e->offset, wsize);
667 } else if (e->type == EOT_DB_STRING ||
668 e->type == EOT_DB_STRING_FREE)
669 osize = e->stringlen;
670
671 align = (-osize) % wsize;
672 if (align < 0)
673 align += wsize;
674 isize += osize + align;
675 }
676 return isize * instruction->times;
677 }
678
679 if (instruction->opcode == I_INCBIN) {
680 const char *fname = instruction->eops->stringval;
681 FILE *fp;
682 int64_t val = 0;
683 size_t len;
684
685 fp = fopen(fname, "rb");
686 if (!fp)
687 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
688 fname);
689 else if (fseek(fp, 0L, SEEK_END) < 0)
690 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
691 fname);
692 else {
693 len = ftell(fp);
694 if (instruction->eops->next) {
695 len -= instruction->eops->next->offset;
696 if (instruction->eops->next->next &&
697 len > (size_t)instruction->eops->next->next->offset) {
698 len = (size_t)instruction->eops->next->next->offset;
699 }
700 }
701 val = instruction->times * len;
702 }
703 if (fp)
704 fclose(fp);
705 return val;
706 }
707
708 /* Check to see if we need an address-size prefix */
709 add_asp(instruction, bits);
710
711 m = find_match(&temp, instruction, segment, offset, bits);
712 if (m == MOK_GOOD) {
713 /* we've matched an instruction. */
714 int64_t isize;
715 const uint8_t *codes = temp->code;
716 int j;
717
718 isize = calcsize(segment, offset, bits, instruction, codes);
719 if (isize < 0)
720 return -1;
721 for (j = 0; j < MAXPREFIX; j++) {
722 switch (instruction->prefixes[j]) {
723 case P_A16:
724 if (bits != 16)
725 isize++;
726 break;
727 case P_A32:
728 if (bits != 32)
729 isize++;
730 break;
731 case P_O16:
732 if (bits != 16)
733 isize++;
734 break;
735 case P_O32:
736 if (bits == 16)
737 isize++;
738 break;
739 case P_A64:
740 case P_O64:
741 case P_none:
742 break;
743 default:
744 isize++;
745 break;
746 }
747 }
748 return isize * instruction->times;
749 } else {
750 return -1; /* didn't match any instruction */
751 }
752 }
753
754 static bool possible_sbyte(operand *o)
755 {
756 return o->wrt == NO_SEG && o->segment == NO_SEG &&
757 !(o->opflags & OPFLAG_UNKNOWN) &&
758 optimizing >= 0 && !(o->type & STRICT);
759 }
760
761 /* check that opn[op] is a signed byte of size 16 or 32 */
762 static bool is_sbyte16(operand *o)
763 {
764 int16_t v;
765
766 if (!possible_sbyte(o))
767 return false;
768
769 v = o->offset;
770 return v >= -128 && v <= 127;
771 }
772
773 static bool is_sbyte32(operand *o)
774 {
775 int32_t v;
776
777 if (!possible_sbyte(o))
778 return false;
779
780 v = o->offset;
781 return v >= -128 && v <= 127;
782 }
783
784 /* Common construct */
785 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
786
787 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
788 insn * ins, const uint8_t *codes)
789 {
790 int64_t length = 0;
791 uint8_t c;
792 int rex_mask = ~0;
793 int op1, op2;
794 struct operand *opx;
795 uint8_t opex = 0;
796 enum ea_type eat;
797
798 ins->rex = 0; /* Ensure REX is reset */
799 eat = EA_SCALAR; /* Expect a scalar EA */
800
801 if (ins->prefixes[PPS_OSIZE] == P_O64)
802 ins->rex |= REX_W;
803
804 (void)segment; /* Don't warn that this parameter is unused */
805 (void)offset; /* Don't warn that this parameter is unused */
806
807 while (*codes) {
808 c = *codes++;
809 op1 = (c & 3) + ((opex & 1) << 2);
810 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
811 opx = &ins->oprs[op1];
812 opex = 0; /* For the next iteration */
813
814 switch (c) {
815 case 01:
816 case 02:
817 case 03:
818 case 04:
819 codes += c, length += c;
820 break;
821
822 case 05:
823 case 06:
824 case 07:
825 opex = c;
826 break;
827
828 case4(010):
829 ins->rex |=
830 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
831 codes++, length++;
832 break;
833
834 case4(014):
835 case4(020):
836 case4(024):
837 length++;
838 break;
839
840 case4(030):
841 length += 2;
842 break;
843
844 case4(034):
845 if (opx->type & (BITS16 | BITS32 | BITS64))
846 length += (opx->type & BITS16) ? 2 : 4;
847 else
848 length += (bits == 16) ? 2 : 4;
849 break;
850
851 case4(040):
852 length += 4;
853 break;
854
855 case4(044):
856 length += ins->addr_size >> 3;
857 break;
858
859 case4(050):
860 length++;
861 break;
862
863 case4(054):
864 length += 8; /* MOV reg64/imm */
865 break;
866
867 case4(060):
868 length += 2;
869 break;
870
871 case4(064):
872 if (opx->type & (BITS16 | BITS32 | BITS64))
873 length += (opx->type & BITS16) ? 2 : 4;
874 else
875 length += (bits == 16) ? 2 : 4;
876 break;
877
878 case4(070):
879 length += 4;
880 break;
881
882 case4(074):
883 length += 2;
884 break;
885
886 case4(0140):
887 length += is_sbyte16(opx) ? 1 : 2;
888 break;
889
890 case4(0144):
891 codes++;
892 length++;
893 break;
894
895 case4(0150):
896 length += is_sbyte32(opx) ? 1 : 4;
897 break;
898
899 case4(0154):
900 codes++;
901 length++;
902 break;
903
904 case 0172:
905 case 0173:
906 codes++;
907 length++;
908 break;
909
910 case4(0174):
911 length++;
912 break;
913
914 case4(0250):
915 length += is_sbyte32(opx) ? 1 : 4;
916 break;
917
918 case4(0254):
919 length += 4;
920 break;
921
922 case4(0260):
923 ins->rex |= REX_V;
924 ins->vexreg = regval(opx);
925 ins->vex_cm = *codes++;
926 ins->vex_wlp = *codes++;
927 break;
928
929 case 0270:
930 ins->rex |= REX_V;
931 ins->vexreg = 0;
932 ins->vex_cm = *codes++;
933 ins->vex_wlp = *codes++;
934 break;
935
936 case4(0274):
937 length++;
938 break;
939
940 case4(0300):
941 break;
942
943 case 0310:
944 if (bits == 64)
945 return -1;
946 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
947 break;
948
949 case 0311:
950 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
951 break;
952
953 case 0312:
954 break;
955
956 case 0313:
957 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
958 has_prefix(ins, PPS_ASIZE, P_A32))
959 return -1;
960 break;
961
962 case4(0314):
963 break;
964
965 case 0320:
966 {
967 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
968 if (pfx == P_O16)
969 break;
970 if (pfx != P_none)
971 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
972 else
973 ins->prefixes[PPS_OSIZE] = P_O16;
974 break;
975 }
976
977 case 0321:
978 {
979 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
980 if (pfx == P_O32)
981 break;
982 if (pfx != P_none)
983 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
984 else
985 ins->prefixes[PPS_OSIZE] = P_O32;
986 break;
987 }
988
989 case 0322:
990 break;
991
992 case 0323:
993 rex_mask &= ~REX_W;
994 break;
995
996 case 0324:
997 ins->rex |= REX_W;
998 break;
999
1000 case 0325:
1001 ins->rex |= REX_NH;
1002 break;
1003
1004 case 0330:
1005 codes++, length++;
1006 break;
1007
1008 case 0331:
1009 break;
1010
1011 case 0332:
1012 case 0333:
1013 length++;
1014 break;
1015
1016 case 0334:
1017 ins->rex |= REX_L;
1018 break;
1019
1020 case 0335:
1021 break;
1022
1023 case 0336:
1024 if (!ins->prefixes[PPS_LREP])
1025 ins->prefixes[PPS_LREP] = P_REP;
1026 break;
1027
1028 case 0337:
1029 if (!ins->prefixes[PPS_LREP])
1030 ins->prefixes[PPS_LREP] = P_REPNE;
1031 break;
1032
1033 case 0340:
1034 if (ins->oprs[0].segment != NO_SEG)
1035 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1036 " quantity of BSS space");
1037 else
1038 length += ins->oprs[0].offset;
1039 break;
1040
1041 case 0341:
1042 if (!ins->prefixes[PPS_WAIT])
1043 ins->prefixes[PPS_WAIT] = P_WAIT;
1044 break;
1045
1046 case4(0344):
1047 length++;
1048 break;
1049
1050 case 0360:
1051 break;
1052
1053 case 0361:
1054 case 0362:
1055 case 0363:
1056 length++;
1057 break;
1058
1059 case 0364:
1060 case 0365:
1061 break;
1062
1063 case 0366:
1064 case 0367:
1065 length++;
1066 break;
1067
1068 case 0370:
1069 case 0371:
1070 case 0372:
1071 break;
1072
1073 case 0373:
1074 length++;
1075 break;
1076
1077 case 0374:
1078 eat = EA_XMMVSIB;
1079 break;
1080
1081 case 0375:
1082 eat = EA_YMMVSIB;
1083 break;
1084
1085 case4(0100):
1086 case4(0110):
1087 case4(0120):
1088 case4(0130):
1089 case4(0200):
1090 case4(0204):
1091 case4(0210):
1092 case4(0214):
1093 case4(0220):
1094 case4(0224):
1095 case4(0230):
1096 case4(0234):
1097 {
1098 ea ea_data;
1099 int rfield;
1100 opflags_t rflags;
1101 struct operand *opy = &ins->oprs[op2];
1102
1103 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1104
1105 if (c <= 0177) {
1106 /* pick rfield from operand b (opx) */
1107 rflags = regflag(opx);
1108 rfield = nasm_regvals[opx->basereg];
1109 } else {
1110 rflags = 0;
1111 rfield = c & 7;
1112 }
1113 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1114 rfield, rflags) != eat) {
1115 errfunc(ERR_NONFATAL, "invalid effective address");
1116 return -1;
1117 } else {
1118 ins->rex |= ea_data.rex;
1119 length += ea_data.size;
1120 }
1121 }
1122 break;
1123
1124 default:
1125 errfunc(ERR_PANIC, "internal instruction table corrupt"
1126 ": instruction code \\%o (0x%02X) given", c, c);
1127 break;
1128 }
1129 }
1130
1131 ins->rex &= rex_mask;
1132
1133 if (ins->rex & REX_NH) {
1134 if (ins->rex & REX_H) {
1135 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1136 return -1;
1137 }
1138 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1139 }
1140
1141 if (ins->rex & REX_V) {
1142 int bad32 = REX_R|REX_W|REX_X|REX_B;
1143
1144 if (ins->rex & REX_H) {
1145 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1146 return -1;
1147 }
1148 switch (ins->vex_wlp & 060) {
1149 case 000:
1150 case 040:
1151 ins->rex &= ~REX_W;
1152 break;
1153 case 020:
1154 ins->rex |= REX_W;
1155 bad32 &= ~REX_W;
1156 break;
1157 case 060:
1158 /* Follow REX_W */
1159 break;
1160 }
1161
1162 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1163 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1164 return -1;
1165 }
1166 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1167 length += 3;
1168 else
1169 length += 2;
1170 } else if (ins->rex & REX_REAL) {
1171 if (ins->rex & REX_H) {
1172 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1173 return -1;
1174 } else if (bits == 64) {
1175 length++;
1176 } else if ((ins->rex & REX_L) &&
1177 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1178 cpu >= IF_X86_64) {
1179 /* LOCK-as-REX.R */
1180 assert_no_prefix(ins, PPS_LREP);
1181 length++;
1182 } else {
1183 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1184 return -1;
1185 }
1186 }
1187
1188 return length;
1189 }
1190
1191 #define EMIT_REX() \
1192 if (!(ins->rex & REX_V) && (ins->rex & REX_REAL) && (bits == 64)) { \
1193 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1194 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1195 ins->rex = 0; \
1196 offset += 1; \
1197 }
1198
1199 static void gencode(int32_t segment, int64_t offset, int bits,
1200 insn * ins, const struct itemplate *temp,
1201 int64_t insn_end)
1202 {
1203 static const char condval[] = { /* conditional opcodes */
1204 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1205 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1206 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1207 };
1208 uint8_t c;
1209 uint8_t bytes[4];
1210 int64_t size;
1211 int64_t data;
1212 int op1, op2;
1213 struct operand *opx;
1214 const uint8_t *codes = temp->code;
1215 uint8_t opex = 0;
1216 enum ea_type eat = EA_SCALAR;
1217
1218 while (*codes) {
1219 c = *codes++;
1220 op1 = (c & 3) + ((opex & 1) << 2);
1221 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1222 opx = &ins->oprs[op1];
1223 opex = 0; /* For the next iteration */
1224
1225 switch (c) {
1226 case 01:
1227 case 02:
1228 case 03:
1229 case 04:
1230 EMIT_REX();
1231 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1232 codes += c;
1233 offset += c;
1234 break;
1235
1236 case 05:
1237 case 06:
1238 case 07:
1239 opex = c;
1240 break;
1241
1242 case4(010):
1243 EMIT_REX();
1244 bytes[0] = *codes++ + (regval(opx) & 7);
1245 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1246 offset += 1;
1247 break;
1248
1249 case4(014):
1250 /*
1251 * The test for BITS8 and SBYTE here is intended to avoid
1252 * warning on optimizer actions due to SBYTE, while still
1253 * warn on explicit BYTE directives. Also warn, obviously,
1254 * if the optimizer isn't enabled.
1255 */
1256 if (((opx->type & BITS8) ||
1257 !(opx->type & temp->opd[op1] & BYTENESS)) &&
1258 (opx->offset < -128 || opx->offset > 127)) {
1259 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1260 "signed byte value exceeds bounds");
1261 }
1262 if (opx->segment != NO_SEG) {
1263 data = opx->offset;
1264 out(offset, segment, &data, OUT_ADDRESS, 1,
1265 opx->segment, opx->wrt);
1266 } else {
1267 bytes[0] = opx->offset;
1268 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1269 NO_SEG);
1270 }
1271 offset += 1;
1272 break;
1273
1274 case4(020):
1275 if (opx->offset < -256 || opx->offset > 255) {
1276 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1277 "byte value exceeds bounds");
1278 }
1279 if (opx->segment != NO_SEG) {
1280 data = opx->offset;
1281 out(offset, segment, &data, OUT_ADDRESS, 1,
1282 opx->segment, opx->wrt);
1283 } else {
1284 bytes[0] = opx->offset;
1285 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1286 NO_SEG);
1287 }
1288 offset += 1;
1289 break;
1290
1291 case4(024):
1292 if (opx->offset < 0 || opx->offset > 255)
1293 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1294 "unsigned byte value exceeds bounds");
1295 if (opx->segment != NO_SEG) {
1296 data = opx->offset;
1297 out(offset, segment, &data, OUT_ADDRESS, 1,
1298 opx->segment, opx->wrt);
1299 } else {
1300 bytes[0] = opx->offset;
1301 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1302 NO_SEG);
1303 }
1304 offset += 1;
1305 break;
1306
1307 case4(030):
1308 warn_overflow_opd(opx, 2);
1309 data = opx->offset;
1310 out(offset, segment, &data, OUT_ADDRESS, 2,
1311 opx->segment, opx->wrt);
1312 offset += 2;
1313 break;
1314
1315 case4(034):
1316 if (opx->type & (BITS16 | BITS32))
1317 size = (opx->type & BITS16) ? 2 : 4;
1318 else
1319 size = (bits == 16) ? 2 : 4;
1320 warn_overflow_opd(opx, size);
1321 data = opx->offset;
1322 out(offset, segment, &data, OUT_ADDRESS, size,
1323 opx->segment, opx->wrt);
1324 offset += size;
1325 break;
1326
1327 case4(040):
1328 warn_overflow_opd(opx, 4);
1329 data = opx->offset;
1330 out(offset, segment, &data, OUT_ADDRESS, 4,
1331 opx->segment, opx->wrt);
1332 offset += 4;
1333 break;
1334
1335 case4(044):
1336 data = opx->offset;
1337 size = ins->addr_size >> 3;
1338 warn_overflow_opd(opx, size);
1339 out(offset, segment, &data, OUT_ADDRESS, size,
1340 opx->segment, opx->wrt);
1341 offset += size;
1342 break;
1343
1344 case4(050):
1345 if (opx->segment != segment) {
1346 data = opx->offset;
1347 out(offset, segment, &data,
1348 OUT_REL1ADR, insn_end - offset,
1349 opx->segment, opx->wrt);
1350 } else {
1351 data = opx->offset - insn_end;
1352 if (data > 127 || data < -128)
1353 errfunc(ERR_NONFATAL, "short jump is out of range");
1354 out(offset, segment, &data,
1355 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1356 }
1357 offset += 1;
1358 break;
1359
1360 case4(054):
1361 data = (int64_t)opx->offset;
1362 out(offset, segment, &data, OUT_ADDRESS, 8,
1363 opx->segment, opx->wrt);
1364 offset += 8;
1365 break;
1366
1367 case4(060):
1368 if (opx->segment != segment) {
1369 data = opx->offset;
1370 out(offset, segment, &data,
1371 OUT_REL2ADR, insn_end - offset,
1372 opx->segment, opx->wrt);
1373 } else {
1374 data = opx->offset - insn_end;
1375 out(offset, segment, &data,
1376 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1377 }
1378 offset += 2;
1379 break;
1380
1381 case4(064):
1382 if (opx->type & (BITS16 | BITS32 | BITS64))
1383 size = (opx->type & BITS16) ? 2 : 4;
1384 else
1385 size = (bits == 16) ? 2 : 4;
1386 if (opx->segment != segment) {
1387 data = opx->offset;
1388 out(offset, segment, &data,
1389 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1390 insn_end - offset, opx->segment, opx->wrt);
1391 } else {
1392 data = opx->offset - insn_end;
1393 out(offset, segment, &data,
1394 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1395 }
1396 offset += size;
1397 break;
1398
1399 case4(070):
1400 if (opx->segment != segment) {
1401 data = opx->offset;
1402 out(offset, segment, &data,
1403 OUT_REL4ADR, insn_end - offset,
1404 opx->segment, opx->wrt);
1405 } else {
1406 data = opx->offset - insn_end;
1407 out(offset, segment, &data,
1408 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1409 }
1410 offset += 4;
1411 break;
1412
1413 case4(074):
1414 if (opx->segment == NO_SEG)
1415 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1416 " relocatable");
1417 data = 0;
1418 out(offset, segment, &data, OUT_ADDRESS, 2,
1419 outfmt->segbase(1 + opx->segment),
1420 opx->wrt);
1421 offset += 2;
1422 break;
1423
1424 case4(0140):
1425 data = opx->offset;
1426 warn_overflow_opd(opx, 2);
1427 if (is_sbyte16(opx)) {
1428 bytes[0] = data;
1429 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1430 NO_SEG);
1431 offset++;
1432 } else {
1433 out(offset, segment, &data, OUT_ADDRESS, 2,
1434 opx->segment, opx->wrt);
1435 offset += 2;
1436 }
1437 break;
1438
1439 case4(0144):
1440 EMIT_REX();
1441 bytes[0] = *codes++;
1442 if (is_sbyte16(opx))
1443 bytes[0] |= 2; /* s-bit */
1444 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1445 offset++;
1446 break;
1447
1448 case4(0150):
1449 data = opx->offset;
1450 warn_overflow_opd(opx, 4);
1451 if (is_sbyte32(opx)) {
1452 bytes[0] = data;
1453 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1454 NO_SEG);
1455 offset++;
1456 } else {
1457 out(offset, segment, &data, OUT_ADDRESS, 4,
1458 opx->segment, opx->wrt);
1459 offset += 4;
1460 }
1461 break;
1462
1463 case4(0154):
1464 EMIT_REX();
1465 bytes[0] = *codes++;
1466 if (is_sbyte32(opx))
1467 bytes[0] |= 2; /* s-bit */
1468 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1469 offset++;
1470 break;
1471
1472 case 0172:
1473 c = *codes++;
1474 opx = &ins->oprs[c >> 3];
1475 bytes[0] = nasm_regvals[opx->basereg] << 4;
1476 opx = &ins->oprs[c & 7];
1477 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1478 errfunc(ERR_NONFATAL,
1479 "non-absolute expression not permitted as argument %d",
1480 c & 7);
1481 } else {
1482 if (opx->offset & ~15) {
1483 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1484 "four-bit argument exceeds bounds");
1485 }
1486 bytes[0] |= opx->offset & 15;
1487 }
1488 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1489 offset++;
1490 break;
1491
1492 case 0173:
1493 c = *codes++;
1494 opx = &ins->oprs[c >> 4];
1495 bytes[0] = nasm_regvals[opx->basereg] << 4;
1496 bytes[0] |= c & 15;
1497 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1498 offset++;
1499 break;
1500
1501 case4(0174):
1502 bytes[0] = nasm_regvals[opx->basereg] << 4;
1503 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1504 offset++;
1505 break;
1506
1507 case4(0250):
1508 data = opx->offset;
1509 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1510 (int32_t)data != (int64_t)data) {
1511 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1512 "signed dword immediate exceeds bounds");
1513 }
1514 if (is_sbyte32(opx)) {
1515 bytes[0] = data;
1516 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1517 NO_SEG);
1518 offset++;
1519 } else {
1520 out(offset, segment, &data, OUT_ADDRESS, 4,
1521 opx->segment, opx->wrt);
1522 offset += 4;
1523 }
1524 break;
1525
1526 case4(0254):
1527 data = opx->offset;
1528 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1529 (int32_t)data != (int64_t)data) {
1530 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1531 "signed dword immediate exceeds bounds");
1532 }
1533 out(offset, segment, &data, OUT_ADDRESS, 4,
1534 opx->segment, opx->wrt);
1535 offset += 4;
1536 break;
1537
1538 case4(0260):
1539 case 0270:
1540 codes += 2;
1541 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1542 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1543 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1544 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1545 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1546 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1547 offset += 3;
1548 } else {
1549 bytes[0] = 0xc5;
1550 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1551 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1552 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1553 offset += 2;
1554 }
1555 break;
1556
1557 case4(0274):
1558 {
1559 uint64_t uv, um;
1560 int s;
1561
1562 if (ins->rex & REX_W)
1563 s = 64;
1564 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1565 s = 16;
1566 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1567 s = 32;
1568 else
1569 s = bits;
1570
1571 um = (uint64_t)2 << (s-1);
1572 uv = opx->offset;
1573
1574 if (uv > 127 && uv < (uint64_t)-128 &&
1575 (uv < um-128 || uv > um-1)) {
1576 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1577 "signed byte value exceeds bounds");
1578 }
1579 if (opx->segment != NO_SEG) {
1580 data = uv;
1581 out(offset, segment, &data, OUT_ADDRESS, 1,
1582 opx->segment, opx->wrt);
1583 } else {
1584 bytes[0] = uv;
1585 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1586 NO_SEG);
1587 }
1588 offset += 1;
1589 break;
1590 }
1591
1592 case4(0300):
1593 break;
1594
1595 case 0310:
1596 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1597 *bytes = 0x67;
1598 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1599 offset += 1;
1600 } else
1601 offset += 0;
1602 break;
1603
1604 case 0311:
1605 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1606 *bytes = 0x67;
1607 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1608 offset += 1;
1609 } else
1610 offset += 0;
1611 break;
1612
1613 case 0312:
1614 break;
1615
1616 case 0313:
1617 ins->rex = 0;
1618 break;
1619
1620 case4(0314):
1621 break;
1622
1623 case 0320:
1624 case 0321:
1625 break;
1626
1627 case 0322:
1628 case 0323:
1629 break;
1630
1631 case 0324:
1632 ins->rex |= REX_W;
1633 break;
1634
1635 case 0325:
1636 break;
1637
1638 case 0330:
1639 *bytes = *codes++ ^ condval[ins->condition];
1640 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1641 offset += 1;
1642 break;
1643
1644 case 0331:
1645 break;
1646
1647 case 0332:
1648 case 0333:
1649 *bytes = c - 0332 + 0xF2;
1650 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1651 offset += 1;
1652 break;
1653
1654 case 0334:
1655 if (ins->rex & REX_R) {
1656 *bytes = 0xF0;
1657 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1658 offset += 1;
1659 }
1660 ins->rex &= ~(REX_L|REX_R);
1661 break;
1662
1663 case 0335:
1664 break;
1665
1666 case 0336:
1667 case 0337:
1668 break;
1669
1670 case 0340:
1671 if (ins->oprs[0].segment != NO_SEG)
1672 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1673 else {
1674 int64_t size = ins->oprs[0].offset;
1675 if (size > 0)
1676 out(offset, segment, NULL,
1677 OUT_RESERVE, size, NO_SEG, NO_SEG);
1678 offset += size;
1679 }
1680 break;
1681
1682 case 0341:
1683 break;
1684
1685 case 0344:
1686 case 0345:
1687 bytes[0] = c & 1;
1688 switch (ins->oprs[0].basereg) {
1689 case R_CS:
1690 bytes[0] += 0x0E;
1691 break;
1692 case R_DS:
1693 bytes[0] += 0x1E;
1694 break;
1695 case R_ES:
1696 bytes[0] += 0x06;
1697 break;
1698 case R_SS:
1699 bytes[0] += 0x16;
1700 break;
1701 default:
1702 errfunc(ERR_PANIC,
1703 "bizarre 8086 segment register received");
1704 }
1705 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1706 offset++;
1707 break;
1708
1709 case 0346:
1710 case 0347:
1711 bytes[0] = c & 1;
1712 switch (ins->oprs[0].basereg) {
1713 case R_FS:
1714 bytes[0] += 0xA0;
1715 break;
1716 case R_GS:
1717 bytes[0] += 0xA8;
1718 break;
1719 default:
1720 errfunc(ERR_PANIC,
1721 "bizarre 386 segment register received");
1722 }
1723 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1724 offset++;
1725 break;
1726
1727 case 0360:
1728 break;
1729
1730 case 0361:
1731 bytes[0] = 0x66;
1732 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1733 offset += 1;
1734 break;
1735
1736 case 0362:
1737 case 0363:
1738 bytes[0] = c - 0362 + 0xf2;
1739 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1740 offset += 1;
1741 break;
1742
1743 case 0364:
1744 case 0365:
1745 break;
1746
1747 case 0366:
1748 case 0367:
1749 *bytes = c - 0366 + 0x66;
1750 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1751 offset += 1;
1752 break;
1753
1754 case 0370:
1755 case 0371:
1756 case 0372:
1757 break;
1758
1759 case 0373:
1760 *bytes = bits == 16 ? 3 : 5;
1761 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1762 offset += 1;
1763 break;
1764
1765 case 0374:
1766 eat = EA_XMMVSIB;
1767 break;
1768
1769 case 0375:
1770 eat = EA_YMMVSIB;
1771 break;
1772
1773 case4(0100):
1774 case4(0110):
1775 case4(0120):
1776 case4(0130):
1777 case4(0200):
1778 case4(0204):
1779 case4(0210):
1780 case4(0214):
1781 case4(0220):
1782 case4(0224):
1783 case4(0230):
1784 case4(0234):
1785 {
1786 ea ea_data;
1787 int rfield;
1788 opflags_t rflags;
1789 uint8_t *p;
1790 int32_t s;
1791 struct operand *opy = &ins->oprs[op2];
1792
1793 if (c <= 0177) {
1794 /* pick rfield from operand b (opx) */
1795 rflags = regflag(opx);
1796 rfield = nasm_regvals[opx->basereg];
1797 } else {
1798 /* rfield is constant */
1799 rflags = 0;
1800 rfield = c & 7;
1801 }
1802
1803 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1804 rfield, rflags) != eat)
1805 errfunc(ERR_NONFATAL, "invalid effective address");
1806
1807 p = bytes;
1808 *p++ = ea_data.modrm;
1809 if (ea_data.sib_present)
1810 *p++ = ea_data.sib;
1811
1812 s = p - bytes;
1813 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1814
1815 /*
1816 * Make sure the address gets the right offset in case
1817 * the line breaks in the .lst file (BR 1197827)
1818 */
1819 offset += s;
1820 s = 0;
1821
1822 switch (ea_data.bytes) {
1823 case 0:
1824 break;
1825 case 1:
1826 case 2:
1827 case 4:
1828 case 8:
1829 data = opy->offset;
1830 s += ea_data.bytes;
1831 if (ea_data.rip) {
1832 if (opy->segment == segment) {
1833 data -= insn_end;
1834 if (overflow_signed(data, ea_data.bytes))
1835 warn_overflow(ERR_PASS2, ea_data.bytes);
1836 out(offset, segment, &data, OUT_ADDRESS,
1837 ea_data.bytes, NO_SEG, NO_SEG);
1838 } else {
1839 /* overflow check in output/linker? */
1840 out(offset, segment, &data, OUT_REL4ADR,
1841 insn_end - offset, opy->segment, opy->wrt);
1842 }
1843 } else {
1844 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1845 signed_bits(opy->offset, ins->addr_size) !=
1846 signed_bits(opy->offset, ea_data.bytes * 8))
1847 warn_overflow(ERR_PASS2, ea_data.bytes);
1848
1849 out(offset, segment, &data, OUT_ADDRESS,
1850 ea_data.bytes, opy->segment, opy->wrt);
1851 }
1852 break;
1853 default:
1854 /* Impossible! */
1855 errfunc(ERR_PANIC,
1856 "Invalid amount of bytes (%d) for offset?!",
1857 ea_data.bytes);
1858 break;
1859 }
1860 offset += s;
1861 }
1862 break;
1863
1864 default:
1865 errfunc(ERR_PANIC, "internal instruction table corrupt"
1866 ": instruction code \\%o (0x%02X) given", c, c);
1867 break;
1868 }
1869 }
1870 }
1871
1872 static opflags_t regflag(const operand * o)
1873 {
1874 if (!is_register(o->basereg))
1875 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1876 return nasm_reg_flags[o->basereg];
1877 }
1878
1879 static int32_t regval(const operand * o)
1880 {
1881 if (!is_register(o->basereg))
1882 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1883 return nasm_regvals[o->basereg];
1884 }
1885
1886 static int op_rexflags(const operand * o, int mask)
1887 {
1888 opflags_t flags;
1889 int val;
1890
1891 if (!is_register(o->basereg))
1892 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1893
1894 flags = nasm_reg_flags[o->basereg];
1895 val = nasm_regvals[o->basereg];
1896
1897 return rexflags(val, flags, mask);
1898 }
1899
1900 static int rexflags(int val, opflags_t flags, int mask)
1901 {
1902 int rex = 0;
1903
1904 if (val >= 8)
1905 rex |= REX_B|REX_X|REX_R;
1906 if (flags & BITS64)
1907 rex |= REX_W;
1908 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1909 rex |= REX_H;
1910 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1911 rex |= REX_P;
1912
1913 return rex & mask;
1914 }
1915
1916 static enum match_result find_match(const struct itemplate **tempp,
1917 insn *instruction,
1918 int32_t segment, int64_t offset, int bits)
1919 {
1920 const struct itemplate *temp;
1921 enum match_result m, merr;
1922 opflags_t xsizeflags[MAX_OPERANDS];
1923 bool opsizemissing = false;
1924 int i;
1925
1926 for (i = 0; i < instruction->operands; i++)
1927 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1928
1929 merr = MERR_INVALOP;
1930
1931 for (temp = nasm_instructions[instruction->opcode];
1932 temp->opcode != I_none; temp++) {
1933 m = matches(temp, instruction, bits);
1934 if (m == MOK_JUMP) {
1935 if (jmp_match(segment, offset, bits, instruction, temp->code))
1936 m = MOK_GOOD;
1937 else
1938 m = MERR_INVALOP;
1939 } else if (m == MERR_OPSIZEMISSING &&
1940 (temp->flags & IF_SMASK) != IF_SX) {
1941 /*
1942 * Missing operand size and a candidate for fuzzy matching...
1943 */
1944 for (i = 0; i < temp->operands; i++) {
1945 if ((temp->opd[i] & SAME_AS) == 0)
1946 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1947 }
1948 opsizemissing = true;
1949 }
1950 if (m > merr)
1951 merr = m;
1952 if (merr == MOK_GOOD)
1953 goto done;
1954 }
1955
1956 /* No match, but see if we can get a fuzzy operand size match... */
1957 if (!opsizemissing)
1958 goto done;
1959
1960 for (i = 0; i < instruction->operands; i++) {
1961 /*
1962 * We ignore extrinsic operand sizes on registers, so we should
1963 * never try to fuzzy-match on them. This also resolves the case
1964 * when we have e.g. "xmmrm128" in two different positions.
1965 */
1966 if (is_class(REGISTER, instruction->oprs[i].type))
1967 continue;
1968
1969 /* This tests if xsizeflags[i] has more than one bit set */
1970 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1971 goto done; /* No luck */
1972
1973 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1974 }
1975
1976 /* Try matching again... */
1977 for (temp = nasm_instructions[instruction->opcode];
1978 temp->opcode != I_none; temp++) {
1979 m = matches(temp, instruction, bits);
1980 if (m == MOK_JUMP) {
1981 if (jmp_match(segment, offset, bits, instruction, temp->code))
1982 m = MOK_GOOD;
1983 else
1984 m = MERR_INVALOP;
1985 }
1986 if (m > merr)
1987 merr = m;
1988 if (merr == MOK_GOOD)
1989 goto done;
1990 }
1991
1992 done:
1993 *tempp = temp;
1994 return merr;
1995 }
1996
1997 static enum match_result matches(const struct itemplate *itemp,
1998 insn *instruction, int bits)
1999 {
2000 int i, size[MAX_OPERANDS], asize, oprs;
2001 bool opsizemissing = false;
2002
2003 /*
2004 * Check the opcode
2005 */
2006 if (itemp->opcode != instruction->opcode)
2007 return MERR_INVALOP;
2008
2009 /*
2010 * Count the operands
2011 */
2012 if (itemp->operands != instruction->operands)
2013 return MERR_INVALOP;
2014
2015 /*
2016 * Is it legal?
2017 */
2018 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2019 return MERR_INVALOP;
2020
2021 /*
2022 * Check that no spurious colons or TOs are present
2023 */
2024 for (i = 0; i < itemp->operands; i++)
2025 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2026 return MERR_INVALOP;
2027
2028 /*
2029 * Process size flags
2030 */
2031 switch (itemp->flags & IF_SMASK) {
2032 case IF_SB:
2033 asize = BITS8;
2034 break;
2035 case IF_SW:
2036 asize = BITS16;
2037 break;
2038 case IF_SD:
2039 asize = BITS32;
2040 break;
2041 case IF_SQ:
2042 asize = BITS64;
2043 break;
2044 case IF_SO:
2045 asize = BITS128;
2046 break;
2047 case IF_SY:
2048 asize = BITS256;
2049 break;
2050 case IF_SZ:
2051 switch (bits) {
2052 case 16:
2053 asize = BITS16;
2054 break;
2055 case 32:
2056 asize = BITS32;
2057 break;
2058 case 64:
2059 asize = BITS64;
2060 break;
2061 default:
2062 asize = 0;
2063 break;
2064 }
2065 break;
2066 default:
2067 asize = 0;
2068 break;
2069 }
2070
2071 if (itemp->flags & IF_ARMASK) {
2072 /* S- flags only apply to a specific operand */
2073 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2074 memset(size, 0, sizeof size);
2075 size[i] = asize;
2076 } else {
2077 /* S- flags apply to all operands */
2078 for (i = 0; i < MAX_OPERANDS; i++)
2079 size[i] = asize;
2080 }
2081
2082 /*
2083 * Check that the operand flags all match up,
2084 * it's a bit tricky so lets be verbose:
2085 *
2086 * 1) Find out the size of operand. If instruction
2087 * doesn't have one specified -- we're trying to
2088 * guess it either from template (IF_S* flag) or
2089 * from code bits.
2090 *
2091 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2092 * (ie the same operand as was specified somewhere in template, and
2093 * this referred operand index is being achieved via ~SAME_AS)
2094 * we are to be sure that both registers (in template and instruction)
2095 * do exactly match.
2096 *
2097 * 3) If template operand do not match the instruction OR
2098 * template has an operand size specified AND this size differ
2099 * from which instruction has (perhaps we got it from code bits)
2100 * we are:
2101 * a) Check that only size of instruction and operand is differ
2102 * other characteristics do match
2103 * b) Perhaps it's a register specified in instruction so
2104 * for such a case we just mark that operand as "size
2105 * missing" and this will turn on fuzzy operand size
2106 * logic facility (handled by a caller)
2107 */
2108 for (i = 0; i < itemp->operands; i++) {
2109 opflags_t type = instruction->oprs[i].type;
2110 if (!(type & SIZE_MASK))
2111 type |= size[i];
2112
2113 if (itemp->opd[i] & SAME_AS) {
2114 int j = itemp->opd[i] & ~SAME_AS;
2115 if (type != instruction->oprs[j].type ||
2116 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2117 return MERR_INVALOP;
2118 } else if (itemp->opd[i] & ~type ||
2119 ((itemp->opd[i] & SIZE_MASK) &&
2120 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2121 if ((itemp->opd[i] & ~type & ~SIZE_MASK) || (type & SIZE_MASK)) {
2122 return MERR_INVALOP;
2123 } else if (!is_class(REGISTER, type)) {
2124 /*
2125 * Note: we don't honor extrinsic operand sizes for registers,
2126 * so "missing operand size" for a register should be
2127 * considered a wildcard match rather than an error.
2128 */
2129 opsizemissing = true;
2130 }
2131 }
2132 }
2133
2134 if (opsizemissing)
2135 return MERR_OPSIZEMISSING;
2136
2137 /*
2138 * Check operand sizes
2139 */
2140 if (itemp->flags & (IF_SM | IF_SM2)) {
2141 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2142 for (i = 0; i < oprs; i++) {
2143 asize = itemp->opd[i] & SIZE_MASK;
2144 if (asize) {
2145 for (i = 0; i < oprs; i++)
2146 size[i] = asize;
2147 break;
2148 }
2149 }
2150 } else {
2151 oprs = itemp->operands;
2152 }
2153
2154 for (i = 0; i < itemp->operands; i++) {
2155 if (!(itemp->opd[i] & SIZE_MASK) &&
2156 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2157 return MERR_OPSIZEMISMATCH;
2158 }
2159
2160 /*
2161 * Check template is okay at the set cpu level
2162 */
2163 if (((itemp->flags & IF_PLEVEL) > cpu))
2164 return MERR_BADCPU;
2165
2166 /*
2167 * Verify the appropriate long mode flag.
2168 */
2169 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2170 return MERR_BADMODE;
2171
2172 /*
2173 * Check if special handling needed for Jumps
2174 */
2175 if ((itemp->code[0] & 0374) == 0370)
2176 return MOK_JUMP;
2177
2178 return MOK_GOOD;
2179 }
2180
2181 static enum ea_type process_ea(operand * input, ea * output, int bits,
2182 int addrbits, int rfield, opflags_t rflags)
2183 {
2184 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2185
2186 output->type = EA_SCALAR;
2187 output->rip = false;
2188
2189 /* REX flags for the rfield operand */
2190 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2191
2192 if (is_class(REGISTER, input->type)) { /* register direct */
2193 int i;
2194 opflags_t f;
2195
2196 if (!is_register(input->basereg))
2197 goto err;
2198 f = regflag(input);
2199 i = nasm_regvals[input->basereg];
2200
2201 if (REG_EA & ~f)
2202 goto err;
2203
2204 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2205
2206 output->sib_present = false; /* no SIB necessary */
2207 output->bytes = 0; /* no offset necessary either */
2208 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2209 } else { /* it's a memory reference */
2210 if (input->basereg == -1 &&
2211 (input->indexreg == -1 || input->scale == 0)) {
2212 /* it's a pure offset */
2213
2214 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2215 input->segment == NO_SEG) {
2216 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2217 input->type &= ~IP_REL;
2218 input->type |= MEMORY;
2219 }
2220
2221 if (input->eaflags & EAF_BYTEOFFS ||
2222 (input->eaflags & EAF_WORDOFFS &&
2223 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2224 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2225 }
2226
2227 if (bits == 64 && (~input->type & IP_REL)) {
2228 int scale, index, base;
2229 output->sib_present = true;
2230 scale = 0;
2231 index = 4;
2232 base = 5;
2233 output->sib = (scale << 6) | (index << 3) | base;
2234 output->bytes = 4;
2235 output->modrm = 4 | ((rfield & 7) << 3);
2236 output->rip = false;
2237 } else {
2238 output->sib_present = false;
2239 output->bytes = (addrbits != 16 ? 4 : 2);
2240 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2241 output->rip = bits == 64;
2242 }
2243 } else { /* it's an indirection */
2244 int i = input->indexreg, b = input->basereg, s = input->scale;
2245 int32_t seg = input->segment;
2246 int hb = input->hintbase, ht = input->hinttype;
2247 int t, it, bt; /* register numbers */
2248 opflags_t x, ix, bx; /* register flags */
2249
2250 if (s == 0)
2251 i = -1; /* make this easy, at least */
2252
2253 if (is_register(i)) {
2254 it = nasm_regvals[i];
2255 ix = nasm_reg_flags[i];
2256 } else {
2257 it = -1;
2258 ix = 0;
2259 }
2260
2261 if (is_register(b)) {
2262 bt = nasm_regvals[b];
2263 bx = nasm_reg_flags[b];
2264 } else {
2265 bt = -1;
2266 bx = 0;
2267 }
2268
2269 /* if either one are a vector register... */
2270 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2271 int32_t sok = BITS32 | BITS64;
2272 int32_t o = input->offset;
2273 int mod, scale, index, base;
2274
2275 /*
2276 * For a vector SIB, one has to be a vector and the other,
2277 * if present, a GPR. The vector must be the index operand.
2278 */
2279 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2280 if (s == 0)
2281 s = 1;
2282 else if (s != 1)
2283 goto err;
2284
2285 t = bt, bt = it, it = t;
2286 x = bx, bx = ix, ix = x;
2287 }
2288
2289 if (bt != -1) {
2290 if (REG_GPR & ~bx)
2291 goto err;
2292 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2293 sok &= bx;
2294 else
2295 goto err;
2296 }
2297
2298 /*
2299 * While we're here, ensure the user didn't specify
2300 * WORD or QWORD
2301 */
2302 if (input->disp_size == 16 || input->disp_size == 64)
2303 goto err;
2304
2305 if (addrbits == 16 ||
2306 (addrbits == 32 && !(sok & BITS32)) ||
2307 (addrbits == 64 && !(sok & BITS64)))
2308 goto err;
2309
2310 output->type = (ix & YMMREG & ~REG_EA)
2311 ? EA_YMMVSIB : EA_XMMVSIB;
2312
2313 output->rex |= rexflags(it, ix, REX_X);
2314 output->rex |= rexflags(bt, bx, REX_B);
2315
2316 index = it & 7; /* it is known to be != -1 */
2317
2318 switch (s) {
2319 case 1:
2320 scale = 0;
2321 break;
2322 case 2:
2323 scale = 1;
2324 break;
2325 case 4:
2326 scale = 2;
2327 break;
2328 case 8:
2329 scale = 3;
2330 break;
2331 default: /* then what the smeg is it? */
2332 goto err; /* panic */
2333 }
2334
2335 if (bt == -1) {
2336 base = 5;
2337 mod = 0;
2338 } else {
2339 base = (bt & 7);
2340 if (base != REG_NUM_EBP && o == 0 &&
2341 seg == NO_SEG && !forw_ref &&
2342 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2343 mod = 0;
2344 else if (input->eaflags & EAF_BYTEOFFS ||
2345 (o >= -128 && o <= 127 &&
2346 seg == NO_SEG && !forw_ref &&
2347 !(input->eaflags & EAF_WORDOFFS)))
2348 mod = 1;
2349 else
2350 mod = 2;
2351 }
2352
2353 output->sib_present = true;
2354 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2355 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2356 output->sib = (scale << 6) | (index << 3) | base;
2357 } else if ((ix|bx) & (BITS32|BITS64)) {
2358 /*
2359 * it must be a 32/64-bit memory reference. Firstly we have
2360 * to check that all registers involved are type E/Rxx.
2361 */
2362 int32_t sok = BITS32 | BITS64;
2363 int32_t o = input->offset;
2364
2365 if (it != -1) {
2366 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2367 sok &= ix;
2368 else
2369 goto err;
2370 }
2371
2372 if (bt != -1) {
2373 if (REG_GPR & ~bx)
2374 goto err; /* Invalid register */
2375 if (~sok & bx & SIZE_MASK)
2376 goto err; /* Invalid size */
2377 sok &= bx;
2378 }
2379
2380 /*
2381 * While we're here, ensure the user didn't specify
2382 * WORD or QWORD
2383 */
2384 if (input->disp_size == 16 || input->disp_size == 64)
2385 goto err;
2386
2387 if (addrbits == 16 ||
2388 (addrbits == 32 && !(sok & BITS32)) ||
2389 (addrbits == 64 && !(sok & BITS64)))
2390 goto err;
2391
2392 /* now reorganize base/index */
2393 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2394 ((hb == b && ht == EAH_NOTBASE) ||
2395 (hb == i && ht == EAH_MAKEBASE))) {
2396 /* swap if hints say so */
2397 t = bt, bt = it, it = t;
2398 x = bx, bx = ix, ix = x;
2399 }
2400 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2401 bt = -1, bx = 0, s++;
2402 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2403 /* make single reg base, unless hint */
2404 bt = it, bx = ix, it = -1, ix = 0;
2405 }
2406 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2407 s == 3 || s == 5 || s == 9) && bt == -1)
2408 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2409 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2410 (input->eaflags & EAF_TIMESTWO))
2411 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2412 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2413 if (s == 1 && it == REG_NUM_ESP) {
2414 /* swap ESP into base if scale is 1 */
2415 t = it, it = bt, bt = t;
2416 x = ix, ix = bx, bx = x;
2417 }
2418 if (it == REG_NUM_ESP ||
2419 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2420 goto err; /* wrong, for various reasons */
2421
2422 output->rex |= rexflags(it, ix, REX_X);
2423 output->rex |= rexflags(bt, bx, REX_B);
2424
2425 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2426 /* no SIB needed */
2427 int mod, rm;
2428
2429 if (bt == -1) {
2430 rm = 5;
2431 mod = 0;
2432 } else {
2433 rm = (bt & 7);
2434 if (rm != REG_NUM_EBP && o == 0 &&
2435 seg == NO_SEG && !forw_ref &&
2436 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2437 mod = 0;
2438 else if (input->eaflags & EAF_BYTEOFFS ||
2439 (o >= -128 && o <= 127 &&
2440 seg == NO_SEG && !forw_ref &&
2441 !(input->eaflags & EAF_WORDOFFS)))
2442 mod = 1;
2443 else
2444 mod = 2;
2445 }
2446
2447 output->sib_present = false;
2448 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2449 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2450 } else {
2451 /* we need a SIB */
2452 int mod, scale, index, base;
2453
2454 if (it == -1)
2455 index = 4, s = 1;
2456 else
2457 index = (it & 7);
2458
2459 switch (s) {
2460 case 1:
2461 scale = 0;
2462 break;
2463 case 2:
2464 scale = 1;
2465 break;
2466 case 4:
2467 scale = 2;
2468 break;
2469 case 8:
2470 scale = 3;
2471 break;
2472 default: /* then what the smeg is it? */
2473 goto err; /* panic */
2474 }
2475
2476 if (bt == -1) {
2477 base = 5;
2478 mod = 0;
2479 } else {
2480 base = (bt & 7);
2481 if (base != REG_NUM_EBP && o == 0 &&
2482 seg == NO_SEG && !forw_ref &&
2483 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2484 mod = 0;
2485 else if (input->eaflags & EAF_BYTEOFFS ||
2486 (o >= -128 && o <= 127 &&
2487 seg == NO_SEG && !forw_ref &&
2488 !(input->eaflags & EAF_WORDOFFS)))
2489 mod = 1;
2490 else
2491 mod = 2;
2492 }
2493
2494 output->sib_present = true;
2495 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2496 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2497 output->sib = (scale << 6) | (index << 3) | base;
2498 }
2499 } else { /* it's 16-bit */
2500 int mod, rm;
2501 int16_t o = input->offset;
2502
2503 /* check for 64-bit long mode */
2504 if (addrbits == 64)
2505 goto err;
2506
2507 /* check all registers are BX, BP, SI or DI */
2508 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2509 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2510 goto err;
2511
2512 /* ensure the user didn't specify DWORD/QWORD */
2513 if (input->disp_size == 32 || input->disp_size == 64)
2514 goto err;
2515
2516 if (s != 1 && i != -1)
2517 goto err; /* no can do, in 16-bit EA */
2518 if (b == -1 && i != -1) {
2519 int tmp = b;
2520 b = i;
2521 i = tmp;
2522 } /* swap */
2523 if ((b == R_SI || b == R_DI) && i != -1) {
2524 int tmp = b;
2525 b = i;
2526 i = tmp;
2527 }
2528 /* have BX/BP as base, SI/DI index */
2529 if (b == i)
2530 goto err; /* shouldn't ever happen, in theory */
2531 if (i != -1 && b != -1 &&
2532 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2533 goto err; /* invalid combinations */
2534 if (b == -1) /* pure offset: handled above */
2535 goto err; /* so if it gets to here, panic! */
2536
2537 rm = -1;
2538 if (i != -1)
2539 switch (i * 256 + b) {
2540 case R_SI * 256 + R_BX:
2541 rm = 0;
2542 break;
2543 case R_DI * 256 + R_BX:
2544 rm = 1;
2545 break;
2546 case R_SI * 256 + R_BP:
2547 rm = 2;
2548 break;
2549 case R_DI * 256 + R_BP:
2550 rm = 3;
2551 break;
2552 } else
2553 switch (b) {
2554 case R_SI:
2555 rm = 4;
2556 break;
2557 case R_DI:
2558 rm = 5;
2559 break;
2560 case R_BP:
2561 rm = 6;
2562 break;
2563 case R_BX:
2564 rm = 7;
2565 break;
2566 }
2567 if (rm == -1) /* can't happen, in theory */
2568 goto err; /* so panic if it does */
2569
2570 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2571 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2572 mod = 0;
2573 else if (input->eaflags & EAF_BYTEOFFS ||
2574 (o >= -128 && o <= 127 && seg == NO_SEG &&
2575 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2576 mod = 1;
2577 else
2578 mod = 2;
2579
2580 output->sib_present = false; /* no SIB - it's 16-bit */
2581 output->bytes = mod; /* bytes of offset needed */
2582 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2583 }
2584 }
2585 }
2586
2587 output->size = 1 + output->sib_present + output->bytes;
2588 return output->type;
2589
2590 err:
2591 return output->type = EA_INVALID;
2592 }
2593
2594 static void add_asp(insn *ins, int addrbits)
2595 {
2596 int j, valid;
2597 int defdisp;
2598
2599 valid = (addrbits == 64) ? 64|32 : 32|16;
2600
2601 switch (ins->prefixes[PPS_ASIZE]) {
2602 case P_A16:
2603 valid &= 16;
2604 break;
2605 case P_A32:
2606 valid &= 32;
2607 break;
2608 case P_A64:
2609 valid &= 64;
2610 break;
2611 case P_ASP:
2612 valid &= (addrbits == 32) ? 16 : 32;
2613 break;
2614 default:
2615 break;
2616 }
2617
2618 for (j = 0; j < ins->operands; j++) {
2619 if (is_class(MEMORY, ins->oprs[j].type)) {
2620 opflags_t i, b;
2621
2622 /* Verify as Register */
2623 if (!is_register(ins->oprs[j].indexreg))
2624 i = 0;
2625 else
2626 i = nasm_reg_flags[ins->oprs[j].indexreg];
2627
2628 /* Verify as Register */
2629 if (!is_register(ins->oprs[j].basereg))
2630 b = 0;
2631 else
2632 b = nasm_reg_flags[ins->oprs[j].basereg];
2633
2634 if (ins->oprs[j].scale == 0)
2635 i = 0;
2636
2637 if (!i && !b) {
2638 int ds = ins->oprs[j].disp_size;
2639 if ((addrbits != 64 && ds > 8) ||
2640 (addrbits == 64 && ds == 16))
2641 valid &= ds;
2642 } else {
2643 if (!(REG16 & ~b))
2644 valid &= 16;
2645 if (!(REG32 & ~b))
2646 valid &= 32;
2647 if (!(REG64 & ~b))
2648 valid &= 64;
2649
2650 if (!(REG16 & ~i))
2651 valid &= 16;
2652 if (!(REG32 & ~i))
2653 valid &= 32;
2654 if (!(REG64 & ~i))
2655 valid &= 64;
2656 }
2657 }
2658 }
2659
2660 if (valid & addrbits) {
2661 ins->addr_size = addrbits;
2662 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2663 /* Add an address size prefix */
2664 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2665 ins->prefixes[PPS_ASIZE] = pref;
2666 ins->addr_size = (addrbits == 32) ? 16 : 32;
2667 } else {
2668 /* Impossible... */
2669 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2670 ins->addr_size = addrbits; /* Error recovery */
2671 }
2672
2673 defdisp = ins->addr_size == 16 ? 16 : 32;
2674
2675 for (j = 0; j < ins->operands; j++) {
2676 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2677 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2678 /*
2679 * mem_offs sizes must match the address size; if not,
2680 * strip the MEM_OFFS bit and match only EA instructions
2681 */
2682 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2683 }
2684 }
2685 }
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