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64-bit addressing and prefix handling changes
[nasm.git] / assemble.c
blob83a9a8a0c05d41edb60c6015c0b1441720bc96e8
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into next opcode byte if operand 0..3
37 * is a signed byte rather than a word.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into next opcode byte if operand 0..3
40 * is a signed byte rather than a dword.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \170 - encodes the literal byte 0. (Some compilers don't take
48 * kindly to a zero byte in the _middle_ of a compile time
49 * string constant, so I had to put this hack in.)
50 * \171 - placement of DREX suffix in the absence of an EA
51 * \2ab - a ModRM, calculated on EA in operand a, with the spare
52 * field equal to digit b.
53 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
54 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
55 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
56 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
57 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
58 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
59 * \322 - indicates that this instruction is only valid when the
60 * operand size is the default (instruction to disassembler,
61 * generates no code in the assembler)
62 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
63 * \324 - indicates 64-bit operand size requiring REX prefix.
64 * \330 - a literal byte follows in the code stream, to be added
65 * to the condition code value of the instruction.
66 * \331 - instruction not valid with REP prefix. Hint for
67 * disassembler only; for SSE instructions.
68 * \332 - REP prefix (0xF2 byte) used as opcode extension.
69 * \333 - REP prefix (0xF3 byte) used as opcode extension.
70 * \334 - LOCK prefix used instead of REX.R
71 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
72 * \340 - reserve <operand 0> bytes of uninitialized storage.
73 * Operand 0 had better be a segmentless constant.
74 * \364 - operand-size prefix (0x66) not permitted
75 * \365 - address-size prefix (0x67) not permitted
76 * \366 - operand-size prefix (0x66) used as opcode extension
77 * \367 - address-size prefix (0x67) used as opcode extension
78 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
79 * 370 is used for Jcc, 371 is used for JMP.
80 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
81 * used for conditional jump over longer jump
82 */
83
84 #include "compiler.h"
85
86 #include <stdio.h>
87 #include <string.h>
88 #include <inttypes.h>
89
90 #include "nasm.h"
91 #include "nasmlib.h"
92 #include "assemble.h"
93 #include "insns.h"
94 #include "preproc.h"
95 #include "regflags.c"
96 #include "regvals.c"
97
98 typedef struct {
99 int sib_present; /* is a SIB byte necessary? */
100 int bytes; /* # of bytes of offset needed */
101 int size; /* lazy - this is sib+bytes+1 */
102 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
103 } ea;
104
105 static uint32_t cpu; /* cpu level received from nasm.c */
106 static efunc errfunc;
107 static struct ofmt *outfmt;
108 static ListGen *list;
109
110 static int32_t calcsize(int32_t, int32_t, int, insn *, const char *);
111 static void gencode(int32_t, int32_t, int, insn *, const char *, int32_t);
112 static int matches(const struct itemplate *, insn *, int bits);
113 static int32_t regflag(const operand *);
114 static int32_t regval(const operand *);
115 static int rexflags(int, int32_t, int);
116 static int op_rexflags(const operand *, int);
117 static ea *process_ea(operand *, ea *, int, int, int, int32_t, int);
118 static void add_asp(insn *, int);
119
120 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
121 {
122 return ins->prefixes[pos] == prefix;
123 }
124
125 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
126 {
127 if (ins->prefixes[pos])
128 errfunc(ERR_NONFATAL, "invalid %s prefix",
129 prefix_name(ins->prefixes[pos]));
130 }
131
132 static const char *size_name(int size)
133 {
134 switch (size) {
135 case 1:
136 return "byte";
137 case 2:
138 return "word";
139 case 4:
140 return "dword";
141 case 8:
142 return "qword";
143 case 10:
144 return "tword";
145 case 16:
146 return "oword";
147 default:
148 return "???";
149 }
150 }
151
152 static void warn_overflow(int size, int64_t data)
153 {
154 if (size < 8) {
155 int64_t lim = (1 << (size*8))-1;
156
157 if (data < ~lim || data > lim)
158 errfunc(ERR_WARNING, "%s data exceeds bounds", size_name(size));
159 }
160 }
161 /*
162 * This routine wrappers the real output format's output routine,
163 * in order to pass a copy of the data off to the listing file
164 * generator at the same time.
165 */
166 static void out(int32_t offset, int32_t segto, const void *data,
167 uint32_t type, int32_t segment, int32_t wrt)
168 {
169 static int32_t lineno = 0; /* static!!! */
170 static char *lnfname = NULL;
171
172 if ((type & OUT_TYPMASK) == OUT_ADDRESS) {
173 if (segment != NO_SEG || wrt != NO_SEG) {
174 /*
175 * This address is relocated. We must write it as
176 * OUT_ADDRESS, so there's no work to be done here.
177 */
178 list->output(offset, data, type);
179 } else {
180 uint8_t p[8], *q = p;
181 /*
182 * This is a non-relocated address, and we're going to
183 * convert it into RAWDATA format.
184 */
185 if ((type & OUT_SIZMASK) == 4) {
186 WRITELONG(q, *(int32_t *)data);
187 list->output(offset, p, OUT_RAWDATA + 4);
188 } else if ((type & OUT_SIZMASK) == 8) {
189 WRITEDLONG(q, *(int64_t *)data);
190 list->output(offset, p, OUT_RAWDATA + 8);
191 } else {
192 WRITESHORT(q, *(int32_t *)data);
193 list->output(offset, p, OUT_RAWDATA + 2);
194 }
195 }
196 } else if ((type & OUT_TYPMASK) == OUT_RAWDATA) {
197 list->output(offset, data, type);
198 } else if ((type & OUT_TYPMASK) == OUT_RESERVE) {
199 list->output(offset, NULL, type);
200 } else if ((type & OUT_TYPMASK) == OUT_REL2ADR ||
201 (type & OUT_TYPMASK) == OUT_REL4ADR) {
202 list->output(offset, data, type);
203 }
204
205 /*
206 * this call to src_get determines when we call the
207 * debug-format-specific "linenum" function
208 * it updates lineno and lnfname to the current values
209 * returning 0 if "same as last time", -2 if lnfname
210 * changed, and the amount by which lineno changed,
211 * if it did. thus, these variables must be static
212 */
213
214 if (src_get(&lineno, &lnfname)) {
215 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
216 }
217
218 outfmt->output(segto, data, type, segment, wrt);
219 }
220
221 static int jmp_match(int32_t segment, int32_t offset, int bits,
222 insn * ins, const char *code)
223 {
224 int32_t isize;
225 uint8_t c = code[0];
226
227 if (c != 0370 && c != 0371)
228 return 0;
229 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
230 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
231 && c == 0370)
232 return 1;
233 else
234 return (pass0 == 0); /* match a forward reference */
235 }
236 isize = calcsize(segment, offset, bits, ins, code);
237 if (ins->oprs[0].segment != segment)
238 return 0;
239 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
240 if (isize >= -128L && isize <= 127L)
241 return 1; /* it is byte size */
242
243 return 0;
244 }
245
246 int32_t assemble(int32_t segment, int32_t offset, int bits, uint32_t cp,
247 insn * instruction, struct ofmt *output, efunc error,
248 ListGen * listgen)
249 {
250 const struct itemplate *temp;
251 int j;
252 int size_prob;
253 int32_t insn_end;
254 int32_t itimes;
255 int32_t start = offset;
256 int32_t wsize = 0; /* size for DB etc. */
257
258 errfunc = error; /* to pass to other functions */
259 cpu = cp;
260 outfmt = output; /* likewise */
261 list = listgen; /* and again */
262
263 switch (instruction->opcode) {
264 case -1:
265 return 0;
266 case I_DB:
267 wsize = 1;
268 break;
269 case I_DW:
270 wsize = 2;
271 break;
272 case I_DD:
273 wsize = 4;
274 break;
275 case I_DQ:
276 wsize = 8;
277 break;
278 case I_DT:
279 wsize = 10;
280 break;
281 case I_DO:
282 wsize = 16;
283 break;
284 default:
285 break;
286 }
287
288 if (wsize) {
289 extop *e;
290 int32_t t = instruction->times;
291 if (t < 0)
292 errfunc(ERR_PANIC,
293 "instruction->times < 0 (%ld) in assemble()", t);
294
295 while (t--) { /* repeat TIMES times */
296 for (e = instruction->eops; e; e = e->next) {
297 if (e->type == EOT_DB_NUMBER) {
298 if (wsize == 1) {
299 if (e->segment != NO_SEG)
300 errfunc(ERR_NONFATAL,
301 "one-byte relocation attempted");
302 else {
303 uint8_t out_byte = e->offset;
304 out(offset, segment, &out_byte,
305 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
306 }
307 } else if (wsize > 8) {
308 errfunc(ERR_NONFATAL, "integer supplied to a DT or DO"
309 " instruction");
310 } else
311 out(offset, segment, &e->offset,
312 OUT_ADDRESS + wsize, e->segment, e->wrt);
313 offset += wsize;
314 } else if (e->type == EOT_DB_STRING) {
315 int align;
316
317 out(offset, segment, e->stringval,
318 OUT_RAWDATA + e->stringlen, NO_SEG, NO_SEG);
319 align = e->stringlen % wsize;
320
321 if (align) {
322 align = wsize - align;
323 out(offset, segment, "\0\0\0\0\0\0\0\0",
324 OUT_RAWDATA + align, NO_SEG, NO_SEG);
325 }
326 offset += e->stringlen + align;
327 }
328 }
329 if (t > 0 && t == instruction->times - 1) {
330 /*
331 * Dummy call to list->output to give the offset to the
332 * listing module.
333 */
334 list->output(offset, NULL, OUT_RAWDATA);
335 list->uplevel(LIST_TIMES);
336 }
337 }
338 if (instruction->times > 1)
339 list->downlevel(LIST_TIMES);
340 return offset - start;
341 }
342
343 if (instruction->opcode == I_INCBIN) {
344 static char fname[FILENAME_MAX];
345 FILE *fp;
346 int32_t len;
347 char *prefix = "", *combine;
348 char **pPrevPath = NULL;
349
350 len = FILENAME_MAX - 1;
351 if (len > instruction->eops->stringlen)
352 len = instruction->eops->stringlen;
353 strncpy(fname, instruction->eops->stringval, len);
354 fname[len] = '\0';
355
356 while (1) { /* added by alexfru: 'incbin' uses include paths */
357 combine = nasm_malloc(strlen(prefix) + len + 1);
358 strcpy(combine, prefix);
359 strcat(combine, fname);
360
361 if ((fp = fopen(combine, "rb")) != NULL) {
362 nasm_free(combine);
363 break;
364 }
365
366 nasm_free(combine);
367 pPrevPath = pp_get_include_path_ptr(pPrevPath);
368 if (pPrevPath == NULL)
369 break;
370 prefix = *pPrevPath;
371 }
372
373 if (fp == NULL)
374 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
375 fname);
376 else if (fseek(fp, 0L, SEEK_END) < 0)
377 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
378 fname);
379 else {
380 static char buf[2048];
381 int32_t t = instruction->times;
382 int32_t base = 0;
383
384 len = ftell(fp);
385 if (instruction->eops->next) {
386 base = instruction->eops->next->offset;
387 len -= base;
388 if (instruction->eops->next->next &&
389 len > instruction->eops->next->next->offset)
390 len = instruction->eops->next->next->offset;
391 }
392 /*
393 * Dummy call to list->output to give the offset to the
394 * listing module.
395 */
396 list->output(offset, NULL, OUT_RAWDATA);
397 list->uplevel(LIST_INCBIN);
398 while (t--) {
399 int32_t l;
400
401 fseek(fp, base, SEEK_SET);
402 l = len;
403 while (l > 0) {
404 int32_t m =
405 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
406 fp);
407 if (!m) {
408 /*
409 * This shouldn't happen unless the file
410 * actually changes while we are reading
411 * it.
412 */
413 error(ERR_NONFATAL,
414 "`incbin': unexpected EOF while"
415 " reading file `%s'", fname);
416 t = 0; /* Try to exit cleanly */
417 break;
418 }
419 out(offset, segment, buf, OUT_RAWDATA + m,
420 NO_SEG, NO_SEG);
421 l -= m;
422 }
423 }
424 list->downlevel(LIST_INCBIN);
425 if (instruction->times > 1) {
426 /*
427 * Dummy call to list->output to give the offset to the
428 * listing module.
429 */
430 list->output(offset, NULL, OUT_RAWDATA);
431 list->uplevel(LIST_TIMES);
432 list->downlevel(LIST_TIMES);
433 }
434 fclose(fp);
435 return instruction->times * len;
436 }
437 return 0; /* if we're here, there's an error */
438 }
439
440 /* Check to see if we need an address-size prefix */
441 add_asp(instruction, bits);
442
443 size_prob = false;
444
445 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
446 int m = matches(temp, instruction, bits);
447
448 if (m == 99)
449 m += jmp_match(segment, offset, bits, instruction, temp->code);
450
451 if (m == 100) { /* matches! */
452 const char *codes = temp->code;
453 int32_t insn_size = calcsize(segment, offset, bits,
454 instruction, codes);
455 itimes = instruction->times;
456 if (insn_size < 0) /* shouldn't be, on pass two */
457 error(ERR_PANIC, "errors made it through from pass one");
458 else
459 while (itimes--) {
460 for (j = 0; j < MAXPREFIX; j++) {
461 uint8_t c = 0;
462 switch (instruction->prefixes[j]) {
463 case P_LOCK:
464 c = 0xF0;
465 break;
466 case P_REPNE:
467 case P_REPNZ:
468 c = 0xF2;
469 break;
470 case P_REPE:
471 case P_REPZ:
472 case P_REP:
473 c = 0xF3;
474 break;
475 case R_CS:
476 if (bits == 64) {
477 error(ERR_WARNING,
478 "cs segment base ignored in 64-bit mode");
479 }
480 c = 0x2E;
481 break;
482 case R_DS:
483 if (bits == 64) {
484 error(ERR_WARNING,
485 "ds segment base ignored in 64-bit mode");
486 }
487 c = 0x3E;
488 break;
489 case R_ES:
490 if (bits == 64) {
491 error(ERR_WARNING,
492 "es segment base ignored in 64-bit mode");
493 }
494 c = 0x26;
495 break;
496 case R_FS:
497 c = 0x64;
498 break;
499 case R_GS:
500 c = 0x65;
501 break;
502 case R_SS:
503 if (bits == 64) {
504 error(ERR_WARNING,
505 "ss segment base ignored in 64-bit mode");
506 }
507 c = 0x36;
508 break;
509 case R_SEGR6:
510 case R_SEGR7:
511 error(ERR_NONFATAL,
512 "segr6 and segr7 cannot be used as prefixes");
513 break;
514 case P_A16:
515 if (bits == 64) {
516 error(ERR_NONFATAL,
517 "16-bit addressing is not supported "
518 "in 64-bit mode");
519 } else if (bits != 16)
520 c = 0x67;
521 break;
522 case P_A32:
523 if (bits != 32)
524 c = 0x67;
525 break;
526 case P_A64:
527 if (bits != 64) {
528 error(ERR_NONFATAL,
529 "64-bit addressing is only supported "
530 "in 64-bit mode");
531 }
532 break;
533 case P_ASP:
534 c = 0x67;
535 break;
536 case P_O16:
537 if (bits != 16)
538 c = 0x66;
539 break;
540 case P_O32:
541 if (bits == 16)
542 c = 0x66;
543 break;
544 case P_O64:
545 /* REX.W */
546 break;
547 case P_OSP:
548 c = 0x66;
549 break;
550 case P_none:
551 break;
552 default:
553 error(ERR_PANIC, "invalid instruction prefix");
554 }
555 if (c != 0) {
556 out(offset, segment, &c, OUT_RAWDATA + 1,
557 NO_SEG, NO_SEG);
558 offset++;
559 }
560 }
561 insn_end = offset + insn_size;
562 gencode(segment, offset, bits, instruction, codes,
563 insn_end);
564 offset += insn_size;
565 if (itimes > 0 && itimes == instruction->times - 1) {
566 /*
567 * Dummy call to list->output to give the offset to the
568 * listing module.
569 */
570 list->output(offset, NULL, OUT_RAWDATA);
571 list->uplevel(LIST_TIMES);
572 }
573 }
574 if (instruction->times > 1)
575 list->downlevel(LIST_TIMES);
576 return offset - start;
577 } else if (m > 0 && m > size_prob) {
578 size_prob = m;
579 }
580 // temp++;
581 }
582
583 if (temp->opcode == -1) { /* didn't match any instruction */
584 switch (size_prob) {
585 case 1:
586 error(ERR_NONFATAL, "operation size not specified");
587 break;
588 case 2:
589 error(ERR_NONFATAL, "mismatch in operand sizes");
590 break;
591 case 3:
592 error(ERR_NONFATAL, "no instruction for this cpu level");
593 break;
594 case 4:
595 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
596 break;
597 default:
598 error(ERR_NONFATAL,
599 "invalid combination of opcode and operands");
600 break;
601 }
602 }
603 return 0;
604 }
605
606 int32_t insn_size(int32_t segment, int32_t offset, int bits, uint32_t cp,
607 insn * instruction, efunc error)
608 {
609 const struct itemplate *temp;
610
611 errfunc = error; /* to pass to other functions */
612 cpu = cp;
613
614 if (instruction->opcode == -1)
615 return 0;
616
617 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
618 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
619 instruction->opcode == I_DT || instruction->opcode == I_DO) {
620 extop *e;
621 int32_t isize, osize, wsize = 0; /* placate gcc */
622
623 isize = 0;
624 switch (instruction->opcode) {
625 case I_DB:
626 wsize = 1;
627 break;
628 case I_DW:
629 wsize = 2;
630 break;
631 case I_DD:
632 wsize = 4;
633 break;
634 case I_DQ:
635 wsize = 8;
636 break;
637 case I_DT:
638 wsize = 10;
639 break;
640 case I_DO:
641 wsize = 16;
642 break;
643 default:
644 break;
645 }
646
647 for (e = instruction->eops; e; e = e->next) {
648 int32_t align;
649
650 osize = 0;
651 if (e->type == EOT_DB_NUMBER)
652 osize = 1;
653 else if (e->type == EOT_DB_STRING)
654 osize = e->stringlen;
655
656 align = (-osize) % wsize;
657 if (align < 0)
658 align += wsize;
659 isize += osize + align;
660 }
661 return isize * instruction->times;
662 }
663
664 if (instruction->opcode == I_INCBIN) {
665 char fname[FILENAME_MAX];
666 FILE *fp;
667 int32_t len;
668 char *prefix = "", *combine;
669 char **pPrevPath = NULL;
670
671 len = FILENAME_MAX - 1;
672 if (len > instruction->eops->stringlen)
673 len = instruction->eops->stringlen;
674 strncpy(fname, instruction->eops->stringval, len);
675 fname[len] = '\0';
676
677 /* added by alexfru: 'incbin' uses include paths */
678 while (1) {
679 combine = nasm_malloc(strlen(prefix) + len + 1);
680 strcpy(combine, prefix);
681 strcat(combine, fname);
682
683 if ((fp = fopen(combine, "rb")) != NULL) {
684 nasm_free(combine);
685 break;
686 }
687
688 nasm_free(combine);
689 pPrevPath = pp_get_include_path_ptr(pPrevPath);
690 if (pPrevPath == NULL)
691 break;
692 prefix = *pPrevPath;
693 }
694
695 if (fp == NULL)
696 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
697 fname);
698 else if (fseek(fp, 0L, SEEK_END) < 0)
699 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
700 fname);
701 else {
702 len = ftell(fp);
703 fclose(fp);
704 if (instruction->eops->next) {
705 len -= instruction->eops->next->offset;
706 if (instruction->eops->next->next &&
707 len > instruction->eops->next->next->offset) {
708 len = instruction->eops->next->next->offset;
709 }
710 }
711 return instruction->times * len;
712 }
713 return 0; /* if we're here, there's an error */
714 }
715
716 /* Check to see if we need an address-size prefix */
717 add_asp(instruction, bits);
718
719 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
720 int m = matches(temp, instruction, bits);
721 if (m == 99)
722 m += jmp_match(segment, offset, bits, instruction, temp->code);
723
724 if (m == 100) {
725 /* we've matched an instruction. */
726 int32_t isize;
727 const char *codes = temp->code;
728 int j;
729
730 isize = calcsize(segment, offset, bits, instruction, codes);
731 if (isize < 0)
732 return -1;
733 for (j = 0; j < MAXPREFIX; j++) {
734 switch (instruction->prefixes[j]) {
735 case P_A16:
736 if (bits != 16)
737 isize++;
738 break;
739 case P_A32:
740 if (bits != 32)
741 isize++;
742 break;
743 case P_O16:
744 if (bits != 16)
745 isize++;
746 break;
747 case P_O32:
748 if (bits == 16)
749 isize++;
750 break;
751 case P_A64:
752 case P_O64:
753 case P_none:
754 break;
755 default:
756 isize++;
757 break;
758 }
759 }
760 return isize * instruction->times;
761 }
762 }
763 return -1; /* didn't match any instruction */
764 }
765
766 /* check that opn[op] is a signed byte of size 16 or 32,
767 and return the signed value*/
768 static int is_sbyte(insn * ins, int op, int size)
769 {
770 int32_t v;
771 int ret;
772
773 ret = !(ins->forw_ref && ins->oprs[op].opflags) && /* dead in the water on forward reference or External */
774 optimizing >= 0 &&
775 !(ins->oprs[op].type & STRICT) &&
776 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
777
778 v = ins->oprs[op].offset;
779 if (size == 16)
780 v = (int16_t)v; /* sign extend if 16 bits */
781
782 return ret && v >= -128L && v <= 127L;
783 }
784
785 static int32_t calcsize(int32_t segment, int32_t offset, int bits,
786 insn * ins, const char *codes)
787 {
788 int32_t length = 0;
789 uint8_t c;
790 int rex_mask = ~0;
791 ins->rex = 0; /* Ensure REX is reset */
792
793 if (ins->prefixes[PPS_OSIZE] == P_O64)
794 ins->rex |= REX_W;
795
796 (void)segment; /* Don't warn that this parameter is unused */
797 (void)offset; /* Don't warn that this parameter is unused */
798
799 while (*codes)
800 switch (c = *codes++) {
801 case 01:
802 case 02:
803 case 03:
804 codes += c, length += c;
805 break;
806 case 04:
807 case 05:
808 case 06:
809 case 07:
810 length++;
811 break;
812 case 010:
813 case 011:
814 case 012:
815 case 013:
816 ins->rex |=
817 op_rexflags(&ins->oprs[c - 010], REX_B|REX_H|REX_P|REX_W);
818 codes++, length++;
819 break;
820 case 014:
821 case 015:
822 case 016:
823 case 017:
824 length++;
825 break;
826 case 020:
827 case 021:
828 case 022:
829 case 023:
830 length++;
831 break;
832 case 024:
833 case 025:
834 case 026:
835 case 027:
836 length++;
837 break;
838 case 030:
839 case 031:
840 case 032:
841 case 033:
842 length += 2;
843 break;
844 case 034:
845 case 035:
846 case 036:
847 case 037:
848 if (ins->oprs[c - 034].type & (BITS16 | BITS32 | BITS64))
849 length += (ins->oprs[c - 034].type & BITS16) ? 2 : 4;
850 else
851 length += (bits == 16) ? 2 : 4;
852 break;
853 case 040:
854 case 041:
855 case 042:
856 case 043:
857 length += 4;
858 break;
859 case 044:
860 case 045:
861 case 046:
862 case 047:
863 length += ins->addr_size >> 3;
864 break;
865 case 050:
866 case 051:
867 case 052:
868 case 053:
869 length++;
870 break;
871 case 054:
872 case 055:
873 case 056:
874 case 057:
875 length += 8; /* MOV reg64/imm */
876 break;
877 case 060:
878 case 061:
879 case 062:
880 case 063:
881 length += 2;
882 break;
883 case 064:
884 case 065:
885 case 066:
886 case 067:
887 if (ins->oprs[c - 064].type & (BITS16 | BITS32 | BITS64))
888 length += (ins->oprs[c - 064].type & BITS16) ? 2 : 4;
889 else
890 length += (bits == 16) ? 2 : 4;
891 break;
892 case 070:
893 case 071:
894 case 072:
895 case 073:
896 length += 4;
897 break;
898 case 074:
899 case 075:
900 case 076:
901 case 077:
902 length += 2;
903 break;
904 case 0140:
905 case 0141:
906 case 0142:
907 case 0143:
908 length += is_sbyte(ins, c - 0140, 16) ? 1 : 2;
909 break;
910 case 0144:
911 case 0145:
912 case 0146:
913 case 0147:
914 codes += 2;
915 length++;
916 break;
917 case 0150:
918 case 0151:
919 case 0152:
920 case 0153:
921 length += is_sbyte(ins, c - 0150, 32) ? 1 : 4;
922 break;
923 case 0154:
924 case 0155:
925 case 0156:
926 case 0157:
927 codes += 2;
928 length++;
929 break;
930 case 0160:
931 case 0161:
932 case 0162:
933 case 0163:
934 length++;
935 ins->rex |= REX_D;
936 ins->drexdst = regval(&ins->oprs[c & 3]);
937 break;
938 case 0164:
939 case 0165:
940 case 0166:
941 case 0167:
942 length++;
943 ins->rex |= REX_D|REX_OC;
944 ins->drexdst = regval(&ins->oprs[c & 3]);
945 break;
946 case 0170:
947 length++;
948 break;
949 case 0171:
950 break;
951 case 0300:
952 case 0301:
953 case 0302:
954 case 0303:
955 break;
956 case 0310:
957 if (bits == 64)
958 return -1;
959 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
960 break;
961 case 0311:
962 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
963 break;
964 case 0312:
965 break;
966 case 0313:
967 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
968 has_prefix(ins, PPS_ASIZE, P_A32))
969 return -1;
970 break;
971 case 0320:
972 length += (bits != 16);
973 break;
974 case 0321:
975 length += (bits == 16);
976 break;
977 case 0322:
978 break;
979 case 0323:
980 rex_mask &= ~REX_W;
981 break;
982 case 0324:
983 ins->rex |= REX_W;
984 break;
985 case 0330:
986 codes++, length++;
987 break;
988 case 0331:
989 break;
990 case 0332:
991 case 0333:
992 length++;
993 break;
994 case 0334:
995 ins->rex |= REX_L;
996 break;
997 case 0335:
998 break;
999 case 0340:
1000 case 0341:
1001 case 0342:
1002 if (ins->oprs[0].segment != NO_SEG)
1003 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1004 " quantity of BSS space");
1005 else
1006 length += ins->oprs[0].offset << (c - 0340);
1007 break;
1008 case 0364:
1009 case 0365:
1010 break;
1011 case 0366:
1012 case 0367:
1013 length++;
1014 break;
1015 case 0370:
1016 case 0371:
1017 case 0372:
1018 break;
1019 case 0373:
1020 length++;
1021 break;
1022 default: /* can't do it by 'case' statements */
1023 if (c >= 0100 && c <= 0277) { /* it's an EA */
1024 ea ea_data;
1025 int rfield;
1026 int32_t rflags;
1027 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1028
1029 if (c <= 0177) {
1030 /* pick rfield from operand b */
1031 rflags = regflag(&ins->oprs[c & 7]);
1032 rfield = regvals[ins->oprs[c & 7].basereg];
1033 } else {
1034 rflags = 0;
1035 rfield = c & 7;
1036 }
1037
1038 if (!process_ea
1039 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1040 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1041 errfunc(ERR_NONFATAL, "invalid effective address");
1042 return -1;
1043 } else {
1044 ins->rex |= ea_data.rex;
1045 length += ea_data.size;
1046 }
1047 } else
1048 errfunc(ERR_PANIC, "internal instruction table corrupt"
1049 ": instruction code 0x%02X given", c);
1050 }
1051
1052 ins->rex &= rex_mask;
1053
1054 if (ins->rex & REX_D) {
1055 if (ins->rex & REX_H) {
1056 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1057 return -1;
1058 }
1059 if (bits != 64 && ((ins->rex & (REX_W|REX_X|REX_B)) ||
1060 ins->drexdst > 7)) {
1061 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1062 return -1;
1063 }
1064 length++;
1065 } else if (ins->rex & REX_REAL) {
1066 if (ins->rex & REX_H) {
1067 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1068 return -1;
1069 } else if (bits == 64) {
1070 length++;
1071 } else if ((ins->rex & REX_L) &&
1072 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1073 cpu >= IF_X86_64) {
1074 /* LOCK-as-REX.R */
1075 assert_no_prefix(ins, PPS_LREP);
1076 length++;
1077 } else {
1078 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1079 return -1;
1080 }
1081 }
1082
1083 return length;
1084 }
1085
1086 #define EMIT_REX() \
1087 if (!(ins->rex & REX_D) && (ins->rex & REX_REAL) && (bits == 64)) { \
1088 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1089 out(offset, segment, &ins->rex, OUT_RAWDATA+1, NO_SEG, NO_SEG); \
1090 ins->rex = 0; \
1091 offset += 1; \
1092 }
1093
1094 static void gencode(int32_t segment, int32_t offset, int bits,
1095 insn * ins, const char *codes, int32_t insn_end)
1096 {
1097 static char condval[] = { /* conditional opcodes */
1098 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1099 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1100 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1101 };
1102 uint8_t c;
1103 uint8_t bytes[4];
1104 int32_t size;
1105 int64_t data;
1106
1107 while (*codes)
1108 switch (c = *codes++) {
1109 case 01:
1110 case 02:
1111 case 03:
1112 EMIT_REX();
1113 out(offset, segment, codes, OUT_RAWDATA + c, NO_SEG, NO_SEG);
1114 codes += c;
1115 offset += c;
1116 break;
1117
1118 case 04:
1119 case 06:
1120 switch (ins->oprs[0].basereg) {
1121 case R_CS:
1122 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1123 break;
1124 case R_DS:
1125 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1126 break;
1127 case R_ES:
1128 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1129 break;
1130 case R_SS:
1131 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1132 break;
1133 default:
1134 errfunc(ERR_PANIC,
1135 "bizarre 8086 segment register received");
1136 }
1137 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1138 offset++;
1139 break;
1140
1141 case 05:
1142 case 07:
1143 switch (ins->oprs[0].basereg) {
1144 case R_FS:
1145 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1146 break;
1147 case R_GS:
1148 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1149 break;
1150 default:
1151 errfunc(ERR_PANIC,
1152 "bizarre 386 segment register received");
1153 }
1154 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1155 offset++;
1156 break;
1157
1158 case 010:
1159 case 011:
1160 case 012:
1161 case 013:
1162 EMIT_REX();
1163 bytes[0] = *codes++ + ((regval(&ins->oprs[c - 010])) & 7);
1164 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1165 offset += 1;
1166 break;
1167
1168 case 014:
1169 case 015:
1170 case 016:
1171 case 017:
1172 if (ins->oprs[c - 014].offset < -128
1173 || ins->oprs[c - 014].offset > 127) {
1174 errfunc(ERR_WARNING, "signed byte value exceeds bounds");
1175 }
1176
1177 if (ins->oprs[c - 014].segment != NO_SEG) {
1178 data = ins->oprs[c - 014].offset;
1179 out(offset, segment, &data, OUT_ADDRESS + 1,
1180 ins->oprs[c - 014].segment, ins->oprs[c - 014].wrt);
1181 } else {
1182 bytes[0] = ins->oprs[c - 014].offset;
1183 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1184 NO_SEG);
1185 }
1186 offset += 1;
1187 break;
1188
1189 case 020:
1190 case 021:
1191 case 022:
1192 case 023:
1193 if (ins->oprs[c - 020].offset < -256
1194 || ins->oprs[c - 020].offset > 255) {
1195 errfunc(ERR_WARNING, "byte value exceeds bounds");
1196 }
1197 if (ins->oprs[c - 020].segment != NO_SEG) {
1198 data = ins->oprs[c - 020].offset;
1199 out(offset, segment, &data, OUT_ADDRESS + 1,
1200 ins->oprs[c - 020].segment, ins->oprs[c - 020].wrt);
1201 } else {
1202 bytes[0] = ins->oprs[c - 020].offset;
1203 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1204 NO_SEG);
1205 }
1206 offset += 1;
1207 break;
1208
1209 case 024:
1210 case 025:
1211 case 026:
1212 case 027:
1213 if (ins->oprs[c - 024].offset < 0
1214 || ins->oprs[c - 024].offset > 255)
1215 errfunc(ERR_WARNING, "unsigned byte value exceeds bounds");
1216 if (ins->oprs[c - 024].segment != NO_SEG) {
1217 data = ins->oprs[c - 024].offset;
1218 out(offset, segment, &data, OUT_ADDRESS + 1,
1219 ins->oprs[c - 024].segment, ins->oprs[c - 024].wrt);
1220 } else {
1221 bytes[0] = ins->oprs[c - 024].offset;
1222 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1223 NO_SEG);
1224 }
1225 offset += 1;
1226 break;
1227
1228 case 030:
1229 case 031:
1230 case 032:
1231 case 033:
1232 data = ins->oprs[c - 030].offset;
1233 if (ins->oprs[c - 030].segment == NO_SEG &&
1234 ins->oprs[c - 030].wrt == NO_SEG)
1235 warn_overflow(2, data);
1236 out(offset, segment, &data, OUT_ADDRESS + 2,
1237 ins->oprs[c - 030].segment, ins->oprs[c - 030].wrt);
1238 offset += 2;
1239 break;
1240
1241 case 034:
1242 case 035:
1243 case 036:
1244 case 037:
1245 if (ins->oprs[c - 034].type & (BITS16 | BITS32))
1246 size = (ins->oprs[c - 034].type & BITS16) ? 2 : 4;
1247 else
1248 size = (bits == 16) ? 2 : 4;
1249 data = ins->oprs[c - 034].offset;
1250 warn_overflow(size, data);
1251 out(offset, segment, &data, OUT_ADDRESS + size,
1252 ins->oprs[c - 034].segment, ins->oprs[c - 034].wrt);
1253 offset += size;
1254 break;
1255
1256 case 040:
1257 case 041:
1258 case 042:
1259 case 043:
1260 data = ins->oprs[c - 040].offset;
1261 out(offset, segment, &data, OUT_ADDRESS + 4,
1262 ins->oprs[c - 040].segment, ins->oprs[c - 040].wrt);
1263 offset += 4;
1264 break;
1265
1266 case 044:
1267 case 045:
1268 case 046:
1269 case 047:
1270 data = ins->oprs[c - 044].offset;
1271 size = ins->addr_size >> 3;
1272 warn_overflow(size, data);
1273 out(offset, segment, &data, OUT_ADDRESS + size,
1274 ins->oprs[c - 044].segment, ins->oprs[c - 044].wrt);
1275 offset += size;
1276 break;
1277
1278 case 050:
1279 case 051:
1280 case 052:
1281 case 053:
1282 if (ins->oprs[c - 050].segment != segment)
1283 errfunc(ERR_NONFATAL,
1284 "short relative jump outside segment");
1285 data = ins->oprs[c - 050].offset - insn_end;
1286 if (data > 127 || data < -128)
1287 errfunc(ERR_NONFATAL, "short jump is out of range");
1288 bytes[0] = data;
1289 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1290 offset += 1;
1291 break;
1292
1293 case 054:
1294 case 055:
1295 case 056:
1296 case 057:
1297 data = (int64_t)ins->oprs[c - 054].offset;
1298 out(offset, segment, &data, OUT_ADDRESS + 8,
1299 ins->oprs[c - 054].segment, ins->oprs[c - 054].wrt);
1300 offset += 8;
1301 break;
1302
1303 case 060:
1304 case 061:
1305 case 062:
1306 case 063:
1307 if (ins->oprs[c - 060].segment != segment) {
1308 data = ins->oprs[c - 060].offset;
1309 out(offset, segment, &data,
1310 OUT_REL2ADR + insn_end - offset,
1311 ins->oprs[c - 060].segment, ins->oprs[c - 060].wrt);
1312 } else {
1313 data = ins->oprs[c - 060].offset - insn_end;
1314 out(offset, segment, &data,
1315 OUT_ADDRESS + 2, NO_SEG, NO_SEG);
1316 }
1317 offset += 2;
1318 break;
1319
1320 case 064:
1321 case 065:
1322 case 066:
1323 case 067:
1324 if (ins->oprs[c - 064].type & (BITS16 | BITS32 | BITS64))
1325 size = (ins->oprs[c - 064].type & BITS16) ? 2 : 4;
1326 else
1327 size = (bits == 16) ? 2 : 4;
1328 if (ins->oprs[c - 064].segment != segment) {
1329 int32_t reltype = (size == 2 ? OUT_REL2ADR : OUT_REL4ADR);
1330 data = ins->oprs[c - 064].offset;
1331 out(offset, segment, &data, reltype + insn_end - offset,
1332 ins->oprs[c - 064].segment, ins->oprs[c - 064].wrt);
1333 } else {
1334 data = ins->oprs[c - 064].offset - insn_end;
1335 out(offset, segment, &data,
1336 OUT_ADDRESS + size, NO_SEG, NO_SEG);
1337 }
1338 offset += size;
1339 break;
1340
1341 case 070:
1342 case 071:
1343 case 072:
1344 case 073:
1345 if (ins->oprs[c - 070].segment != segment) {
1346 data = ins->oprs[c - 070].offset;
1347 out(offset, segment, &data,
1348 OUT_REL4ADR + insn_end - offset,
1349 ins->oprs[c - 070].segment, ins->oprs[c - 070].wrt);
1350 } else {
1351 data = ins->oprs[c - 070].offset - insn_end;
1352 out(offset, segment, &data,
1353 OUT_ADDRESS + 4, NO_SEG, NO_SEG);
1354 }
1355 offset += 4;
1356 break;
1357
1358 case 074:
1359 case 075:
1360 case 076:
1361 case 077:
1362 if (ins->oprs[c - 074].segment == NO_SEG)
1363 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1364 " relocatable");
1365 data = 0L;
1366 out(offset, segment, &data, OUT_ADDRESS + 2,
1367 outfmt->segbase(1 + ins->oprs[c - 074].segment),
1368 ins->oprs[c - 074].wrt);
1369 offset += 2;
1370 break;
1371
1372 case 0140:
1373 case 0141:
1374 case 0142:
1375 case 0143:
1376 data = ins->oprs[c - 0140].offset;
1377 if (is_sbyte(ins, c - 0140, 16)) {
1378 bytes[0] = data;
1379 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1380 NO_SEG);
1381 offset++;
1382 } else {
1383 if (ins->oprs[c - 0140].segment == NO_SEG &&
1384 ins->oprs[c - 0140].wrt == NO_SEG)
1385 warn_overflow(2, data);
1386 out(offset, segment, &data, OUT_ADDRESS + 2,
1387 ins->oprs[c - 0140].segment, ins->oprs[c - 0140].wrt);
1388 offset += 2;
1389 }
1390 break;
1391
1392 case 0144:
1393 case 0145:
1394 case 0146:
1395 case 0147:
1396 EMIT_REX();
1397 codes++;
1398 bytes[0] = *codes++;
1399 if (is_sbyte(ins, c - 0144, 16))
1400 bytes[0] |= 2; /* s-bit */
1401 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1402 offset++;
1403 break;
1404
1405 case 0150:
1406 case 0151:
1407 case 0152:
1408 case 0153:
1409 data = ins->oprs[c - 0150].offset;
1410 if (is_sbyte(ins, c - 0150, 32)) {
1411 bytes[0] = data;
1412 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1413 NO_SEG);
1414 offset++;
1415 } else {
1416 out(offset, segment, &data, OUT_ADDRESS + 4,
1417 ins->oprs[c - 0150].segment, ins->oprs[c - 0150].wrt);
1418 offset += 4;
1419 }
1420 break;
1421
1422 case 0154:
1423 case 0155:
1424 case 0156:
1425 case 0157:
1426 EMIT_REX();
1427 codes++;
1428 bytes[0] = *codes++;
1429 if (is_sbyte(ins, c - 0154, 32))
1430 bytes[0] |= 2; /* s-bit */
1431 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1432 offset++;
1433 break;
1434
1435 case 0160:
1436 case 0161:
1437 case 0162:
1438 case 0163:
1439 case 0164:
1440 case 0165:
1441 case 0166:
1442 case 0167:
1443 break;
1444
1445 case 0170:
1446 EMIT_REX();
1447 bytes[0] = 0;
1448 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1449 offset += 1;
1450 break;
1451
1452 case 0171:
1453 bytes[0] =
1454 (ins->drexdst << 4) |
1455 (ins->rex & REX_OC ? 0x08 : 0) |
1456 (ins->rex & (REX_R|REX_X|REX_B));
1457 ins->rex = 0;
1458 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1459 offset++;
1460 break;
1461
1462 case 0300:
1463 case 0301:
1464 case 0302:
1465 case 0303:
1466 break;
1467
1468 case 0310:
1469 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1470 *bytes = 0x67;
1471 out(offset, segment, bytes,
1472 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1473 offset += 1;
1474 } else
1475 offset += 0;
1476 break;
1477
1478 case 0311:
1479 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1480 *bytes = 0x67;
1481 out(offset, segment, bytes,
1482 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1483 offset += 1;
1484 } else
1485 offset += 0;
1486 break;
1487
1488 case 0312:
1489 break;
1490
1491 case 0313:
1492 ins->rex = 0;
1493 break;
1494
1495 case 0320:
1496 if (bits != 16) {
1497 *bytes = 0x66;
1498 out(offset, segment, bytes,
1499 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1500 offset += 1;
1501 } else
1502 offset += 0;
1503 break;
1504
1505 case 0321:
1506 if (bits == 16) {
1507 *bytes = 0x66;
1508 out(offset, segment, bytes,
1509 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1510 offset += 1;
1511 } else
1512 offset += 0;
1513 break;
1514
1515 case 0322:
1516 case 0323:
1517 break;
1518
1519 case 0324:
1520 ins->rex |= REX_W;
1521 break;
1522
1523 case 0330:
1524 *bytes = *codes++ ^ condval[ins->condition];
1525 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1526 offset += 1;
1527 break;
1528
1529 case 0331:
1530 break;
1531
1532 case 0332:
1533 case 0333:
1534 *bytes = c - 0332 + 0xF2;
1535 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1536 offset += 1;
1537 break;
1538
1539 case 0334:
1540 if (ins->rex & REX_R) {
1541 *bytes = 0xF0;
1542 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1543 offset += 1;
1544 }
1545 ins->rex &= ~(REX_L|REX_R);
1546 break;
1547
1548 case 0335:
1549 break;
1550
1551 case 0340:
1552 case 0341:
1553 case 0342:
1554 if (ins->oprs[0].segment != NO_SEG)
1555 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1556 else {
1557 int32_t size = ins->oprs[0].offset << (c - 0340);
1558 if (size > 0)
1559 out(offset, segment, NULL,
1560 OUT_RESERVE + size, NO_SEG, NO_SEG);
1561 offset += size;
1562 }
1563 break;
1564
1565 case 0364:
1566 case 0365:
1567 break;
1568
1569 case 0366:
1570 case 0367:
1571 *bytes = c - 0366 + 0x66;
1572 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1573 offset += 1;
1574 break;
1575
1576 case 0370:
1577 case 0371:
1578 case 0372:
1579 break;
1580
1581 case 0373:
1582 *bytes = bits == 16 ? 3 : 5;
1583 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1584 offset += 1;
1585 break;
1586
1587 default: /* can't do it by 'case' statements */
1588 if (c >= 0100 && c <= 0277) { /* it's an EA */
1589 ea ea_data;
1590 int rfield;
1591 int32_t rflags;
1592 uint8_t *p;
1593 int32_t s;
1594
1595 if (c <= 0177) {
1596 /* pick rfield from operand b */
1597 rflags = regflag(&ins->oprs[c & 7]);
1598 rfield = regvals[ins->oprs[c & 7].basereg];
1599 } else {
1600 /* rfield is constant */
1601 rflags = 0;
1602 rfield = c & 7;
1603 }
1604
1605 if (!process_ea
1606 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1607 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1608 errfunc(ERR_NONFATAL, "invalid effective address");
1609 }
1610
1611 p = bytes;
1612 *p++ = ea_data.modrm;
1613 if (ea_data.sib_present)
1614 *p++ = ea_data.sib;
1615
1616 /* DREX suffixes come between the SIB and the displacement */
1617 if (ins->rex & REX_D) {
1618 *p++ =
1619 (ins->drexdst << 4) |
1620 (ins->rex & REX_OC ? 0x08 : 0) |
1621 (ins->rex & (REX_R|REX_X|REX_B));
1622 ins->rex = 0;
1623 }
1624
1625 s = p - bytes;
1626 out(offset, segment, bytes, OUT_RAWDATA + s,
1627 NO_SEG, NO_SEG);
1628
1629 switch (ea_data.bytes) {
1630 case 0:
1631 break;
1632 case 1:
1633 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1634 data = ins->oprs[(c >> 3) & 7].offset;
1635 out(offset, segment, &data, OUT_ADDRESS + 1,
1636 ins->oprs[(c >> 3) & 7].segment,
1637 ins->oprs[(c >> 3) & 7].wrt);
1638 } else {
1639 *bytes = ins->oprs[(c >> 3) & 7].offset;
1640 out(offset, segment, bytes, OUT_RAWDATA + 1,
1641 NO_SEG, NO_SEG);
1642 }
1643 s++;
1644 break;
1645 case 8:
1646 case 2:
1647 case 4:
1648 data = ins->oprs[(c >> 3) & 7].offset;
1649 out(offset, segment, &data,
1650 (ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS)
1651 + ea_data.bytes,
1652 ins->oprs[(c >> 3) & 7].segment,
1653 ins->oprs[(c >> 3) & 7].wrt);
1654 s += ea_data.bytes;
1655 break;
1656 }
1657 offset += s;
1658 } else
1659 errfunc(ERR_PANIC, "internal instruction table corrupt"
1660 ": instruction code 0x%02X given", c);
1661 }
1662 }
1663
1664 static int32_t regflag(const operand * o)
1665 {
1666 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1667 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1668 }
1669 return reg_flags[o->basereg];
1670 }
1671
1672 static int32_t regval(const operand * o)
1673 {
1674 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1675 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1676 }
1677 return regvals[o->basereg];
1678 }
1679
1680 static int op_rexflags(const operand * o, int mask)
1681 {
1682 int32_t flags;
1683 int val;
1684
1685 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1686 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1687 }
1688
1689 flags = reg_flags[o->basereg];
1690 val = regvals[o->basereg];
1691
1692 return rexflags(val, flags, mask);
1693 }
1694
1695 static int rexflags(int val, int32_t flags, int mask)
1696 {
1697 int rex = 0;
1698
1699 if (val >= 8)
1700 rex |= REX_B|REX_X|REX_R;
1701 if (flags & BITS64)
1702 rex |= REX_W;
1703 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1704 rex |= REX_H;
1705 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1706 rex |= REX_P;
1707
1708 return rex & mask;
1709 }
1710
1711 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1712 {
1713 int i, size[MAX_OPERANDS], asize, oprs, ret;
1714
1715 ret = 100;
1716
1717 /*
1718 * Check the opcode
1719 */
1720 if (itemp->opcode != instruction->opcode)
1721 return 0;
1722
1723 /*
1724 * Count the operands
1725 */
1726 if (itemp->operands != instruction->operands)
1727 return 0;
1728
1729 /*
1730 * Check that no spurious colons or TOs are present
1731 */
1732 for (i = 0; i < itemp->operands; i++)
1733 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1734 return 0;
1735
1736 /*
1737 * Check that the operand flags all match up
1738 */
1739 for (i = 0; i < itemp->operands; i++) {
1740 if (itemp->opd[i] & SAME_AS) {
1741 int j = itemp->opd[i] & ~SAME_AS;
1742 if (instruction->oprs[i].type != instruction->oprs[j].type ||
1743 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
1744 return 0;
1745 } else if (itemp->opd[i] & ~instruction->oprs[i].type ||
1746 ((itemp->opd[i] & SIZE_MASK) &&
1747 ((itemp->opd[i] ^ instruction->oprs[i].type) & SIZE_MASK))) {
1748 if ((itemp->opd[i] & ~instruction->oprs[i].type & ~SIZE_MASK) ||
1749 (instruction->oprs[i].type & SIZE_MASK))
1750 return 0;
1751 else
1752 return 1;
1753 }
1754 }
1755
1756 /*
1757 * Check operand sizes
1758 */
1759 if (itemp->flags & IF_ARMASK) {
1760 memset(size, 0, sizeof size);
1761
1762 switch (itemp->flags & IF_ARMASK) {
1763 case IF_AR0:
1764 i = 0;
1765 break;
1766 case IF_AR1:
1767 i = 1;
1768 break;
1769 case IF_AR2:
1770 i = 2;
1771 break;
1772 case IF_AR3:
1773 i = 3;
1774 break;
1775 default:
1776 break; /* Shouldn't happen */
1777 }
1778 switch (itemp->flags & IF_SMASK) {
1779 case IF_SB:
1780 size[i] = BITS8;
1781 break;
1782 case IF_SW:
1783 size[i] = BITS16;
1784 break;
1785 case IF_SD:
1786 size[i] = BITS32;
1787 break;
1788 case IF_SQ:
1789 size[i] = BITS64;
1790 break;
1791 case IF_SO:
1792 size[i] = BITS128;
1793 break;
1794 default:
1795 break;
1796 }
1797 } else {
1798 asize = 0;
1799 switch (itemp->flags & IF_SMASK) {
1800 case IF_SB:
1801 asize = BITS8;
1802 oprs = itemp->operands;
1803 break;
1804 case IF_SW:
1805 asize = BITS16;
1806 oprs = itemp->operands;
1807 break;
1808 case IF_SD:
1809 asize = BITS32;
1810 oprs = itemp->operands;
1811 break;
1812 case IF_SQ:
1813 asize = BITS64;
1814 oprs = itemp->operands;
1815 break;
1816 case IF_SO:
1817 asize = BITS128;
1818 oprs = itemp->operands;
1819 break;
1820 default:
1821 break;
1822 }
1823 for (i = 0; i < MAX_OPERANDS; i++)
1824 size[i] = asize;
1825 }
1826
1827 if (itemp->flags & (IF_SM | IF_SM2)) {
1828 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
1829 asize = 0;
1830 for (i = 0; i < oprs; i++) {
1831 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
1832 int j;
1833 for (j = 0; j < oprs; j++)
1834 size[j] = asize;
1835 break;
1836 }
1837 }
1838 } else {
1839 oprs = itemp->operands;
1840 }
1841
1842 for (i = 0; i < itemp->operands; i++) {
1843 if (!(itemp->opd[i] & SIZE_MASK) &&
1844 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
1845 return 2;
1846 }
1847
1848 /*
1849 * Check template is okay at the set cpu level
1850 */
1851 if (((itemp->flags & IF_PLEVEL) > cpu))
1852 return 3;
1853
1854 /*
1855 * Check if instruction is available in long mode
1856 */
1857 if ((itemp->flags & IF_NOLONG) && (bits == 64))
1858 return 4;
1859
1860 /*
1861 * Check if special handling needed for Jumps
1862 */
1863 if ((uint8_t)(itemp->code[0]) >= 0370)
1864 return 99;
1865
1866 return ret;
1867 }
1868
1869 static ea *process_ea(operand * input, ea * output, int bits,
1870 int addrbits, int rfield, int32_t rflags, int forw_ref)
1871 {
1872 output->rip = false;
1873
1874 /* REX flags for the rfield operand */
1875 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
1876
1877 if (!(REGISTER & ~input->type)) { /* register direct */
1878 int i;
1879 int32_t f;
1880
1881 if (input->basereg < EXPR_REG_START /* Verify as Register */
1882 || input->basereg >= REG_ENUM_LIMIT)
1883 return NULL;
1884 f = regflag(input);
1885 i = regvals[input->basereg];
1886
1887 if (REG_EA & ~f)
1888 return NULL; /* Invalid EA register */
1889
1890 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
1891
1892 output->sib_present = false; /* no SIB necessary */
1893 output->bytes = 0; /* no offset necessary either */
1894 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
1895 } else { /* it's a memory reference */
1896 if (input->basereg == -1
1897 && (input->indexreg == -1 || input->scale == 0)) {
1898 /* it's a pure offset */
1899 if (bits == 64 && (~input->type & IP_REL)) {
1900 int scale, index, base;
1901 output->sib_present = true;
1902 scale = 0;
1903 index = 4;
1904 base = 5;
1905 output->sib = (scale << 6) | (index << 3) | base;
1906 output->bytes = 4;
1907 output->modrm = 4 | ((rfield & 7) << 3);
1908 output->rip = false;
1909 } else {
1910 output->sib_present = false;
1911 output->bytes = (addrbits != 16 ? 4 : 2);
1912 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
1913 output->rip = bits == 64;
1914 }
1915 } else { /* it's an indirection */
1916 int i = input->indexreg, b = input->basereg, s = input->scale;
1917 int32_t o = input->offset, seg = input->segment;
1918 int hb = input->hintbase, ht = input->hinttype;
1919 int t;
1920 int it, bt;
1921 int32_t ix, bx; /* register flags */
1922
1923 if (s == 0)
1924 i = -1; /* make this easy, at least */
1925
1926 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
1927 it = regvals[i];
1928 ix = reg_flags[i];
1929 } else {
1930 it = -1;
1931 ix = 0;
1932 }
1933
1934 if (b != -1 && b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
1935 bt = regvals[b];
1936 bx = reg_flags[b];
1937 } else {
1938 bt = -1;
1939 bx = 0;
1940 }
1941
1942 /* check for a 32/64-bit memory reference... */
1943 if ((ix|bx) & (BITS32|BITS64)) {
1944 /* it must be a 32/64-bit memory reference. Firstly we have
1945 * to check that all registers involved are type E/Rxx. */
1946 int32_t sok = BITS32|BITS64;
1947
1948 if (it != -1) {
1949 if (!(REG64 & ~ix) || !(REG32 & ~ix))
1950 sok &= ix;
1951 else
1952 return NULL;
1953 }
1954
1955 if (bt != -1) {
1956 if (REG_GPR & ~bx)
1957 return NULL; /* Invalid register */
1958 if (~sok & bx & SIZE_MASK)
1959 return NULL; /* Invalid size */
1960 sok &= ~bx;
1961 }
1962
1963 /* While we're here, ensure the user didn't specify
1964 WORD or QWORD. */
1965 if (input->disp_size == 16 || input->disp_size == 64)
1966 return NULL;
1967
1968 if (addrbits == 16 ||
1969 (addrbits == 32 && !(sok & BITS32)) ||
1970 (addrbits == 64 && !(sok & BITS64)))
1971 return NULL;
1972
1973 /* now reorganize base/index */
1974 if (s == 1 && bt != it && bt != -1 && it != -1 &&
1975 ((hb == b && ht == EAH_NOTBASE)
1976 || (hb == i && ht == EAH_MAKEBASE))) {
1977 /* swap if hints say so */
1978 t = bt, bt = it, it = t;
1979 t = bx, bx = ix, ix = t;
1980 }
1981 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
1982 bt = -1, bx = 0, s++;
1983 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
1984 /* make single reg base, unless hint */
1985 bt = it, bx = ix, it = -1, ix = 0;
1986 }
1987 if (((s == 2 && it != REG_NUM_ESP
1988 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
1989 || s == 5 || s == 9) && bt == -1)
1990 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
1991 if (it == -1 && (bt & 7) != REG_NUM_ESP
1992 && (input->eaflags & EAF_TIMESTWO))
1993 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
1994 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
1995 if (s == 1 && it == REG_NUM_ESP) {
1996 /* swap ESP into base if scale is 1 */
1997 t = it, it = bt, bt = t;
1998 t = ix, ix = bx, bx = t;
1999 }
2000 if (it == REG_NUM_ESP
2001 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2002 return NULL; /* wrong, for various reasons */
2003
2004 output->rex |= rexflags(it, ix, REX_X);
2005 output->rex |= rexflags(bt, bx, REX_B);
2006
2007 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2008 /* no SIB needed */
2009 int mod, rm;
2010
2011 if (bt == -1) {
2012 rm = 5;
2013 mod = 0;
2014 } else {
2015 rm = (bt & 7);
2016 if (rm != REG_NUM_EBP && o == 0 &&
2017 seg == NO_SEG && !forw_ref &&
2018 !(input->eaflags &
2019 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2020 mod = 0;
2021 else if (input->eaflags & EAF_BYTEOFFS ||
2022 (o >= -128 && o <= 127 && seg == NO_SEG
2023 && !forw_ref
2024 && !(input->eaflags & EAF_WORDOFFS)))
2025 mod = 1;
2026 else
2027 mod = 2;
2028 }
2029
2030 output->sib_present = false;
2031 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2032 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2033 } else {
2034 /* we need a SIB */
2035 int mod, scale, index, base;
2036
2037 if (it == -1)
2038 index = 4, s = 1;
2039 else
2040 index = (it & 7);
2041
2042 switch (s) {
2043 case 1:
2044 scale = 0;
2045 break;
2046 case 2:
2047 scale = 1;
2048 break;
2049 case 4:
2050 scale = 2;
2051 break;
2052 case 8:
2053 scale = 3;
2054 break;
2055 default: /* then what the smeg is it? */
2056 return NULL; /* panic */
2057 }
2058
2059 if (bt == -1) {
2060 base = 5;
2061 mod = 0;
2062 } else {
2063 base = (bt & 7);
2064 if (base != REG_NUM_EBP && o == 0 &&
2065 seg == NO_SEG && !forw_ref &&
2066 !(input->eaflags &
2067 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2068 mod = 0;
2069 else if (input->eaflags & EAF_BYTEOFFS ||
2070 (o >= -128 && o <= 127 && seg == NO_SEG
2071 && !forw_ref
2072 && !(input->eaflags & EAF_WORDOFFS)))
2073 mod = 1;
2074 else
2075 mod = 2;
2076 }
2077
2078 output->sib_present = true;
2079 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2080 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2081 output->sib = (scale << 6) | (index << 3) | base;
2082 }
2083 } else { /* it's 16-bit */
2084 int mod, rm;
2085
2086 /* check for 64-bit long mode */
2087 if (addrbits == 64)
2088 return NULL;
2089
2090 /* check all registers are BX, BP, SI or DI */
2091 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2092 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2093 && i != R_SI && i != R_DI))
2094 return NULL;
2095
2096 /* ensure the user didn't specify DWORD/QWORD */
2097 if (input->disp_size == 32 || input->disp_size == 64)
2098 return NULL;
2099
2100 if (s != 1 && i != -1)
2101 return NULL; /* no can do, in 16-bit EA */
2102 if (b == -1 && i != -1) {
2103 int tmp = b;
2104 b = i;
2105 i = tmp;
2106 } /* swap */
2107 if ((b == R_SI || b == R_DI) && i != -1) {
2108 int tmp = b;
2109 b = i;
2110 i = tmp;
2111 }
2112 /* have BX/BP as base, SI/DI index */
2113 if (b == i)
2114 return NULL; /* shouldn't ever happen, in theory */
2115 if (i != -1 && b != -1 &&
2116 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2117 return NULL; /* invalid combinations */
2118 if (b == -1) /* pure offset: handled above */
2119 return NULL; /* so if it gets to here, panic! */
2120
2121 rm = -1;
2122 if (i != -1)
2123 switch (i * 256 + b) {
2124 case R_SI * 256 + R_BX:
2125 rm = 0;
2126 break;
2127 case R_DI * 256 + R_BX:
2128 rm = 1;
2129 break;
2130 case R_SI * 256 + R_BP:
2131 rm = 2;
2132 break;
2133 case R_DI * 256 + R_BP:
2134 rm = 3;
2135 break;
2136 } else
2137 switch (b) {
2138 case R_SI:
2139 rm = 4;
2140 break;
2141 case R_DI:
2142 rm = 5;
2143 break;
2144 case R_BP:
2145 rm = 6;
2146 break;
2147 case R_BX:
2148 rm = 7;
2149 break;
2150 }
2151 if (rm == -1) /* can't happen, in theory */
2152 return NULL; /* so panic if it does */
2153
2154 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2155 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2156 mod = 0;
2157 else if (input->eaflags & EAF_BYTEOFFS ||
2158 (o >= -128 && o <= 127 && seg == NO_SEG
2159 && !forw_ref
2160 && !(input->eaflags & EAF_WORDOFFS)))
2161 mod = 1;
2162 else
2163 mod = 2;
2164
2165 output->sib_present = false; /* no SIB - it's 16-bit */
2166 output->bytes = mod; /* bytes of offset needed */
2167 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2168 }
2169 }
2170 }
2171
2172 output->size = 1 + output->sib_present + output->bytes;
2173 return output;
2174 }
2175
2176 static void add_asp(insn *ins, int addrbits)
2177 {
2178 int j, valid;
2179 int defdisp;
2180
2181 valid = (addrbits == 64) ? 64|32 : 32|16;
2182
2183 switch (ins->prefixes[PPS_ASIZE]) {
2184 case P_A16:
2185 valid &= 16;
2186 break;
2187 case P_A32:
2188 valid &= 32;
2189 break;
2190 case P_A64:
2191 valid &= 64;
2192 break;
2193 case P_ASP:
2194 valid &= (addrbits == 32) ? 16 : 32;
2195 break;
2196 default:
2197 break;
2198 }
2199
2200 for (j = 0; j < ins->operands; j++) {
2201 if (!(MEMORY & ~ins->oprs[j].type)) {
2202 int32_t i, b;
2203
2204 /* Verify as Register */
2205 if (ins->oprs[j].indexreg < EXPR_REG_START
2206 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2207 i = 0;
2208 else
2209 i = reg_flags[ins->oprs[j].indexreg];
2210
2211 /* Verify as Register */
2212 if (ins->oprs[j].basereg < EXPR_REG_START
2213 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2214 b = 0;
2215 else
2216 b = reg_flags[ins->oprs[j].basereg];
2217
2218 if (ins->oprs[j].scale == 0)
2219 i = 0;
2220
2221 if (!i && !b) {
2222 int ds = ins->oprs[j].disp_size;
2223 if ((addrbits != 64 && ds > 8) ||
2224 (addrbits == 64 && ds == 16))
2225 valid &= ds;
2226 } else {
2227 if (!(REG16 & ~b))
2228 valid &= 16;
2229 if (!(REG32 & ~b))
2230 valid &= 32;
2231 if (!(REG64 & ~b))
2232 valid &= 64;
2233
2234 if (!(REG16 & ~i))
2235 valid &= 16;
2236 if (!(REG32 & ~i))
2237 valid &= 32;
2238 if (!(REG64 & ~i))
2239 valid &= 64;
2240 }
2241 }
2242 }
2243
2244 if (valid & addrbits) {
2245 ins->addr_size = addrbits;
2246 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2247 /* Add an address size prefix */
2248 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2249 ins->prefixes[PPS_ASIZE] = pref;
2250 ins->addr_size = (addrbits == 32) ? 16 : 32;
2251 } else {
2252 /* Impossible... */
2253 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2254 ins->addr_size = addrbits; /* Error recovery */
2255 }
2256
2257 defdisp = ins->addr_size == 16 ? 16 : 32;
2258
2259 for (j = 0; j < ins->operands; j++) {
2260 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2261 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2262 != ins->addr_size) {
2263 /* mem_offs sizes must match the address size; if not,
2264 strip the MEM_OFFS bit and match only EA instructions */
2265 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2266 }
2267 }
2268 }
The Netwide Assembler