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insns.dat: fix minor formatting anomalies
[nasm.git] / disasm.c
blobc320f90606a1ffc07a07d6c81dbf320f0c7926e4
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22 #include "tables.h"
23 #include "regdis.h"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
52 uint8_t vex_v;
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
55 };
56
57 #define getu8(x) (*(uint8_t *)(x))
58 #if X86_MEMORY
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
63 #else
64 static uint16_t getu16(uint8_t *data)
65 {
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
67 }
68 static uint32_t getu32(uint8_t *data)
69 {
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
71 }
72 static uint64_t getu64(uint8_t *data)
73 {
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
75 }
76 #endif
77
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
82
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
85 {
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
88
89 regflags |= REGISTER;
90
91 if (!(REG_AL & ~regflags))
92 return R_AL;
93 if (!(REG_AX & ~regflags))
94 return R_AX;
95 if (!(REG_EAX & ~regflags))
96 return R_EAX;
97 if (!(REG_RAX & ~regflags))
98 return R_RAX;
99 if (!(REG_DL & ~regflags))
100 return R_DL;
101 if (!(REG_DX & ~regflags))
102 return R_DX;
103 if (!(REG_EDX & ~regflags))
104 return R_EDX;
105 if (!(REG_RDX & ~regflags))
106 return R_RDX;
107 if (!(REG_CL & ~regflags))
108 return R_CL;
109 if (!(REG_CX & ~regflags))
110 return R_CX;
111 if (!(REG_ECX & ~regflags))
112 return R_ECX;
113 if (!(REG_RCX & ~regflags))
114 return R_RCX;
115 if (!(FPU0 & ~regflags))
116 return R_ST0;
117 if (!(XMM0 & ~regflags))
118 return R_XMM0;
119 if (!(YMM0 & ~regflags))
120 return R_YMM0;
121 if (!(REG_CS & ~regflags))
122 return (regval == 1) ? R_CS : 0;
123 if (!(REG_DESS & ~regflags))
124 return (regval == 0 || regval == 2
125 || regval == 3 ? nasm_rd_sreg[regval] : 0);
126 if (!(REG_FSGS & ~regflags))
127 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_SEG67 & ~regflags))
129 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
130
131 /* All the entries below look up regval in an 16-entry array */
132 if (regval < 0 || regval > 15)
133 return 0;
134
135 if (!(REG8 & ~regflags)) {
136 if (rex & REX_P)
137 return nasm_rd_reg8_rex[regval];
138 else
139 return nasm_rd_reg8[regval];
140 }
141 if (!(REG16 & ~regflags))
142 return nasm_rd_reg16[regval];
143 if (!(REG32 & ~regflags))
144 return nasm_rd_reg32[regval];
145 if (!(REG64 & ~regflags))
146 return nasm_rd_reg64[regval];
147 if (!(REG_SREG & ~regflags))
148 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
149 if (!(REG_CREG & ~regflags))
150 return nasm_rd_creg[regval];
151 if (!(REG_DREG & ~regflags))
152 return nasm_rd_dreg[regval];
153 if (!(REG_TREG & ~regflags)) {
154 if (rex & REX_P)
155 return 0; /* TR registers are ill-defined with rex */
156 return nasm_rd_treg[regval];
157 }
158 if (!(FPUREG & ~regflags))
159 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
160 if (!(MMXREG & ~regflags))
161 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
162 if (!(XMMREG & ~regflags))
163 return nasm_rd_xmmreg[regval];
164 if (!(YMMREG & ~regflags))
165 return nasm_rd_ymmreg[regval];
166
167 return 0;
168 }
169
170 /*
171 * Process a DREX suffix
172 */
173 static uint8_t *do_drex(uint8_t *data, insn *ins)
174 {
175 uint8_t drex = *data++;
176 operand *dst = &ins->oprs[ins->drexdst];
177
178 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
179 return NULL; /* OC0 mismatch */
180 ins->rex = (ins->rex & ~7) | (drex & 7);
181
182 dst->segment = SEG_RMREG;
183 dst->basereg = drex >> 4;
184 return data;
185 }
186
187
188 /*
189 * Process an effective address (ModRM) specification.
190 */
191 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
192 int segsize, operand * op, insn *ins)
193 {
194 int mod, rm, scale, index, base;
195 int rex;
196 uint8_t sib = 0;
197
198 mod = (modrm >> 6) & 03;
199 rm = modrm & 07;
200
201 if (mod != 3 && rm == 4 && asize != 16)
202 sib = *data++;
203
204 if (ins->rex & REX_D) {
205 data = do_drex(data, ins);
206 if (!data)
207 return NULL;
208 }
209 rex = ins->rex;
210
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
214 return data;
215 }
216
217 op->disp_size = 0;
218 op->eaflags = 0;
219
220 if (asize == 16) {
221 /*
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
226 */
227 op->indexreg = op->basereg = -1;
228 op->scale = 1; /* always, in 16 bits */
229 switch (rm) {
230 case 0:
231 op->basereg = R_BX;
232 op->indexreg = R_SI;
233 break;
234 case 1:
235 op->basereg = R_BX;
236 op->indexreg = R_DI;
237 break;
238 case 2:
239 op->basereg = R_BP;
240 op->indexreg = R_SI;
241 break;
242 case 3:
243 op->basereg = R_BP;
244 op->indexreg = R_DI;
245 break;
246 case 4:
247 op->basereg = R_SI;
248 break;
249 case 5:
250 op->basereg = R_DI;
251 break;
252 case 6:
253 op->basereg = R_BP;
254 break;
255 case 7:
256 op->basereg = R_BX;
257 break;
258 }
259 if (rm == 6 && mod == 0) { /* special case */
260 op->basereg = -1;
261 if (segsize != 16)
262 op->disp_size = 16;
263 mod = 2; /* fake disp16 */
264 }
265 switch (mod) {
266 case 0:
267 op->segment |= SEG_NODISP;
268 break;
269 case 1:
270 op->segment |= SEG_DISP8;
271 op->offset = (int8_t)*data++;
272 break;
273 case 2:
274 op->segment |= SEG_DISP16;
275 op->offset = *data++;
276 op->offset |= ((unsigned)*data++) << 8;
277 break;
278 }
279 return data;
280 } else {
281 /*
282 * Once again, <mod> specifies displacement size (this time
283 * none, byte or *dword*), while <rm> specifies the base
284 * register. Again, [EBP] is missing, replaced by a pure
285 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
286 * and RIP-relative addressing in 64-bit mode.
287 *
288 * However, rm=4
289 * indicates not a single base register, but instead the
290 * presence of a SIB byte...
291 */
292 int a64 = asize == 64;
293
294 op->indexreg = -1;
295
296 if (a64)
297 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
298 else
299 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
300
301 if (rm == 5 && mod == 0) {
302 if (segsize == 64) {
303 op->eaflags |= EAF_REL;
304 op->segment |= SEG_RELATIVE;
305 mod = 2; /* fake disp32 */
306 }
307
308 if (asize != 64)
309 op->disp_size = asize;
310
311 op->basereg = -1;
312 mod = 2; /* fake disp32 */
313 }
314
315 if (rm == 4) { /* process SIB */
316 scale = (sib >> 6) & 03;
317 index = (sib >> 3) & 07;
318 base = sib & 07;
319
320 op->scale = 1 << scale;
321
322 if (index == 4 && !(rex & REX_X))
323 op->indexreg = -1; /* ESP/RSP cannot be an index */
324 else if (a64)
325 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
326 else
327 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
328
329 if (base == 5 && mod == 0) {
330 op->basereg = -1;
331 mod = 2; /* Fake disp32 */
332 } else if (a64)
333 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
334 else
335 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
336
337 if (segsize == 16)
338 op->disp_size = 32;
339 }
340
341 switch (mod) {
342 case 0:
343 op->segment |= SEG_NODISP;
344 break;
345 case 1:
346 op->segment |= SEG_DISP8;
347 op->offset = gets8(data);
348 data++;
349 break;
350 case 2:
351 op->segment |= SEG_DISP32;
352 op->offset = gets32(data);
353 data += 4;
354 break;
355 }
356 return data;
357 }
358 }
359
360 /*
361 * Determine whether the instruction template in t corresponds to the data
362 * stream in data. Return the number of bytes matched if so.
363 */
364 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
365
366 static int matches(const struct itemplate *t, uint8_t *data,
367 const struct prefix_info *prefix, int segsize, insn *ins)
368 {
369 uint8_t *r = (uint8_t *)(t->code);
370 uint8_t *origdata = data;
371 bool a_used = false, o_used = false;
372 enum prefixes drep = 0;
373 uint8_t lock = prefix->lock;
374 int osize = prefix->osize;
375 int asize = prefix->asize;
376 int i, c;
377 int op1, op2;
378 struct operand *opx, *opy;
379 uint8_t opex = 0;
380 int s_field_for = -1; /* No 144/154 series code encountered */
381 bool vex_ok = false;
382 int regmask = (segsize == 64) ? 15 : 7;
383
384 for (i = 0; i < MAX_OPERANDS; i++) {
385 ins->oprs[i].segment = ins->oprs[i].disp_size =
386 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
387 }
388 ins->condition = -1;
389 ins->rex = prefix->rex;
390 memset(ins->prefixes, 0, sizeof ins->prefixes);
391
392 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
393 return false;
394
395 if (prefix->rep == 0xF2)
396 drep = P_REPNE;
397 else if (prefix->rep == 0xF3)
398 drep = P_REP;
399
400 while ((c = *r++) != 0) {
401 op1 = (c & 3) + ((opex & 1) << 2);
402 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
403 opx = &ins->oprs[op1];
404 opy = &ins->oprs[op2];
405 opex = 0;
406
407 switch (c) {
408 case 01:
409 case 02:
410 case 03:
411 case 04:
412 while (c--)
413 if (*r++ != *data++)
414 return false;
415 break;
416
417 case 05:
418 case 06:
419 case 07:
420 opex = c;
421 break;
422
423 case4(010):
424 {
425 int t = *r++, d = *data++;
426 if (d < t || d > t + 7)
427 return false;
428 else {
429 opx->basereg = (d-t)+
430 (ins->rex & REX_B ? 8 : 0);
431 opx->segment |= SEG_RMREG;
432 }
433 break;
434 }
435
436 case4(014):
437 case4(0274):
438 opx->offset = (int8_t)*data++;
439 opx->segment |= SEG_SIGNED;
440 break;
441
442 case4(020):
443 opx->offset = *data++;
444 break;
445
446 case4(024):
447 opx->offset = *data++;
448 break;
449
450 case4(030):
451 opx->offset = getu16(data);
452 data += 2;
453 break;
454
455 case4(034):
456 if (osize == 32) {
457 opx->offset = getu32(data);
458 data += 4;
459 } else {
460 opx->offset = getu16(data);
461 data += 2;
462 }
463 if (segsize != asize)
464 opx->disp_size = asize;
465 break;
466
467 case4(040):
468 case4(0254):
469 opx->offset = getu32(data);
470 data += 4;
471 break;
472
473 case4(044):
474 switch (asize) {
475 case 16:
476 opx->offset = getu16(data);
477 data += 2;
478 if (segsize != 16)
479 opx->disp_size = 16;
480 break;
481 case 32:
482 opx->offset = getu32(data);
483 data += 4;
484 if (segsize == 16)
485 opx->disp_size = 32;
486 break;
487 case 64:
488 opx->offset = getu64(data);
489 opx->disp_size = 64;
490 data += 8;
491 break;
492 }
493 break;
494
495 case4(050):
496 opx->offset = gets8(data++);
497 opx->segment |= SEG_RELATIVE;
498 break;
499
500 case4(054):
501 opx->offset = getu64(data);
502 data += 8;
503 break;
504
505 case4(060):
506 opx->offset = gets16(data);
507 data += 2;
508 opx->segment |= SEG_RELATIVE;
509 opx->segment &= ~SEG_32BIT;
510 break;
511
512 case4(064):
513 opx->segment |= SEG_RELATIVE;
514 if (osize == 16) {
515 opx->offset = gets16(data);
516 data += 2;
517 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
518 } else if (osize == 32) {
519 opx->offset = gets32(data);
520 data += 4;
521 opx->segment &= ~SEG_64BIT;
522 opx->segment |= SEG_32BIT;
523 }
524 if (segsize != osize) {
525 opx->type =
526 (opx->type & ~SIZE_MASK)
527 | ((osize == 16) ? BITS16 : BITS32);
528 }
529 break;
530
531 case4(070):
532 opx->offset = gets32(data);
533 data += 4;
534 opx->segment |= SEG_32BIT | SEG_RELATIVE;
535 break;
536
537 case4(0100):
538 case4(0110):
539 case4(0120):
540 case4(0130):
541 {
542 int modrm = *data++;
543 opx->segment |= SEG_RMREG;
544 data = do_ea(data, modrm, asize, segsize, opy, ins);
545 if (!data)
546 return false;
547 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
548 break;
549 }
550
551 case4(0140):
552 if (s_field_for == op1) {
553 opx->offset = gets8(data);
554 data++;
555 } else {
556 opx->offset = getu16(data);
557 data += 2;
558 }
559 break;
560
561 case4(0144):
562 case4(0154):
563 s_field_for = (*data & 0x02) ? op1 : -1;
564 if ((*data++ & ~0x02) != *r++)
565 return false;
566 break;
567
568 case4(0150):
569 if (s_field_for == op1) {
570 opx->offset = gets8(data);
571 data++;
572 } else {
573 opx->offset = getu32(data);
574 data += 4;
575 }
576 break;
577
578 case4(0160):
579 ins->rex |= REX_D;
580 ins->drexdst = op1;
581 break;
582
583 case4(0164):
584 ins->rex |= REX_D|REX_OC;
585 ins->drexdst = op1;
586 break;
587
588 case 0171:
589 data = do_drex(data, ins);
590 if (!data)
591 return false;
592 break;
593
594 case 0172:
595 {
596 uint8_t ximm = *data++;
597 c = *r++;
598 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
599 ins->oprs[c >> 3].segment |= SEG_RMREG;
600 ins->oprs[c & 7].offset = ximm & 15;
601 }
602 break;
603
604 case 0173:
605 {
606 uint8_t ximm = *data++;
607 c = *r++;
608
609 if ((c ^ ximm) & 15)
610 return false;
611
612 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
613 ins->oprs[c >> 4].segment |= SEG_RMREG;
614 }
615 break;
616
617 case 0174:
618 {
619 uint8_t ximm = *data++;
620 c = *r++;
621
622 ins->oprs[c].basereg = (ximm >> 4) & regmask;
623 ins->oprs[c].segment |= SEG_RMREG;
624 }
625 break;
626
627 case4(0200):
628 case4(0204):
629 case4(0210):
630 case4(0214):
631 case4(0220):
632 case4(0224):
633 case4(0230):
634 case4(0234):
635 {
636 int modrm = *data++;
637 if (((modrm >> 3) & 07) != (c & 07))
638 return false; /* spare field doesn't match up */
639 data = do_ea(data, modrm, asize, segsize, opy, ins);
640 if (!data)
641 return false;
642 break;
643 }
644
645 case4(0260):
646 {
647 int vexm = *r++;
648 int vexwlp = *r++;
649 ins->rex |= REX_V;
650 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
651 return false;
652
653 if ((vexm & 0x1f) != prefix->vex_m)
654 return false;
655
656 switch (vexwlp & 030) {
657 case 000:
658 if (prefix->rex & REX_W)
659 return false;
660 break;
661 case 010:
662 if (!(prefix->rex & REX_W))
663 return false;
664 ins->rex &= ~REX_W;
665 break;
666 case 020: /* VEX.W is a don't care */
667 ins->rex &= ~REX_W;
668 break;
669 case 030:
670 break;
671 }
672
673 if ((vexwlp & 007) != prefix->vex_lp)
674 return false;
675
676 opx->segment |= SEG_RMREG;
677 opx->basereg = prefix->vex_v;
678 vex_ok = true;
679 break;
680 }
681
682 case 0270:
683 {
684 int vexm = *r++;
685 int vexwlp = *r++;
686 ins->rex |= REX_V;
687 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
688 return false;
689
690 if ((vexm & 0x1f) != prefix->vex_m)
691 return false;
692
693 switch (vexwlp & 030) {
694 case 000:
695 if (ins->rex & REX_W)
696 return false;
697 break;
698 case 010:
699 if (!(ins->rex & REX_W))
700 return false;
701 break;
702 default:
703 break; /* Need to do anything special here? */
704 }
705
706 if ((vexwlp & 007) != prefix->vex_lp)
707 return false;
708
709 if (prefix->vex_v != 0)
710 return false;
711
712 vex_ok = true;
713 break;
714 }
715
716 case 0310:
717 if (asize != 16)
718 return false;
719 else
720 a_used = true;
721 break;
722
723 case 0311:
724 if (asize == 16)
725 return false;
726 else
727 a_used = true;
728 break;
729
730 case 0312:
731 if (asize != segsize)
732 return false;
733 else
734 a_used = true;
735 break;
736
737 case 0313:
738 if (asize != 64)
739 return false;
740 else
741 a_used = true;
742 break;
743
744 case 0314:
745 if (prefix->rex & REX_B)
746 return false;
747 break;
748
749 case 0315:
750 if (prefix->rex & REX_X)
751 return false;
752 break;
753
754 case 0316:
755 if (prefix->rex & REX_R)
756 return false;
757 break;
758
759 case 0317:
760 if (prefix->rex & REX_W)
761 return false;
762 break;
763
764 case 0320:
765 if (osize != 16)
766 return false;
767 else
768 o_used = true;
769 break;
770
771 case 0321:
772 if (osize != 32)
773 return false;
774 else
775 o_used = true;
776 break;
777
778 case 0322:
779 if (osize != (segsize == 16) ? 16 : 32)
780 return false;
781 else
782 o_used = true;
783 break;
784
785 case 0323:
786 ins->rex |= REX_W; /* 64-bit only instruction */
787 osize = 64;
788 o_used = true;
789 break;
790
791 case 0324:
792 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
793 return false;
794 o_used = true;
795 break;
796
797 case 0330:
798 {
799 int t = *r++, d = *data++;
800 if (d < t || d > t + 15)
801 return false;
802 else
803 ins->condition = d - t;
804 break;
805 }
806
807 case 0331:
808 if (prefix->rep)
809 return false;
810 break;
811
812 case 0332:
813 if (prefix->rep != 0xF2)
814 return false;
815 drep = 0;
816 break;
817
818 case 0333:
819 if (prefix->rep != 0xF3)
820 return false;
821 drep = 0;
822 break;
823
824 case 0334:
825 if (lock) {
826 ins->rex |= REX_R;
827 lock = 0;
828 }
829 break;
830
831 case 0335:
832 if (drep == P_REP)
833 drep = P_REPE;
834 break;
835
836 case 0336:
837 case 0337:
838 break;
839
840 case 0340:
841 return false;
842
843 case4(0344):
844 ins->oprs[0].basereg = (*data++ >> 3) & 7;
845 break;
846
847 case 0360:
848 if (prefix->osp || prefix->rep)
849 return false;
850 break;
851
852 case 0361:
853 if (!prefix->osp || prefix->rep)
854 return false;
855 o_used = true;
856 break;
857
858 case 0362:
859 if (prefix->osp || prefix->rep != 0xf2)
860 return false;
861 drep = 0;
862 break;
863
864 case 0363:
865 if (prefix->osp || prefix->rep != 0xf3)
866 return false;
867 drep = 0;
868 break;
869
870 case 0364:
871 if (prefix->osp)
872 return false;
873 break;
874
875 case 0365:
876 if (prefix->asp)
877 return false;
878 break;
879
880 case 0366:
881 if (!prefix->osp)
882 return false;
883 o_used = true;
884 break;
885
886 case 0367:
887 if (!prefix->asp)
888 return false;
889 a_used = true;
890 break;
891
892 default:
893 return false; /* Unknown code */
894 }
895 }
896
897 if (!vex_ok && (ins->rex & REX_V))
898 return false;
899
900 /* REX cannot be combined with DREX or VEX */
901 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
902 return false;
903
904 /*
905 * Check for unused rep or a/o prefixes.
906 */
907 for (i = 0; i < t->operands; i++) {
908 if (ins->oprs[i].segment != SEG_RMREG)
909 a_used = true;
910 }
911
912 if (lock) {
913 if (ins->prefixes[PPS_LREP])
914 return false;
915 ins->prefixes[PPS_LREP] = P_LOCK;
916 }
917 if (drep) {
918 if (ins->prefixes[PPS_LREP])
919 return false;
920 ins->prefixes[PPS_LREP] = drep;
921 }
922 if (!o_used) {
923 if (osize != ((segsize == 16) ? 16 : 32)) {
924 enum prefixes pfx = 0;
925
926 switch (osize) {
927 case 16:
928 pfx = P_O16;
929 break;
930 case 32:
931 pfx = P_O32;
932 break;
933 case 64:
934 pfx = P_O64;
935 break;
936 }
937
938 if (ins->prefixes[PPS_OSIZE])
939 return false;
940 ins->prefixes[PPS_OSIZE] = pfx;
941 }
942 }
943 if (!a_used && asize != segsize) {
944 if (ins->prefixes[PPS_ASIZE])
945 return false;
946 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
947 }
948
949 /* Fix: check for redundant REX prefixes */
950
951 return data - origdata;
952 }
953
954 /* Condition names for disassembly, sorted by x86 code */
955 static const char * const condition_name[16] = {
956 "o", "no", "c", "nc", "z", "nz", "na", "a",
957 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
958 };
959
960 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
961 int32_t offset, int autosync, uint32_t prefer)
962 {
963 const struct itemplate * const *p, * const *best_p;
964 const struct disasm_index *ix;
965 uint8_t *dp;
966 int length, best_length = 0;
967 char *segover;
968 int i, slen, colon, n;
969 uint8_t *origdata;
970 int works;
971 insn tmp_ins, ins;
972 uint32_t goodness, best;
973 int best_pref;
974 struct prefix_info prefix;
975 bool end_prefix;
976
977 memset(&ins, 0, sizeof ins);
978
979 /*
980 * Scan for prefixes.
981 */
982 memset(&prefix, 0, sizeof prefix);
983 prefix.asize = segsize;
984 prefix.osize = (segsize == 64) ? 32 : segsize;
985 segover = NULL;
986 origdata = data;
987
988 ix = itable;
989
990 end_prefix = false;
991 while (!end_prefix) {
992 switch (*data) {
993 case 0xF2:
994 case 0xF3:
995 prefix.rep = *data++;
996 break;
997
998 case 0xF0:
999 prefix.lock = *data++;
1000 break;
1001
1002 case 0x2E:
1003 segover = "cs", prefix.seg = *data++;
1004 break;
1005 case 0x36:
1006 segover = "ss", prefix.seg = *data++;
1007 break;
1008 case 0x3E:
1009 segover = "ds", prefix.seg = *data++;
1010 break;
1011 case 0x26:
1012 segover = "es", prefix.seg = *data++;
1013 break;
1014 case 0x64:
1015 segover = "fs", prefix.seg = *data++;
1016 break;
1017 case 0x65:
1018 segover = "gs", prefix.seg = *data++;
1019 break;
1020
1021 case 0x66:
1022 prefix.osize = (segsize == 16) ? 32 : 16;
1023 prefix.osp = *data++;
1024 break;
1025 case 0x67:
1026 prefix.asize = (segsize == 32) ? 16 : 32;
1027 prefix.asp = *data++;
1028 break;
1029
1030 case 0xC4:
1031 case 0xC5:
1032 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1033 prefix.vex[0] = *data++;
1034 prefix.vex[1] = *data++;
1035
1036 prefix.rex = REX_V;
1037
1038 if (prefix.vex[0] == 0xc4) {
1039 prefix.vex[2] = *data++;
1040 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1041 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1042 prefix.vex_m = prefix.vex[1] & 0x1f;
1043 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1044 prefix.vex_lp = prefix.vex[2] & 7;
1045 } else {
1046 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1047 prefix.vex_m = 1;
1048 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1049 prefix.vex_lp = prefix.vex[1] & 7;
1050 }
1051
1052 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1053 }
1054 end_prefix = true;
1055 break;
1056
1057 case REX_P + 0x0:
1058 case REX_P + 0x1:
1059 case REX_P + 0x2:
1060 case REX_P + 0x3:
1061 case REX_P + 0x4:
1062 case REX_P + 0x5:
1063 case REX_P + 0x6:
1064 case REX_P + 0x7:
1065 case REX_P + 0x8:
1066 case REX_P + 0x9:
1067 case REX_P + 0xA:
1068 case REX_P + 0xB:
1069 case REX_P + 0xC:
1070 case REX_P + 0xD:
1071 case REX_P + 0xE:
1072 case REX_P + 0xF:
1073 if (segsize == 64) {
1074 prefix.rex = *data++;
1075 if (prefix.rex & REX_W)
1076 prefix.osize = 64;
1077 }
1078 end_prefix = true;
1079 break;
1080
1081 default:
1082 end_prefix = true;
1083 break;
1084 }
1085 }
1086
1087 best = -1; /* Worst possible */
1088 best_p = NULL;
1089 best_pref = INT_MAX;
1090
1091 if (!ix)
1092 return 0; /* No instruction table at all... */
1093
1094 dp = data;
1095 ix += *dp++;
1096 while (ix->n == -1) {
1097 ix = (const struct disasm_index *)ix->p + *dp++;
1098 }
1099
1100 p = (const struct itemplate * const *)ix->p;
1101 for (n = ix->n; n; n--, p++) {
1102 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1103 works = true;
1104 /*
1105 * Final check to make sure the types of r/m match up.
1106 * XXX: Need to make sure this is actually correct.
1107 */
1108 for (i = 0; i < (*p)->operands; i++) {
1109 if (!((*p)->opd[i] & SAME_AS) &&
1110 (
1111 /* If it's a mem-only EA but we have a
1112 register, die. */
1113 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1114 !(MEMORY & ~(*p)->opd[i])) ||
1115 /* If it's a reg-only EA but we have a memory
1116 ref, die. */
1117 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1118 !(REG_EA & ~(*p)->opd[i]) &&
1119 !((*p)->opd[i] & REG_SMASK)) ||
1120 /* Register type mismatch (eg FS vs REG_DESS):
1121 die. */
1122 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1123 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1124 !whichreg((*p)->opd[i],
1125 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1126 )) {
1127 works = false;
1128 break;
1129 }
1130 }
1131
1132 /*
1133 * Note: we always prefer instructions which incorporate
1134 * prefixes in the instructions themselves. This is to allow
1135 * e.g. PAUSE to be preferred to REP NOP, and deal with
1136 * MMX/SSE instructions where prefixes are used to select
1137 * between MMX and SSE register sets or outright opcode
1138 * selection.
1139 */
1140 if (works) {
1141 int i, nprefix;
1142 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1143 nprefix = 0;
1144 for (i = 0; i < MAXPREFIX; i++)
1145 if (tmp_ins.prefixes[i])
1146 nprefix++;
1147 if (nprefix < best_pref ||
1148 (nprefix == best_pref && goodness < best)) {
1149 /* This is the best one found so far */
1150 best = goodness;
1151 best_p = p;
1152 best_pref = nprefix;
1153 best_length = length;
1154 ins = tmp_ins;
1155 }
1156 }
1157 }
1158 }
1159
1160 if (!best_p)
1161 return 0; /* no instruction was matched */
1162
1163 /* Pick the best match */
1164 p = best_p;
1165 length = best_length;
1166
1167 slen = 0;
1168
1169 /* TODO: snprintf returns the value that the string would have if
1170 * the buffer were long enough, and not the actual length of
1171 * the returned string, so each instance of using the return
1172 * value of snprintf should actually be checked to assure that
1173 * the return value is "sane." Maybe a macro wrapper could
1174 * be used for that purpose.
1175 */
1176 for (i = 0; i < MAXPREFIX; i++)
1177 switch (ins.prefixes[i]) {
1178 case P_LOCK:
1179 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1180 break;
1181 case P_REP:
1182 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1183 break;
1184 case P_REPE:
1185 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1186 break;
1187 case P_REPNE:
1188 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1189 break;
1190 case P_A16:
1191 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1192 break;
1193 case P_A32:
1194 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1195 break;
1196 case P_A64:
1197 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1198 break;
1199 case P_O16:
1200 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1201 break;
1202 case P_O32:
1203 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1204 break;
1205 case P_O64:
1206 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1207 break;
1208 default:
1209 break;
1210 }
1211
1212 i = (*p)->opcode;
1213 if (i >= FIRST_COND_OPCODE)
1214 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1215 nasm_insn_names[i], condition_name[ins.condition]);
1216 else
1217 slen += snprintf(output + slen, outbufsize - slen, "%s",
1218 nasm_insn_names[i]);
1219
1220 colon = false;
1221 length += data - origdata; /* fix up for prefixes */
1222 for (i = 0; i < (*p)->operands; i++) {
1223 opflags_t t = (*p)->opd[i];
1224 const operand *o = &ins.oprs[i];
1225 int64_t offs;
1226
1227 if (t & SAME_AS) {
1228 o = &ins.oprs[t & ~SAME_AS];
1229 t = (*p)->opd[t & ~SAME_AS];
1230 }
1231
1232 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1233
1234 offs = o->offset;
1235 if (o->segment & SEG_RELATIVE) {
1236 offs += offset + length;
1237 /*
1238 * sort out wraparound
1239 */
1240 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1241 offs &= 0xffff;
1242 else if (segsize != 64)
1243 offs &= 0xffffffff;
1244
1245 /*
1246 * add sync marker, if autosync is on
1247 */
1248 if (autosync)
1249 add_sync(offs, 0L);
1250 }
1251
1252 if (t & COLON)
1253 colon = true;
1254 else
1255 colon = false;
1256
1257 if ((t & (REGISTER | FPUREG)) ||
1258 (o->segment & SEG_RMREG)) {
1259 enum reg_enum reg;
1260 reg = whichreg(t, o->basereg, ins.rex);
1261 if (t & TO)
1262 slen += snprintf(output + slen, outbufsize - slen, "to ");
1263 slen += snprintf(output + slen, outbufsize - slen, "%s",
1264 nasm_reg_names[reg-EXPR_REG_START]);
1265 } else if (!(UNITY & ~t)) {
1266 output[slen++] = '1';
1267 } else if (t & IMMEDIATE) {
1268 if (t & BITS8) {
1269 slen +=
1270 snprintf(output + slen, outbufsize - slen, "byte ");
1271 if (o->segment & SEG_SIGNED) {
1272 if (offs < 0) {
1273 offs *= -1;
1274 output[slen++] = '-';
1275 } else
1276 output[slen++] = '+';
1277 }
1278 } else if (t & BITS16) {
1279 slen +=
1280 snprintf(output + slen, outbufsize - slen, "word ");
1281 } else if (t & BITS32) {
1282 slen +=
1283 snprintf(output + slen, outbufsize - slen, "dword ");
1284 } else if (t & BITS64) {
1285 slen +=
1286 snprintf(output + slen, outbufsize - slen, "qword ");
1287 } else if (t & NEAR) {
1288 slen +=
1289 snprintf(output + slen, outbufsize - slen, "near ");
1290 } else if (t & SHORT) {
1291 slen +=
1292 snprintf(output + slen, outbufsize - slen, "short ");
1293 }
1294 slen +=
1295 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1296 offs);
1297 } else if (!(MEM_OFFS & ~t)) {
1298 slen +=
1299 snprintf(output + slen, outbufsize - slen,
1300 "[%s%s%s0x%"PRIx64"]",
1301 (segover ? segover : ""),
1302 (segover ? ":" : ""),
1303 (o->disp_size == 64 ? "qword " :
1304 o->disp_size == 32 ? "dword " :
1305 o->disp_size == 16 ? "word " : ""), offs);
1306 segover = NULL;
1307 } else if (!(REGMEM & ~t)) {
1308 int started = false;
1309 if (t & BITS8)
1310 slen +=
1311 snprintf(output + slen, outbufsize - slen, "byte ");
1312 if (t & BITS16)
1313 slen +=
1314 snprintf(output + slen, outbufsize - slen, "word ");
1315 if (t & BITS32)
1316 slen +=
1317 snprintf(output + slen, outbufsize - slen, "dword ");
1318 if (t & BITS64)
1319 slen +=
1320 snprintf(output + slen, outbufsize - slen, "qword ");
1321 if (t & BITS80)
1322 slen +=
1323 snprintf(output + slen, outbufsize - slen, "tword ");
1324 if (t & BITS128)
1325 slen +=
1326 snprintf(output + slen, outbufsize - slen, "oword ");
1327 if (t & BITS256)
1328 slen +=
1329 snprintf(output + slen, outbufsize - slen, "yword ");
1330 if (t & FAR)
1331 slen += snprintf(output + slen, outbufsize - slen, "far ");
1332 if (t & NEAR)
1333 slen +=
1334 snprintf(output + slen, outbufsize - slen, "near ");
1335 output[slen++] = '[';
1336 if (o->disp_size)
1337 slen += snprintf(output + slen, outbufsize - slen, "%s",
1338 (o->disp_size == 64 ? "qword " :
1339 o->disp_size == 32 ? "dword " :
1340 o->disp_size == 16 ? "word " :
1341 ""));
1342 if (o->eaflags & EAF_REL)
1343 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1344 if (segover) {
1345 slen +=
1346 snprintf(output + slen, outbufsize - slen, "%s:",
1347 segover);
1348 segover = NULL;
1349 }
1350 if (o->basereg != -1) {
1351 slen += snprintf(output + slen, outbufsize - slen, "%s",
1352 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1353 started = true;
1354 }
1355 if (o->indexreg != -1) {
1356 if (started)
1357 output[slen++] = '+';
1358 slen += snprintf(output + slen, outbufsize - slen, "%s",
1359 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1360 if (o->scale > 1)
1361 slen +=
1362 snprintf(output + slen, outbufsize - slen, "*%d",
1363 o->scale);
1364 started = true;
1365 }
1366
1367
1368 if (o->segment & SEG_DISP8) {
1369 const char *prefix;
1370 uint8_t offset = offs;
1371 if ((int8_t)offset < 0) {
1372 prefix = "-";
1373 offset = -offset;
1374 } else {
1375 prefix = "+";
1376 }
1377 slen +=
1378 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1379 prefix, offset);
1380 } else if (o->segment & SEG_DISP16) {
1381 const char *prefix;
1382 uint16_t offset = offs;
1383 if ((int16_t)offset < 0 && started) {
1384 offset = -offset;
1385 prefix = "-";
1386 } else {
1387 prefix = started ? "+" : "";
1388 }
1389 slen +=
1390 snprintf(output + slen, outbufsize - slen,
1391 "%s0x%"PRIx16"", prefix, offset);
1392 } else if (o->segment & SEG_DISP32) {
1393 if (prefix.asize == 64) {
1394 const char *prefix;
1395 uint64_t offset = (int64_t)(int32_t)offs;
1396 if ((int32_t)offs < 0 && started) {
1397 offset = -offset;
1398 prefix = "-";
1399 } else {
1400 prefix = started ? "+" : "";
1401 }
1402 slen +=
1403 snprintf(output + slen, outbufsize - slen,
1404 "%s0x%"PRIx64"", prefix, offset);
1405 } else {
1406 const char *prefix;
1407 uint32_t offset = offs;
1408 if ((int32_t) offset < 0 && started) {
1409 offset = -offset;
1410 prefix = "-";
1411 } else {
1412 prefix = started ? "+" : "";
1413 }
1414 slen +=
1415 snprintf(output + slen, outbufsize - slen,
1416 "%s0x%"PRIx32"", prefix, offset);
1417 }
1418 }
1419 output[slen++] = ']';
1420 } else {
1421 slen +=
1422 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1423 i);
1424 }
1425 }
1426 output[slen] = '\0';
1427 if (segover) { /* unused segment override */
1428 char *p = output;
1429 int count = slen + 1;
1430 while (count--)
1431 p[count + 3] = p[count];
1432 strncpy(output, segover, 2);
1433 output[2] = ' ';
1434 }
1435 return length;
1436 }
1437
1438 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1439 {
1440 snprintf(output, outbufsize, "db 0x%02X", *data);
1441 return 1;
1442 }
The Netwide Assembler