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Add missing header file in labels.c
[nasm.git] / disasm.c
blob2f68b1d051b5b0dd53588c82567df9e4228f5d06
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43 #include <inttypes.h>
44
45 #include "nasm.h"
46 #include "disasm.h"
47 #include "sync.h"
48 #include "insns.h"
49 #include "tables.h"
50 #include "regdis.h"
51 #include "disp8.h"
52
53 /*
54 * Flags that go into the `segment' field of `insn' structures
55 * during disassembly.
56 */
57 #define SEG_RELATIVE 1
58 #define SEG_32BIT 2
59 #define SEG_RMREG 4
60 #define SEG_DISP8 8
61 #define SEG_DISP16 16
62 #define SEG_DISP32 32
63 #define SEG_NODISP 64
64 #define SEG_SIGNED 128
65 #define SEG_64BIT 256
66
67 /*
68 * Prefix information
69 */
70 struct prefix_info {
71 uint8_t osize; /* Operand size */
72 uint8_t asize; /* Address size */
73 uint8_t osp; /* Operand size prefix present */
74 uint8_t asp; /* Address size prefix present */
75 uint8_t rep; /* Rep prefix present */
76 uint8_t seg; /* Segment override prefix present */
77 uint8_t wait; /* WAIT "prefix" present */
78 uint8_t lock; /* Lock prefix present */
79 uint8_t vex[3]; /* VEX prefix present */
80 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
81 uint8_t vex_m; /* VEX.M field */
82 uint8_t vex_v;
83 uint8_t vex_lp; /* VEX.LP fields */
84 uint32_t rex; /* REX prefix present */
85 uint8_t evex[3]; /* EVEX prefix present */
86 };
87
88 #define getu8(x) (*(uint8_t *)(x))
89 #if X86_MEMORY
90 /* Littleendian CPU which can handle unaligned references */
91 #define getu16(x) (*(uint16_t *)(x))
92 #define getu32(x) (*(uint32_t *)(x))
93 #define getu64(x) (*(uint64_t *)(x))
94 #else
95 static uint16_t getu16(uint8_t *data)
96 {
97 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
98 }
99 static uint32_t getu32(uint8_t *data)
100 {
101 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
102 }
103 static uint64_t getu64(uint8_t *data)
104 {
105 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
106 }
107 #endif
108
109 #define gets8(x) ((int8_t)getu8(x))
110 #define gets16(x) ((int16_t)getu16(x))
111 #define gets32(x) ((int32_t)getu32(x))
112 #define gets64(x) ((int64_t)getu64(x))
113
114 /* Important: regval must already have been adjusted for rex extensions */
115 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
116 {
117 size_t i;
118
119 static const struct {
120 opflags_t flags;
121 enum reg_enum reg;
122 } specific_registers[] = {
123 {REG_AL, R_AL},
124 {REG_AX, R_AX},
125 {REG_EAX, R_EAX},
126 {REG_RAX, R_RAX},
127 {REG_DL, R_DL},
128 {REG_DX, R_DX},
129 {REG_EDX, R_EDX},
130 {REG_RDX, R_RDX},
131 {REG_CL, R_CL},
132 {REG_CX, R_CX},
133 {REG_ECX, R_ECX},
134 {REG_RCX, R_RCX},
135 {FPU0, R_ST0},
136 {XMM0, R_XMM0},
137 {YMM0, R_YMM0},
138 {ZMM0, R_ZMM0},
139 {REG_ES, R_ES},
140 {REG_CS, R_CS},
141 {REG_SS, R_SS},
142 {REG_DS, R_DS},
143 {REG_FS, R_FS},
144 {REG_GS, R_GS},
145 {OPMASK0, R_K0},
146 };
147
148 if (!(regflags & (REGISTER|REGMEM)))
149 return 0; /* Registers not permissible?! */
150
151 regflags |= REGISTER;
152
153 for (i = 0; i < ARRAY_SIZE(specific_registers); i++)
154 if (!(specific_registers[i].flags & ~regflags))
155 return specific_registers[i].reg;
156
157 /* All the entries below look up regval in an 16-entry array */
158 if (regval < 0 || regval > (rex & REX_EV ? 31 : 15))
159 return 0;
160
161 if (!(REG8 & ~regflags)) {
162 if (rex & (REX_P|REX_NH))
163 return nasm_rd_reg8_rex[regval];
164 else
165 return nasm_rd_reg8[regval];
166 }
167 if (!(REG16 & ~regflags))
168 return nasm_rd_reg16[regval];
169 if (!(REG32 & ~regflags))
170 return nasm_rd_reg32[regval];
171 if (!(REG64 & ~regflags))
172 return nasm_rd_reg64[regval];
173 if (!(REG_SREG & ~regflags))
174 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
175 if (!(REG_CREG & ~regflags))
176 return nasm_rd_creg[regval];
177 if (!(REG_DREG & ~regflags))
178 return nasm_rd_dreg[regval];
179 if (!(REG_TREG & ~regflags)) {
180 if (regval > 7)
181 return 0; /* TR registers are ill-defined with rex */
182 return nasm_rd_treg[regval];
183 }
184 if (!(FPUREG & ~regflags))
185 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
186 if (!(MMXREG & ~regflags))
187 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
188 if (!(XMMREG & ~regflags))
189 return nasm_rd_xmmreg[regval];
190 if (!(YMMREG & ~regflags))
191 return nasm_rd_ymmreg[regval];
192 if (!(ZMMREG & ~regflags))
193 return nasm_rd_zmmreg[regval];
194 if (!(OPMASKREG & ~regflags))
195 return nasm_rd_opmaskreg[regval];
196 if (!(BNDREG & ~regflags))
197 return nasm_rd_bndreg[regval];
198
199 return 0;
200 }
201
202 static uint32_t append_evex_reg_deco(char *buf, uint32_t num,
203 decoflags_t deco, uint8_t *evex)
204 {
205 const char * const er_names[] = {"rn-sae", "rd-sae", "ru-sae", "rz-sae"};
206 uint32_t num_chars = 0;
207
208 if ((deco & MASK) && (evex[2] & EVEX_P2AAA)) {
209 enum reg_enum opmasknum = nasm_rd_opmaskreg[evex[2] & EVEX_P2AAA];
210 const char * regname = nasm_reg_names[opmasknum - EXPR_REG_START];
211
212 num_chars += snprintf(buf + num_chars, num - num_chars,
213 "{%s}", regname);
214
215 if ((deco & Z) && (evex[2] & EVEX_P2Z)) {
216 num_chars += snprintf(buf + num_chars, num - num_chars,
217 "{z}");
218 }
219 }
220
221 if (evex[2] & EVEX_P2B) {
222 if (deco & ER) {
223 uint8_t er_type = (evex[2] & EVEX_P2LL) >> 5;
224 num_chars += snprintf(buf + num_chars, num - num_chars,
225 ",{%s}", er_names[er_type]);
226 } else if (deco & SAE) {
227 num_chars += snprintf(buf + num_chars, num - num_chars,
228 ",{sae}");
229 }
230 }
231
232 return num_chars;
233 }
234
235 static uint32_t append_evex_mem_deco(char *buf, uint32_t num, opflags_t type,
236 decoflags_t deco, uint8_t *evex)
237 {
238 uint32_t num_chars = 0;
239
240 if ((evex[2] & EVEX_P2B) && (deco & BRDCAST_MASK)) {
241 decoflags_t deco_brsize = deco & BRSIZE_MASK;
242 opflags_t template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
243 uint8_t br_num = (type & SIZE_MASK) / BITS128 *
244 BITS64 / template_opsize * 2;
245
246 num_chars += snprintf(buf + num_chars, num - num_chars,
247 "{1to%d}", br_num);
248 }
249
250 if ((deco & MASK) && (evex[2] & EVEX_P2AAA)) {
251 enum reg_enum opmasknum = nasm_rd_opmaskreg[evex[2] & EVEX_P2AAA];
252 const char * regname = nasm_reg_names[opmasknum - EXPR_REG_START];
253
254 num_chars += snprintf(buf + num_chars, num - num_chars,
255 "{%s}", regname);
256
257 if ((deco & Z) && (evex[2] & EVEX_P2Z)) {
258 num_chars += snprintf(buf + num_chars, num - num_chars,
259 "{z}");
260 }
261 }
262
263
264 return num_chars;
265 }
266
267 /*
268 * Process an effective address (ModRM) specification.
269 */
270 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
271 int segsize, enum ea_type type,
272 operand *op, insn *ins)
273 {
274 int mod, rm, scale, index, base;
275 int rex;
276 uint8_t *evex;
277 uint8_t sib = 0;
278 bool is_evex = !!(ins->rex & REX_EV);
279
280 mod = (modrm >> 6) & 03;
281 rm = modrm & 07;
282
283 if (mod != 3 && asize != 16 && rm == 4)
284 sib = *data++;
285
286 rex = ins->rex;
287 evex = ins->evex_p;
288
289 if (mod == 3) { /* pure register version */
290 op->basereg = rm+(rex & REX_B ? 8 : 0);
291 op->segment |= SEG_RMREG;
292 if (is_evex && segsize == 64) {
293 op->basereg += (evex[0] & EVEX_P0X ? 0 : 16);
294 }
295 return data;
296 }
297
298 op->disp_size = 0;
299 op->eaflags = 0;
300
301 if (asize == 16) {
302 /*
303 * <mod> specifies the displacement size (none, byte or
304 * word), and <rm> specifies the register combination.
305 * Exception: mod=0,rm=6 does not specify [BP] as one might
306 * expect, but instead specifies [disp16].
307 */
308
309 if (type != EA_SCALAR)
310 return NULL;
311
312 op->indexreg = op->basereg = -1;
313 op->scale = 1; /* always, in 16 bits */
314 switch (rm) {
315 case 0:
316 op->basereg = R_BX;
317 op->indexreg = R_SI;
318 break;
319 case 1:
320 op->basereg = R_BX;
321 op->indexreg = R_DI;
322 break;
323 case 2:
324 op->basereg = R_BP;
325 op->indexreg = R_SI;
326 break;
327 case 3:
328 op->basereg = R_BP;
329 op->indexreg = R_DI;
330 break;
331 case 4:
332 op->basereg = R_SI;
333 break;
334 case 5:
335 op->basereg = R_DI;
336 break;
337 case 6:
338 op->basereg = R_BP;
339 break;
340 case 7:
341 op->basereg = R_BX;
342 break;
343 }
344 if (rm == 6 && mod == 0) { /* special case */
345 op->basereg = -1;
346 if (segsize != 16)
347 op->disp_size = 16;
348 mod = 2; /* fake disp16 */
349 }
350 switch (mod) {
351 case 0:
352 op->segment |= SEG_NODISP;
353 break;
354 case 1:
355 op->segment |= SEG_DISP8;
356 if (ins->evex_tuple != 0) {
357 op->offset = gets8(data) * get_disp8N(ins);
358 } else {
359 op->offset = gets8(data);
360 }
361 data++;
362 break;
363 case 2:
364 op->segment |= SEG_DISP16;
365 op->offset = *data++;
366 op->offset |= ((unsigned)*data++) << 8;
367 break;
368 }
369 return data;
370 } else {
371 /*
372 * Once again, <mod> specifies displacement size (this time
373 * none, byte or *dword*), while <rm> specifies the base
374 * register. Again, [EBP] is missing, replaced by a pure
375 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
376 * and RIP-relative addressing in 64-bit mode.
377 *
378 * However, rm=4
379 * indicates not a single base register, but instead the
380 * presence of a SIB byte...
381 */
382 int a64 = asize == 64;
383
384 op->indexreg = -1;
385
386 if (a64)
387 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
388 else
389 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
390
391 if (rm == 5 && mod == 0) {
392 if (segsize == 64) {
393 op->eaflags |= EAF_REL;
394 op->segment |= SEG_RELATIVE;
395 mod = 2; /* fake disp32 */
396 }
397
398 if (asize != 64)
399 op->disp_size = asize;
400
401 op->basereg = -1;
402 mod = 2; /* fake disp32 */
403 }
404
405
406 if (rm == 4) { /* process SIB */
407 uint8_t vsib_hi = 0;
408 scale = (sib >> 6) & 03;
409 index = (sib >> 3) & 07;
410 base = sib & 07;
411
412 op->scale = 1 << scale;
413
414 if (segsize == 64) {
415 vsib_hi = (rex & REX_X ? 8 : 0) |
416 (evex[2] & EVEX_P2VP ? 0 : 16);
417 }
418
419 if (type == EA_XMMVSIB)
420 op->indexreg = nasm_rd_xmmreg[index | vsib_hi];
421 else if (type == EA_YMMVSIB)
422 op->indexreg = nasm_rd_ymmreg[index | vsib_hi];
423 else if (type == EA_ZMMVSIB)
424 op->indexreg = nasm_rd_zmmreg[index | vsib_hi];
425 else if (index == 4 && !(rex & REX_X))
426 op->indexreg = -1; /* ESP/RSP cannot be an index */
427 else if (a64)
428 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
429 else
430 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
431
432 if (base == 5 && mod == 0) {
433 op->basereg = -1;
434 mod = 2; /* Fake disp32 */
435 } else if (a64)
436 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
437 else
438 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
439
440 if (segsize == 16)
441 op->disp_size = 32;
442 } else if (type != EA_SCALAR) {
443 /* Can't have VSIB without SIB */
444 return NULL;
445 }
446
447 switch (mod) {
448 case 0:
449 op->segment |= SEG_NODISP;
450 break;
451 case 1:
452 op->segment |= SEG_DISP8;
453 if (ins->evex_tuple != 0) {
454 op->offset = gets8(data) * get_disp8N(ins);
455 } else {
456 op->offset = gets8(data);
457 }
458 data++;
459 break;
460 case 2:
461 op->segment |= SEG_DISP32;
462 op->offset = gets32(data);
463 data += 4;
464 break;
465 }
466 return data;
467 }
468 }
469
470 /*
471 * Determine whether the instruction template in t corresponds to the data
472 * stream in data. Return the number of bytes matched if so.
473 */
474 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
475
476 static int matches(const struct itemplate *t, uint8_t *data,
477 const struct prefix_info *prefix, int segsize, insn *ins)
478 {
479 uint8_t *r = (uint8_t *)(t->code);
480 uint8_t *origdata = data;
481 bool a_used = false, o_used = false;
482 enum prefixes drep = 0;
483 enum prefixes dwait = 0;
484 uint8_t lock = prefix->lock;
485 int osize = prefix->osize;
486 int asize = prefix->asize;
487 int i, c;
488 int op1, op2;
489 struct operand *opx, *opy;
490 uint8_t opex = 0;
491 bool vex_ok = false;
492 int regmask = (segsize == 64) ? 15 : 7;
493 enum ea_type eat = EA_SCALAR;
494
495 for (i = 0; i < MAX_OPERANDS; i++) {
496 ins->oprs[i].segment = ins->oprs[i].disp_size =
497 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
498 }
499 ins->condition = -1;
500 ins->evex_tuple = 0;
501 ins->rex = prefix->rex;
502 memset(ins->prefixes, 0, sizeof ins->prefixes);
503
504 if (itemp_has(t, (segsize == 64 ? IF_NOLONG : IF_LONG)))
505 return false;
506
507 if (prefix->rep == 0xF2)
508 drep = (itemp_has(t, IF_BND) ? P_BND : P_REPNE);
509 else if (prefix->rep == 0xF3)
510 drep = P_REP;
511
512 dwait = prefix->wait ? P_WAIT : 0;
513
514 while ((c = *r++) != 0) {
515 op1 = (c & 3) + ((opex & 1) << 2);
516 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
517 opx = &ins->oprs[op1];
518 opy = &ins->oprs[op2];
519 opex = 0;
520
521 switch (c) {
522 case 01:
523 case 02:
524 case 03:
525 case 04:
526 while (c--)
527 if (*r++ != *data++)
528 return false;
529 break;
530
531 case 05:
532 case 06:
533 case 07:
534 opex = c;
535 break;
536
537 case4(010):
538 {
539 int t = *r++, d = *data++;
540 if (d < t || d > t + 7)
541 return false;
542 else {
543 opx->basereg = (d-t)+
544 (ins->rex & REX_B ? 8 : 0);
545 opx->segment |= SEG_RMREG;
546 }
547 break;
548 }
549
550 case4(014):
551 /* this is an separate index reg position of MIB operand (ICC) */
552 /* Disassembler uses NASM's split EA form only */
553 break;
554
555 case4(0274):
556 opx->offset = (int8_t)*data++;
557 opx->segment |= SEG_SIGNED;
558 break;
559
560 case4(020):
561 opx->offset = *data++;
562 break;
563
564 case4(024):
565 opx->offset = *data++;
566 break;
567
568 case4(030):
569 opx->offset = getu16(data);
570 data += 2;
571 break;
572
573 case4(034):
574 if (osize == 32) {
575 opx->offset = getu32(data);
576 data += 4;
577 } else {
578 opx->offset = getu16(data);
579 data += 2;
580 }
581 if (segsize != asize)
582 opx->disp_size = asize;
583 break;
584
585 case4(040):
586 opx->offset = getu32(data);
587 data += 4;
588 break;
589
590 case4(0254):
591 opx->offset = gets32(data);
592 data += 4;
593 break;
594
595 case4(044):
596 switch (asize) {
597 case 16:
598 opx->offset = getu16(data);
599 data += 2;
600 if (segsize != 16)
601 opx->disp_size = 16;
602 break;
603 case 32:
604 opx->offset = getu32(data);
605 data += 4;
606 if (segsize == 16)
607 opx->disp_size = 32;
608 break;
609 case 64:
610 opx->offset = getu64(data);
611 opx->disp_size = 64;
612 data += 8;
613 break;
614 }
615 break;
616
617 case4(050):
618 opx->offset = gets8(data++);
619 opx->segment |= SEG_RELATIVE;
620 break;
621
622 case4(054):
623 opx->offset = getu64(data);
624 data += 8;
625 break;
626
627 case4(060):
628 opx->offset = gets16(data);
629 data += 2;
630 opx->segment |= SEG_RELATIVE;
631 opx->segment &= ~SEG_32BIT;
632 break;
633
634 case4(064): /* rel */
635 opx->segment |= SEG_RELATIVE;
636 /* In long mode rel is always 32 bits, sign extended. */
637 if (segsize == 64 || osize == 32) {
638 opx->offset = gets32(data);
639 data += 4;
640 if (segsize != 64)
641 opx->segment |= SEG_32BIT;
642 opx->type = (opx->type & ~SIZE_MASK)
643 | (segsize == 64 ? BITS64 : BITS32);
644 } else {
645 opx->offset = gets16(data);
646 data += 2;
647 opx->segment &= ~SEG_32BIT;
648 opx->type = (opx->type & ~SIZE_MASK) | BITS16;
649 }
650 break;
651
652 case4(070):
653 opx->offset = gets32(data);
654 data += 4;
655 opx->segment |= SEG_32BIT | SEG_RELATIVE;
656 break;
657
658 case4(0100):
659 case4(0110):
660 case4(0120):
661 case4(0130):
662 {
663 int modrm = *data++;
664 opx->segment |= SEG_RMREG;
665 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
666 if (!data)
667 return false;
668 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
669 if ((ins->rex & REX_EV) && (segsize == 64))
670 opx->basereg += (ins->evex_p[0] & EVEX_P0RP ? 0 : 16);
671 break;
672 }
673
674 case 0172:
675 {
676 uint8_t ximm = *data++;
677 c = *r++;
678 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
679 ins->oprs[c >> 3].segment |= SEG_RMREG;
680 ins->oprs[c & 7].offset = ximm & 15;
681 }
682 break;
683
684 case 0173:
685 {
686 uint8_t ximm = *data++;
687 c = *r++;
688
689 if ((c ^ ximm) & 15)
690 return false;
691
692 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
693 ins->oprs[c >> 4].segment |= SEG_RMREG;
694 }
695 break;
696
697 case4(0174):
698 {
699 uint8_t ximm = *data++;
700
701 opx->basereg = (ximm >> 4) & regmask;
702 opx->segment |= SEG_RMREG;
703 }
704 break;
705
706 case4(0200):
707 case4(0204):
708 case4(0210):
709 case4(0214):
710 case4(0220):
711 case4(0224):
712 case4(0230):
713 case4(0234):
714 {
715 int modrm = *data++;
716 if (((modrm >> 3) & 07) != (c & 07))
717 return false; /* spare field doesn't match up */
718 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
719 if (!data)
720 return false;
721 break;
722 }
723
724 case4(0240):
725 case 0250:
726 {
727 uint8_t evexm = *r++;
728 uint8_t evexwlp = *r++;
729 uint8_t modrm, valid_mask;
730 ins->evex_tuple = *r++ - 0300;
731 modrm = *(origdata + 1);
732
733 ins->rex |= REX_EV;
734 if ((prefix->rex & (REX_EV|REX_V|REX_P)) != REX_EV)
735 return false;
736
737 if ((evexm & 0x1f) != prefix->vex_m)
738 return false;
739
740 switch (evexwlp & 060) {
741 case 000:
742 if (prefix->rex & REX_W)
743 return false;
744 break;
745 case 020:
746 if (!(prefix->rex & REX_W))
747 return false;
748 ins->rex |= REX_W;
749 break;
750 case 040: /* VEX.W is a don't care */
751 ins->rex &= ~REX_W;
752 break;
753 case 060:
754 break;
755 }
756
757 /* If EVEX.b is set with reg-reg op,
758 * EVEX.L'L contains embedded rounding control info
759 */
760 if ((prefix->evex[2] & EVEX_P2B) && ((modrm >> 6) == 3)) {
761 valid_mask = 0x3; /* prefix only */
762 } else {
763 valid_mask = 0xf; /* vector length and prefix */
764 }
765 if ((evexwlp ^ prefix->vex_lp) & valid_mask)
766 return false;
767
768 if (c == 0250) {
769 if ((prefix->vex_v != 0) ||
770 (!(prefix->evex[2] & EVEX_P2VP) &&
771 ((eat < EA_XMMVSIB) || (eat > EA_ZMMVSIB))))
772 return false;
773 } else {
774 opx->segment |= SEG_RMREG;
775 opx->basereg = ((~prefix->evex[2] & EVEX_P2VP) << (4 - 3) ) |
776 prefix->vex_v;
777 }
778 vex_ok = true;
779 memcpy(ins->evex_p, prefix->evex, 3);
780 break;
781 }
782
783 case4(0260):
784 case 0270:
785 {
786 int vexm = *r++;
787 int vexwlp = *r++;
788
789 ins->rex |= REX_V;
790 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
791 return false;
792
793 if ((vexm & 0x1f) != prefix->vex_m)
794 return false;
795
796 switch (vexwlp & 060) {
797 case 000:
798 if (prefix->rex & REX_W)
799 return false;
800 break;
801 case 020:
802 if (!(prefix->rex & REX_W))
803 return false;
804 ins->rex &= ~REX_W;
805 break;
806 case 040: /* VEX.W is a don't care */
807 ins->rex &= ~REX_W;
808 break;
809 case 060:
810 break;
811 }
812
813 /* The 010 bit of vexwlp is set if VEX.L is ignored */
814 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
815 return false;
816
817 if (c == 0270) {
818 if (prefix->vex_v != 0)
819 return false;
820 } else {
821 opx->segment |= SEG_RMREG;
822 opx->basereg = prefix->vex_v;
823 }
824 vex_ok = true;
825 break;
826 }
827
828 case 0271:
829 if (prefix->rep == 0xF3)
830 drep = P_XRELEASE;
831 break;
832
833 case 0272:
834 if (prefix->rep == 0xF2)
835 drep = P_XACQUIRE;
836 else if (prefix->rep == 0xF3)
837 drep = P_XRELEASE;
838 break;
839
840 case 0273:
841 if (prefix->lock == 0xF0) {
842 if (prefix->rep == 0xF2)
843 drep = P_XACQUIRE;
844 else if (prefix->rep == 0xF3)
845 drep = P_XRELEASE;
846 }
847 break;
848
849 case 0310:
850 if (asize != 16)
851 return false;
852 else
853 a_used = true;
854 break;
855
856 case 0311:
857 if (asize != 32)
858 return false;
859 else
860 a_used = true;
861 break;
862
863 case 0312:
864 if (asize != segsize)
865 return false;
866 else
867 a_used = true;
868 break;
869
870 case 0313:
871 if (asize != 64)
872 return false;
873 else
874 a_used = true;
875 break;
876
877 case 0314:
878 if (prefix->rex & REX_B)
879 return false;
880 break;
881
882 case 0315:
883 if (prefix->rex & REX_X)
884 return false;
885 break;
886
887 case 0316:
888 if (prefix->rex & REX_R)
889 return false;
890 break;
891
892 case 0317:
893 if (prefix->rex & REX_W)
894 return false;
895 break;
896
897 case 0320:
898 if (osize != 16)
899 return false;
900 else
901 o_used = true;
902 break;
903
904 case 0321:
905 if (osize != 32)
906 return false;
907 else
908 o_used = true;
909 break;
910
911 case 0322:
912 if (osize != (segsize == 16) ? 16 : 32)
913 return false;
914 else
915 o_used = true;
916 break;
917
918 case 0323:
919 ins->rex |= REX_W; /* 64-bit only instruction */
920 osize = 64;
921 o_used = true;
922 break;
923
924 case 0324:
925 if (osize != 64)
926 return false;
927 o_used = true;
928 break;
929
930 case 0325:
931 ins->rex |= REX_NH;
932 break;
933
934 case 0330:
935 {
936 int t = *r++, d = *data++;
937 if (d < t || d > t + 15)
938 return false;
939 else
940 ins->condition = d - t;
941 break;
942 }
943
944 case 0326:
945 if (prefix->rep == 0xF3)
946 return false;
947 break;
948
949 case 0331:
950 if (prefix->rep)
951 return false;
952 break;
953
954 case 0332:
955 if (prefix->rep != 0xF2)
956 return false;
957 drep = 0;
958 break;
959
960 case 0333:
961 if (prefix->rep != 0xF3)
962 return false;
963 drep = 0;
964 break;
965
966 case 0334:
967 if (lock) {
968 ins->rex |= REX_R;
969 lock = 0;
970 }
971 break;
972
973 case 0335:
974 if (drep == P_REP)
975 drep = P_REPE;
976 break;
977
978 case 0336:
979 case 0337:
980 break;
981
982 case 0340:
983 return false;
984
985 case 0341:
986 if (prefix->wait != 0x9B)
987 return false;
988 dwait = 0;
989 break;
990
991 case 0360:
992 if (prefix->osp || prefix->rep)
993 return false;
994 break;
995
996 case 0361:
997 if (!prefix->osp || prefix->rep)
998 return false;
999 o_used = true;
1000 break;
1001
1002 case 0364:
1003 if (prefix->osp)
1004 return false;
1005 break;
1006
1007 case 0365:
1008 if (prefix->asp)
1009 return false;
1010 break;
1011
1012 case 0366:
1013 if (!prefix->osp)
1014 return false;
1015 o_used = true;
1016 break;
1017
1018 case 0367:
1019 if (!prefix->asp)
1020 return false;
1021 a_used = true;
1022 break;
1023
1024 case 0370:
1025 case 0371:
1026 break;
1027
1028 case 0374:
1029 eat = EA_XMMVSIB;
1030 break;
1031
1032 case 0375:
1033 eat = EA_YMMVSIB;
1034 break;
1035
1036 case 0376:
1037 eat = EA_ZMMVSIB;
1038 break;
1039
1040 default:
1041 return false; /* Unknown code */
1042 }
1043 }
1044
1045 if (!vex_ok && (ins->rex & (REX_V | REX_EV)))
1046 return false;
1047
1048 /* REX cannot be combined with VEX */
1049 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
1050 return false;
1051
1052 /*
1053 * Check for unused rep or a/o prefixes.
1054 */
1055 for (i = 0; i < t->operands; i++) {
1056 if (ins->oprs[i].segment != SEG_RMREG)
1057 a_used = true;
1058 }
1059
1060 if (lock) {
1061 if (ins->prefixes[PPS_LOCK])
1062 return false;
1063 ins->prefixes[PPS_LOCK] = P_LOCK;
1064 }
1065 if (drep) {
1066 if (ins->prefixes[PPS_REP])
1067 return false;
1068 ins->prefixes[PPS_REP] = drep;
1069 }
1070 ins->prefixes[PPS_WAIT] = dwait;
1071 if (!o_used) {
1072 if (osize != ((segsize == 16) ? 16 : 32)) {
1073 enum prefixes pfx = 0;
1074
1075 switch (osize) {
1076 case 16:
1077 pfx = P_O16;
1078 break;
1079 case 32:
1080 pfx = P_O32;
1081 break;
1082 case 64:
1083 pfx = P_O64;
1084 break;
1085 }
1086
1087 if (ins->prefixes[PPS_OSIZE])
1088 return false;
1089 ins->prefixes[PPS_OSIZE] = pfx;
1090 }
1091 }
1092 if (!a_used && asize != segsize) {
1093 if (ins->prefixes[PPS_ASIZE])
1094 return false;
1095 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
1096 }
1097
1098 /* Fix: check for redundant REX prefixes */
1099
1100 return data - origdata;
1101 }
1102
1103 /* Condition names for disassembly, sorted by x86 code */
1104 static const char * const condition_name[16] = {
1105 "o", "no", "c", "nc", "z", "nz", "na", "a",
1106 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
1107 };
1108
1109 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
1110 int32_t offset, int autosync, iflag_t *prefer)
1111 {
1112 const struct itemplate * const *p, * const *best_p;
1113 const struct disasm_index *ix;
1114 uint8_t *dp;
1115 int length, best_length = 0;
1116 char *segover;
1117 int i, slen, colon, n;
1118 uint8_t *origdata;
1119 int works;
1120 insn tmp_ins, ins;
1121 iflag_t goodness, best;
1122 int best_pref;
1123 struct prefix_info prefix;
1124 bool end_prefix;
1125 bool is_evex;
1126
1127 memset(&ins, 0, sizeof ins);
1128
1129 /*
1130 * Scan for prefixes.
1131 */
1132 memset(&prefix, 0, sizeof prefix);
1133 prefix.asize = segsize;
1134 prefix.osize = (segsize == 64) ? 32 : segsize;
1135 segover = NULL;
1136 origdata = data;
1137
1138 ix = itable;
1139
1140 end_prefix = false;
1141 while (!end_prefix) {
1142 switch (*data) {
1143 case 0xF2:
1144 case 0xF3:
1145 prefix.rep = *data++;
1146 break;
1147
1148 case 0x9B:
1149 prefix.wait = *data++;
1150 break;
1151
1152 case 0xF0:
1153 prefix.lock = *data++;
1154 break;
1155
1156 case 0x2E:
1157 segover = "cs", prefix.seg = *data++;
1158 break;
1159 case 0x36:
1160 segover = "ss", prefix.seg = *data++;
1161 break;
1162 case 0x3E:
1163 segover = "ds", prefix.seg = *data++;
1164 break;
1165 case 0x26:
1166 segover = "es", prefix.seg = *data++;
1167 break;
1168 case 0x64:
1169 segover = "fs", prefix.seg = *data++;
1170 break;
1171 case 0x65:
1172 segover = "gs", prefix.seg = *data++;
1173 break;
1174
1175 case 0x66:
1176 prefix.osize = (segsize == 16) ? 32 : 16;
1177 prefix.osp = *data++;
1178 break;
1179 case 0x67:
1180 prefix.asize = (segsize == 32) ? 16 : 32;
1181 prefix.asp = *data++;
1182 break;
1183
1184 case 0xC4:
1185 case 0xC5:
1186 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1187 prefix.vex[0] = *data++;
1188 prefix.vex[1] = *data++;
1189
1190 prefix.rex = REX_V;
1191 prefix.vex_c = RV_VEX;
1192
1193 if (prefix.vex[0] == 0xc4) {
1194 prefix.vex[2] = *data++;
1195 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1196 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1197 prefix.vex_m = prefix.vex[1] & 0x1f;
1198 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1199 prefix.vex_lp = prefix.vex[2] & 7;
1200 } else {
1201 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1202 prefix.vex_m = 1;
1203 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1204 prefix.vex_lp = prefix.vex[1] & 7;
1205 }
1206
1207 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1208 }
1209 end_prefix = true;
1210 break;
1211
1212 case 0x62:
1213 {
1214 uint8_t evex_p0 = data[1] & 0x0f;
1215 if (segsize == 64 ||
1216 ((evex_p0 >= 0x01) && (evex_p0 <= 0x03))) {
1217 data++; /* 62h EVEX prefix */
1218 prefix.evex[0] = *data++;
1219 prefix.evex[1] = *data++;
1220 prefix.evex[2] = *data++;
1221
1222 prefix.rex = REX_EV;
1223 prefix.vex_c = RV_EVEX;
1224 prefix.rex |= (~prefix.evex[0] >> 5) & 7; /* REX_RXB */
1225 prefix.rex |= (prefix.evex[1] >> (7-3)) & REX_W;
1226 prefix.vex_m = prefix.evex[0] & EVEX_P0MM;
1227 prefix.vex_v = (~prefix.evex[1] & EVEX_P1VVVV) >> 3;
1228 prefix.vex_lp = ((prefix.evex[2] & EVEX_P2LL) >> (5-2)) |
1229 (prefix.evex[1] & EVEX_P1PP);
1230
1231 ix = itable_vex[prefix.vex_c][prefix.vex_m][prefix.vex_lp & 3];
1232 }
1233 end_prefix = true;
1234 break;
1235 }
1236
1237 case 0x8F:
1238 if ((data[1] & 030) != 0 &&
1239 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1240 prefix.vex[0] = *data++;
1241 prefix.vex[1] = *data++;
1242 prefix.vex[2] = *data++;
1243
1244 prefix.rex = REX_V;
1245 prefix.vex_c = RV_XOP;
1246
1247 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1248 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1249 prefix.vex_m = prefix.vex[1] & 0x1f;
1250 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1251 prefix.vex_lp = prefix.vex[2] & 7;
1252
1253 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1254 }
1255 end_prefix = true;
1256 break;
1257
1258 case REX_P + 0x0:
1259 case REX_P + 0x1:
1260 case REX_P + 0x2:
1261 case REX_P + 0x3:
1262 case REX_P + 0x4:
1263 case REX_P + 0x5:
1264 case REX_P + 0x6:
1265 case REX_P + 0x7:
1266 case REX_P + 0x8:
1267 case REX_P + 0x9:
1268 case REX_P + 0xA:
1269 case REX_P + 0xB:
1270 case REX_P + 0xC:
1271 case REX_P + 0xD:
1272 case REX_P + 0xE:
1273 case REX_P + 0xF:
1274 if (segsize == 64) {
1275 prefix.rex = *data++;
1276 if (prefix.rex & REX_W)
1277 prefix.osize = 64;
1278 }
1279 end_prefix = true;
1280 break;
1281
1282 default:
1283 end_prefix = true;
1284 break;
1285 }
1286 }
1287
1288 iflag_set_all(&best); /* Worst possible */
1289 best_p = NULL;
1290 best_pref = INT_MAX;
1291
1292 if (!ix)
1293 return 0; /* No instruction table at all... */
1294
1295 dp = data;
1296 ix += *dp++;
1297 while (ix->n == -1) {
1298 ix = (const struct disasm_index *)ix->p + *dp++;
1299 }
1300
1301 p = (const struct itemplate * const *)ix->p;
1302 for (n = ix->n; n; n--, p++) {
1303 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1304 works = true;
1305 /*
1306 * Final check to make sure the types of r/m match up.
1307 * XXX: Need to make sure this is actually correct.
1308 */
1309 for (i = 0; i < (*p)->operands; i++) {
1310 if (
1311 /* If it's a mem-only EA but we have a
1312 register, die. */
1313 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1314 is_class(MEMORY, (*p)->opd[i])) ||
1315 /* If it's a reg-only EA but we have a memory
1316 ref, die. */
1317 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1318 !(REG_EA & ~(*p)->opd[i]) &&
1319 !((*p)->opd[i] & REG_SMASK)) ||
1320 /* Register type mismatch (eg FS vs REG_DESS):
1321 die. */
1322 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1323 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1324 !whichreg((*p)->opd[i],
1325 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1326 ) {
1327 works = false;
1328 break;
1329 }
1330 }
1331
1332 /*
1333 * Note: we always prefer instructions which incorporate
1334 * prefixes in the instructions themselves. This is to allow
1335 * e.g. PAUSE to be preferred to REP NOP, and deal with
1336 * MMX/SSE instructions where prefixes are used to select
1337 * between MMX and SSE register sets or outright opcode
1338 * selection.
1339 */
1340 if (works) {
1341 int i, nprefix;
1342 goodness = iflag_pfmask(*p);
1343 goodness = iflag_xor(&goodness, prefer);
1344 nprefix = 0;
1345 for (i = 0; i < MAXPREFIX; i++)
1346 if (tmp_ins.prefixes[i])
1347 nprefix++;
1348 if (nprefix < best_pref ||
1349 (nprefix == best_pref &&
1350 iflag_cmp(&goodness, &best) < 0)) {
1351 /* This is the best one found so far */
1352 best = goodness;
1353 best_p = p;
1354 best_pref = nprefix;
1355 best_length = length;
1356 ins = tmp_ins;
1357 }
1358 }
1359 }
1360 }
1361
1362 if (!best_p)
1363 return 0; /* no instruction was matched */
1364
1365 /* Pick the best match */
1366 p = best_p;
1367 length = best_length;
1368
1369 slen = 0;
1370
1371 /* TODO: snprintf returns the value that the string would have if
1372 * the buffer were long enough, and not the actual length of
1373 * the returned string, so each instance of using the return
1374 * value of snprintf should actually be checked to assure that
1375 * the return value is "sane." Maybe a macro wrapper could
1376 * be used for that purpose.
1377 */
1378 for (i = 0; i < MAXPREFIX; i++) {
1379 const char *prefix = prefix_name(ins.prefixes[i]);
1380 if (prefix)
1381 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1382 }
1383
1384 i = (*p)->opcode;
1385 if (i >= FIRST_COND_OPCODE)
1386 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1387 nasm_insn_names[i], condition_name[ins.condition]);
1388 else
1389 slen += snprintf(output + slen, outbufsize - slen, "%s",
1390 nasm_insn_names[i]);
1391
1392 colon = false;
1393 is_evex = !!(ins.rex & REX_EV);
1394 length += data - origdata; /* fix up for prefixes */
1395 for (i = 0; i < (*p)->operands; i++) {
1396 opflags_t t = (*p)->opd[i];
1397 decoflags_t deco = (*p)->deco[i];
1398 const operand *o = &ins.oprs[i];
1399 int64_t offs;
1400
1401 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1402
1403 offs = o->offset;
1404 if (o->segment & SEG_RELATIVE) {
1405 offs += offset + length;
1406 /*
1407 * sort out wraparound
1408 */
1409 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1410 offs &= 0xffff;
1411 else if (segsize != 64)
1412 offs &= 0xffffffff;
1413
1414 /*
1415 * add sync marker, if autosync is on
1416 */
1417 if (autosync)
1418 add_sync(offs, 0L);
1419 }
1420
1421 if (t & COLON)
1422 colon = true;
1423 else
1424 colon = false;
1425
1426 if ((t & (REGISTER | FPUREG)) ||
1427 (o->segment & SEG_RMREG)) {
1428 enum reg_enum reg;
1429 reg = whichreg(t, o->basereg, ins.rex);
1430 if (t & TO)
1431 slen += snprintf(output + slen, outbufsize - slen, "to ");
1432 slen += snprintf(output + slen, outbufsize - slen, "%s",
1433 nasm_reg_names[reg-EXPR_REG_START]);
1434 if (is_evex && deco)
1435 slen += append_evex_reg_deco(output + slen, outbufsize - slen,
1436 deco, ins.evex_p);
1437 } else if (!(UNITY & ~t)) {
1438 output[slen++] = '1';
1439 } else if (t & IMMEDIATE) {
1440 if (t & BITS8) {
1441 slen +=
1442 snprintf(output + slen, outbufsize - slen, "byte ");
1443 if (o->segment & SEG_SIGNED) {
1444 if (offs < 0) {
1445 offs *= -1;
1446 output[slen++] = '-';
1447 } else
1448 output[slen++] = '+';
1449 }
1450 } else if (t & BITS16) {
1451 slen +=
1452 snprintf(output + slen, outbufsize - slen, "word ");
1453 } else if (t & BITS32) {
1454 slen +=
1455 snprintf(output + slen, outbufsize - slen, "dword ");
1456 } else if (t & BITS64) {
1457 slen +=
1458 snprintf(output + slen, outbufsize - slen, "qword ");
1459 } else if (t & NEAR) {
1460 slen +=
1461 snprintf(output + slen, outbufsize - slen, "near ");
1462 } else if (t & SHORT) {
1463 slen +=
1464 snprintf(output + slen, outbufsize - slen, "short ");
1465 }
1466 slen +=
1467 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1468 offs);
1469 } else if (!(MEM_OFFS & ~t)) {
1470 slen +=
1471 snprintf(output + slen, outbufsize - slen,
1472 "[%s%s%s0x%"PRIx64"]",
1473 (segover ? segover : ""),
1474 (segover ? ":" : ""),
1475 (o->disp_size == 64 ? "qword " :
1476 o->disp_size == 32 ? "dword " :
1477 o->disp_size == 16 ? "word " : ""), offs);
1478 segover = NULL;
1479 } else if (is_class(REGMEM, t)) {
1480 int started = false;
1481 if (t & BITS8)
1482 slen +=
1483 snprintf(output + slen, outbufsize - slen, "byte ");
1484 if (t & BITS16)
1485 slen +=
1486 snprintf(output + slen, outbufsize - slen, "word ");
1487 if (t & BITS32)
1488 slen +=
1489 snprintf(output + slen, outbufsize - slen, "dword ");
1490 if (t & BITS64)
1491 slen +=
1492 snprintf(output + slen, outbufsize - slen, "qword ");
1493 if (t & BITS80)
1494 slen +=
1495 snprintf(output + slen, outbufsize - slen, "tword ");
1496 if ((ins.evex_p[2] & EVEX_P2B) && (deco & BRDCAST_MASK)) {
1497 /* when broadcasting, each element size should be used */
1498 if (deco & BR_BITS32)
1499 slen +=
1500 snprintf(output + slen, outbufsize - slen, "dword ");
1501 else if (deco & BR_BITS64)
1502 slen +=
1503 snprintf(output + slen, outbufsize - slen, "qword ");
1504 } else {
1505 if (t & BITS128)
1506 slen +=
1507 snprintf(output + slen, outbufsize - slen, "oword ");
1508 if (t & BITS256)
1509 slen +=
1510 snprintf(output + slen, outbufsize - slen, "yword ");
1511 if (t & BITS512)
1512 slen +=
1513 snprintf(output + slen, outbufsize - slen, "zword ");
1514 }
1515 if (t & FAR)
1516 slen += snprintf(output + slen, outbufsize - slen, "far ");
1517 if (t & NEAR)
1518 slen +=
1519 snprintf(output + slen, outbufsize - slen, "near ");
1520 output[slen++] = '[';
1521 if (o->disp_size)
1522 slen += snprintf(output + slen, outbufsize - slen, "%s",
1523 (o->disp_size == 64 ? "qword " :
1524 o->disp_size == 32 ? "dword " :
1525 o->disp_size == 16 ? "word " :
1526 ""));
1527 if (o->eaflags & EAF_REL)
1528 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1529 if (segover) {
1530 slen +=
1531 snprintf(output + slen, outbufsize - slen, "%s:",
1532 segover);
1533 segover = NULL;
1534 }
1535 if (o->basereg != -1) {
1536 slen += snprintf(output + slen, outbufsize - slen, "%s",
1537 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1538 started = true;
1539 }
1540 if (o->indexreg != -1 && !itemp_has(*best_p, IF_MIB)) {
1541 if (started)
1542 output[slen++] = '+';
1543 slen += snprintf(output + slen, outbufsize - slen, "%s",
1544 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1545 if (o->scale > 1)
1546 slen +=
1547 snprintf(output + slen, outbufsize - slen, "*%d",
1548 o->scale);
1549 started = true;
1550 }
1551
1552
1553 if (o->segment & SEG_DISP8) {
1554 if (is_evex) {
1555 const char *prefix;
1556 uint32_t offset = offs;
1557 if ((int32_t)offset < 0) {
1558 prefix = "-";
1559 offset = -offset;
1560 } else {
1561 prefix = "+";
1562 }
1563 slen +=
1564 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx32"",
1565 prefix, offset);
1566 } else {
1567 const char *prefix;
1568 uint8_t offset = offs;
1569 if ((int8_t)offset < 0) {
1570 prefix = "-";
1571 offset = -offset;
1572 } else {
1573 prefix = "+";
1574 }
1575 slen +=
1576 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1577 prefix, offset);
1578 }
1579 } else if (o->segment & SEG_DISP16) {
1580 const char *prefix;
1581 uint16_t offset = offs;
1582 if ((int16_t)offset < 0 && started) {
1583 offset = -offset;
1584 prefix = "-";
1585 } else {
1586 prefix = started ? "+" : "";
1587 }
1588 slen +=
1589 snprintf(output + slen, outbufsize - slen,
1590 "%s0x%"PRIx16"", prefix, offset);
1591 } else if (o->segment & SEG_DISP32) {
1592 if (prefix.asize == 64) {
1593 const char *prefix;
1594 uint64_t offset = (int64_t)(int32_t)offs;
1595 if ((int32_t)offs < 0 && started) {
1596 offset = -offset;
1597 prefix = "-";
1598 } else {
1599 prefix = started ? "+" : "";
1600 }
1601 slen +=
1602 snprintf(output + slen, outbufsize - slen,
1603 "%s0x%"PRIx64"", prefix, offset);
1604 } else {
1605 const char *prefix;
1606 uint32_t offset = offs;
1607 if ((int32_t) offset < 0 && started) {
1608 offset = -offset;
1609 prefix = "-";
1610 } else {
1611 prefix = started ? "+" : "";
1612 }
1613 slen +=
1614 snprintf(output + slen, outbufsize - slen,
1615 "%s0x%"PRIx32"", prefix, offset);
1616 }
1617 }
1618
1619 if (o->indexreg != -1 && itemp_has(*best_p, IF_MIB)) {
1620 output[slen++] = ',';
1621 slen += snprintf(output + slen, outbufsize - slen, "%s",
1622 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1623 if (o->scale > 1)
1624 slen +=
1625 snprintf(output + slen, outbufsize - slen, "*%d",
1626 o->scale);
1627 started = true;
1628 }
1629
1630 output[slen++] = ']';
1631
1632 if (is_evex && deco)
1633 slen += append_evex_mem_deco(output + slen, outbufsize - slen,
1634 t, deco, ins.evex_p);
1635 } else {
1636 slen +=
1637 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1638 i);
1639 }
1640 }
1641 output[slen] = '\0';
1642 if (segover) { /* unused segment override */
1643 char *p = output;
1644 int count = slen + 1;
1645 while (count--)
1646 p[count + 3] = p[count];
1647 strncpy(output, segover, 2);
1648 output[2] = ' ';
1649 }
1650 return length;
1651 }
1652
1653 /*
1654 * This is called when we don't have a complete instruction. If it
1655 * is a standalone *single-byte* prefix show it as such, otherwise
1656 * print it as a literal.
1657 */
1658 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1659 {
1660 uint8_t byte = *data;
1661 const char *str = NULL;
1662
1663 switch (byte) {
1664 case 0xF2:
1665 str = "repne";
1666 break;
1667 case 0xF3:
1668 str = "rep";
1669 break;
1670 case 0x9B:
1671 str = "wait";
1672 break;
1673 case 0xF0:
1674 str = "lock";
1675 break;
1676 case 0x2E:
1677 str = "cs";
1678 break;
1679 case 0x36:
1680 str = "ss";
1681 break;
1682 case 0x3E:
1683 str = "ss";
1684 break;
1685 case 0x26:
1686 str = "es";
1687 break;
1688 case 0x64:
1689 str = "fs";
1690 break;
1691 case 0x65:
1692 str = "gs";
1693 break;
1694 case 0x66:
1695 str = (segsize == 16) ? "o32" : "o16";
1696 break;
1697 case 0x67:
1698 str = (segsize == 32) ? "a16" : "a32";
1699 break;
1700 case REX_P + 0x0:
1701 case REX_P + 0x1:
1702 case REX_P + 0x2:
1703 case REX_P + 0x3:
1704 case REX_P + 0x4:
1705 case REX_P + 0x5:
1706 case REX_P + 0x6:
1707 case REX_P + 0x7:
1708 case REX_P + 0x8:
1709 case REX_P + 0x9:
1710 case REX_P + 0xA:
1711 case REX_P + 0xB:
1712 case REX_P + 0xC:
1713 case REX_P + 0xD:
1714 case REX_P + 0xE:
1715 case REX_P + 0xF:
1716 if (segsize == 64) {
1717 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1718 (byte == REX_P) ? "" : ".",
1719 (byte & REX_W) ? "w" : "",
1720 (byte & REX_R) ? "r" : "",
1721 (byte & REX_X) ? "x" : "",
1722 (byte & REX_B) ? "b" : "");
1723 break;
1724 }
1725 /* else fall through */
1726 default:
1727 snprintf(output, outbufsize, "db 0x%02x", byte);
1728 break;
1729 }
1730
1731 if (str)
1732 snprintf(output, outbufsize, "%s", str);
1733
1734 return 1;
1735 }
The Netwide Assembler