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Remove unnecessary calls to memset
[nasm.git] / disasm.c
blob97bf27e528a41eba60d1da5fb9f364bbf0daad65
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43 #include <inttypes.h>
44
45 #include "nasm.h"
46 #include "disasm.h"
47 #include "sync.h"
48 #include "insns.h"
49 #include "tables.h"
50 #include "regdis.h"
51
52 /*
53 * Flags that go into the `segment' field of `insn' structures
54 * during disassembly.
55 */
56 #define SEG_RELATIVE 1
57 #define SEG_32BIT 2
58 #define SEG_RMREG 4
59 #define SEG_DISP8 8
60 #define SEG_DISP16 16
61 #define SEG_DISP32 32
62 #define SEG_NODISP 64
63 #define SEG_SIGNED 128
64 #define SEG_64BIT 256
65
66 /*
67 * Prefix information
68 */
69 struct prefix_info {
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
81 uint8_t vex_v;
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
84 };
85
86 #define getu8(x) (*(uint8_t *)(x))
87 #if X86_MEMORY
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
92 #else
93 static uint16_t getu16(uint8_t *data)
94 {
95 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
96 }
97 static uint32_t getu32(uint8_t *data)
98 {
99 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
100 }
101 static uint64_t getu64(uint8_t *data)
102 {
103 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
104 }
105 #endif
106
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
111
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
114 {
115 size_t i;
116
117 static const struct {
118 opflags_t flags;
119 enum reg_enum reg;
120 } specific_registers[] = {
121 {REG_AL, R_AL},
122 {REG_AX, R_AX},
123 {REG_EAX, R_EAX},
124 {REG_RAX, R_RAX},
125 {REG_DL, R_DL},
126 {REG_DX, R_DX},
127 {REG_EDX, R_EDX},
128 {REG_RDX, R_RDX},
129 {REG_CL, R_CL},
130 {REG_CX, R_CX},
131 {REG_ECX, R_ECX},
132 {REG_RCX, R_RCX},
133 {FPU0, R_ST0},
134 {XMM0, R_XMM0},
135 {YMM0, R_YMM0},
136 {REG_ES, R_ES},
137 {REG_CS, R_CS},
138 {REG_SS, R_SS},
139 {REG_DS, R_DS},
140 {REG_FS, R_FS},
141 {REG_GS, R_GS}
142 };
143
144 if (!(regflags & (REGISTER|REGMEM)))
145 return 0; /* Registers not permissible?! */
146
147 regflags |= REGISTER;
148
149 for (i = 0; i < ARRAY_SIZE(specific_registers); i++)
150 if (!(specific_registers[i].flags & ~regflags))
151 return specific_registers[i].reg;
152
153 /* All the entries below look up regval in an 16-entry array */
154 if (regval < 0 || regval > 15)
155 return 0;
156
157 if (!(REG8 & ~regflags)) {
158 if (rex & (REX_P|REX_NH))
159 return nasm_rd_reg8_rex[regval];
160 else
161 return nasm_rd_reg8[regval];
162 }
163 if (!(REG16 & ~regflags))
164 return nasm_rd_reg16[regval];
165 if (!(REG32 & ~regflags))
166 return nasm_rd_reg32[regval];
167 if (!(REG64 & ~regflags))
168 return nasm_rd_reg64[regval];
169 if (!(REG_SREG & ~regflags))
170 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
171 if (!(REG_CREG & ~regflags))
172 return nasm_rd_creg[regval];
173 if (!(REG_DREG & ~regflags))
174 return nasm_rd_dreg[regval];
175 if (!(REG_TREG & ~regflags)) {
176 if (regval > 7)
177 return 0; /* TR registers are ill-defined with rex */
178 return nasm_rd_treg[regval];
179 }
180 if (!(FPUREG & ~regflags))
181 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
182 if (!(MMXREG & ~regflags))
183 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
184 if (!(XMMREG & ~regflags))
185 return nasm_rd_xmmreg[regval];
186 if (!(YMMREG & ~regflags))
187 return nasm_rd_ymmreg[regval];
188
189 return 0;
190 }
191
192 /*
193 * Process an effective address (ModRM) specification.
194 */
195 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
196 int segsize, enum ea_type type,
197 operand *op, insn *ins)
198 {
199 int mod, rm, scale, index, base;
200 int rex;
201 uint8_t sib = 0;
202
203 mod = (modrm >> 6) & 03;
204 rm = modrm & 07;
205
206 if (mod != 3 && asize != 16 && rm == 4)
207 sib = *data++;
208
209 rex = ins->rex;
210
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
214 return data;
215 }
216
217 op->disp_size = 0;
218 op->eaflags = 0;
219
220 if (asize == 16) {
221 /*
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
226 */
227
228 if (type != EA_SCALAR)
229 return NULL;
230
231 op->indexreg = op->basereg = -1;
232 op->scale = 1; /* always, in 16 bits */
233 switch (rm) {
234 case 0:
235 op->basereg = R_BX;
236 op->indexreg = R_SI;
237 break;
238 case 1:
239 op->basereg = R_BX;
240 op->indexreg = R_DI;
241 break;
242 case 2:
243 op->basereg = R_BP;
244 op->indexreg = R_SI;
245 break;
246 case 3:
247 op->basereg = R_BP;
248 op->indexreg = R_DI;
249 break;
250 case 4:
251 op->basereg = R_SI;
252 break;
253 case 5:
254 op->basereg = R_DI;
255 break;
256 case 6:
257 op->basereg = R_BP;
258 break;
259 case 7:
260 op->basereg = R_BX;
261 break;
262 }
263 if (rm == 6 && mod == 0) { /* special case */
264 op->basereg = -1;
265 if (segsize != 16)
266 op->disp_size = 16;
267 mod = 2; /* fake disp16 */
268 }
269 switch (mod) {
270 case 0:
271 op->segment |= SEG_NODISP;
272 break;
273 case 1:
274 op->segment |= SEG_DISP8;
275 op->offset = (int8_t)*data++;
276 break;
277 case 2:
278 op->segment |= SEG_DISP16;
279 op->offset = *data++;
280 op->offset |= ((unsigned)*data++) << 8;
281 break;
282 }
283 return data;
284 } else {
285 /*
286 * Once again, <mod> specifies displacement size (this time
287 * none, byte or *dword*), while <rm> specifies the base
288 * register. Again, [EBP] is missing, replaced by a pure
289 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
290 * and RIP-relative addressing in 64-bit mode.
291 *
292 * However, rm=4
293 * indicates not a single base register, but instead the
294 * presence of a SIB byte...
295 */
296 int a64 = asize == 64;
297
298 op->indexreg = -1;
299
300 if (a64)
301 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
302 else
303 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
304
305 if (rm == 5 && mod == 0) {
306 if (segsize == 64) {
307 op->eaflags |= EAF_REL;
308 op->segment |= SEG_RELATIVE;
309 mod = 2; /* fake disp32 */
310 }
311
312 if (asize != 64)
313 op->disp_size = asize;
314
315 op->basereg = -1;
316 mod = 2; /* fake disp32 */
317 }
318
319
320 if (rm == 4) { /* process SIB */
321 scale = (sib >> 6) & 03;
322 index = (sib >> 3) & 07;
323 base = sib & 07;
324
325 op->scale = 1 << scale;
326
327 if (type == EA_XMMVSIB)
328 op->indexreg = nasm_rd_xmmreg[index | ((rex & REX_X) ? 8 : 0)];
329 else if (type == EA_YMMVSIB)
330 op->indexreg = nasm_rd_ymmreg[index | ((rex & REX_X) ? 8 : 0)];
331 else if (index == 4 && !(rex & REX_X))
332 op->indexreg = -1; /* ESP/RSP cannot be an index */
333 else if (a64)
334 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
335 else
336 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
337
338 if (base == 5 && mod == 0) {
339 op->basereg = -1;
340 mod = 2; /* Fake disp32 */
341 } else if (a64)
342 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
343 else
344 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
345
346 if (segsize == 16)
347 op->disp_size = 32;
348 } else if (type != EA_SCALAR) {
349 /* Can't have VSIB without SIB */
350 return NULL;
351 }
352
353 switch (mod) {
354 case 0:
355 op->segment |= SEG_NODISP;
356 break;
357 case 1:
358 op->segment |= SEG_DISP8;
359 op->offset = gets8(data);
360 data++;
361 break;
362 case 2:
363 op->segment |= SEG_DISP32;
364 op->offset = gets32(data);
365 data += 4;
366 break;
367 }
368 return data;
369 }
370 }
371
372 /*
373 * Determine whether the instruction template in t corresponds to the data
374 * stream in data. Return the number of bytes matched if so.
375 */
376 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
377
378 static int matches(const struct itemplate *t, uint8_t *data,
379 const struct prefix_info *prefix, int segsize, insn *ins)
380 {
381 uint8_t *r = (uint8_t *)(t->code);
382 uint8_t *origdata = data;
383 bool a_used = false, o_used = false;
384 enum prefixes drep = 0;
385 enum prefixes dwait = 0;
386 uint8_t lock = prefix->lock;
387 int osize = prefix->osize;
388 int asize = prefix->asize;
389 int i, c;
390 int op1, op2;
391 struct operand *opx, *opy;
392 uint8_t opex = 0;
393 bool vex_ok = false;
394 int regmask = (segsize == 64) ? 15 : 7;
395 enum ea_type eat = EA_SCALAR;
396
397 for (i = 0; i < MAX_OPERANDS; i++) {
398 ins->oprs[i].segment = ins->oprs[i].disp_size =
399 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
400 }
401 ins->condition = -1;
402 ins->rex = prefix->rex;
403 memset(ins->prefixes, 0, sizeof ins->prefixes);
404
405 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
406 return false;
407
408 if (prefix->rep == 0xF2)
409 drep = P_REPNE;
410 else if (prefix->rep == 0xF3)
411 drep = P_REP;
412
413 dwait = prefix->wait ? P_WAIT : 0;
414
415 while ((c = *r++) != 0) {
416 op1 = (c & 3) + ((opex & 1) << 2);
417 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
418 opx = &ins->oprs[op1];
419 opy = &ins->oprs[op2];
420 opex = 0;
421
422 switch (c) {
423 case 01:
424 case 02:
425 case 03:
426 case 04:
427 while (c--)
428 if (*r++ != *data++)
429 return false;
430 break;
431
432 case 05:
433 case 06:
434 case 07:
435 opex = c;
436 break;
437
438 case4(010):
439 {
440 int t = *r++, d = *data++;
441 if (d < t || d > t + 7)
442 return false;
443 else {
444 opx->basereg = (d-t)+
445 (ins->rex & REX_B ? 8 : 0);
446 opx->segment |= SEG_RMREG;
447 }
448 break;
449 }
450
451 case4(0274):
452 opx->offset = (int8_t)*data++;
453 opx->segment |= SEG_SIGNED;
454 break;
455
456 case4(020):
457 opx->offset = *data++;
458 break;
459
460 case4(024):
461 opx->offset = *data++;
462 break;
463
464 case4(030):
465 opx->offset = getu16(data);
466 data += 2;
467 break;
468
469 case4(034):
470 if (osize == 32) {
471 opx->offset = getu32(data);
472 data += 4;
473 } else {
474 opx->offset = getu16(data);
475 data += 2;
476 }
477 if (segsize != asize)
478 opx->disp_size = asize;
479 break;
480
481 case4(040):
482 opx->offset = getu32(data);
483 data += 4;
484 break;
485
486 case4(0254):
487 opx->offset = gets32(data);
488 data += 4;
489 break;
490
491 case4(044):
492 switch (asize) {
493 case 16:
494 opx->offset = getu16(data);
495 data += 2;
496 if (segsize != 16)
497 opx->disp_size = 16;
498 break;
499 case 32:
500 opx->offset = getu32(data);
501 data += 4;
502 if (segsize == 16)
503 opx->disp_size = 32;
504 break;
505 case 64:
506 opx->offset = getu64(data);
507 opx->disp_size = 64;
508 data += 8;
509 break;
510 }
511 break;
512
513 case4(050):
514 opx->offset = gets8(data++);
515 opx->segment |= SEG_RELATIVE;
516 break;
517
518 case4(054):
519 opx->offset = getu64(data);
520 data += 8;
521 break;
522
523 case4(060):
524 opx->offset = gets16(data);
525 data += 2;
526 opx->segment |= SEG_RELATIVE;
527 opx->segment &= ~SEG_32BIT;
528 break;
529
530 case4(064): /* rel */
531 opx->segment |= SEG_RELATIVE;
532 /* In long mode rel is always 32 bits, sign extended. */
533 if (segsize == 64 || osize == 32) {
534 opx->offset = gets32(data);
535 data += 4;
536 if (segsize != 64)
537 opx->segment |= SEG_32BIT;
538 opx->type = (opx->type & ~SIZE_MASK)
539 | (segsize == 64 ? BITS64 : BITS32);
540 } else {
541 opx->offset = gets16(data);
542 data += 2;
543 opx->segment &= ~SEG_32BIT;
544 opx->type = (opx->type & ~SIZE_MASK) | BITS16;
545 }
546 break;
547
548 case4(070):
549 opx->offset = gets32(data);
550 data += 4;
551 opx->segment |= SEG_32BIT | SEG_RELATIVE;
552 break;
553
554 case4(0100):
555 case4(0110):
556 case4(0120):
557 case4(0130):
558 {
559 int modrm = *data++;
560 opx->segment |= SEG_RMREG;
561 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
562 if (!data)
563 return false;
564 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
565 break;
566 }
567
568 case 0172:
569 {
570 uint8_t ximm = *data++;
571 c = *r++;
572 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
573 ins->oprs[c >> 3].segment |= SEG_RMREG;
574 ins->oprs[c & 7].offset = ximm & 15;
575 }
576 break;
577
578 case 0173:
579 {
580 uint8_t ximm = *data++;
581 c = *r++;
582
583 if ((c ^ ximm) & 15)
584 return false;
585
586 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
587 ins->oprs[c >> 4].segment |= SEG_RMREG;
588 }
589 break;
590
591 case4(0174):
592 {
593 uint8_t ximm = *data++;
594
595 opx->basereg = (ximm >> 4) & regmask;
596 opx->segment |= SEG_RMREG;
597 }
598 break;
599
600 case4(0200):
601 case4(0204):
602 case4(0210):
603 case4(0214):
604 case4(0220):
605 case4(0224):
606 case4(0230):
607 case4(0234):
608 {
609 int modrm = *data++;
610 if (((modrm >> 3) & 07) != (c & 07))
611 return false; /* spare field doesn't match up */
612 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
613 if (!data)
614 return false;
615 break;
616 }
617
618 case4(0260):
619 case 0270:
620 {
621 int vexm = *r++;
622 int vexwlp = *r++;
623
624 ins->rex |= REX_V;
625 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
626 return false;
627
628 if ((vexm & 0x1f) != prefix->vex_m)
629 return false;
630
631 switch (vexwlp & 060) {
632 case 000:
633 if (prefix->rex & REX_W)
634 return false;
635 break;
636 case 020:
637 if (!(prefix->rex & REX_W))
638 return false;
639 ins->rex &= ~REX_W;
640 break;
641 case 040: /* VEX.W is a don't care */
642 ins->rex &= ~REX_W;
643 break;
644 case 060:
645 break;
646 }
647
648 /* The 010 bit of vexwlp is set if VEX.L is ignored */
649 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
650 return false;
651
652 if (c == 0270) {
653 if (prefix->vex_v != 0)
654 return false;
655 } else {
656 opx->segment |= SEG_RMREG;
657 opx->basereg = prefix->vex_v;
658 }
659 vex_ok = true;
660 break;
661 }
662
663 case 0271:
664 if (prefix->rep == 0xF3)
665 drep = P_XRELEASE;
666 break;
667
668 case 0272:
669 if (prefix->rep == 0xF2)
670 drep = P_XACQUIRE;
671 else if (prefix->rep == 0xF3)
672 drep = P_XRELEASE;
673 break;
674
675 case 0273:
676 if (prefix->lock == 0xF0) {
677 if (prefix->rep == 0xF2)
678 drep = P_XACQUIRE;
679 else if (prefix->rep == 0xF3)
680 drep = P_XRELEASE;
681 }
682 break;
683
684 case 0310:
685 if (asize != 16)
686 return false;
687 else
688 a_used = true;
689 break;
690
691 case 0311:
692 if (asize != 32)
693 return false;
694 else
695 a_used = true;
696 break;
697
698 case 0312:
699 if (asize != segsize)
700 return false;
701 else
702 a_used = true;
703 break;
704
705 case 0313:
706 if (asize != 64)
707 return false;
708 else
709 a_used = true;
710 break;
711
712 case 0314:
713 if (prefix->rex & REX_B)
714 return false;
715 break;
716
717 case 0315:
718 if (prefix->rex & REX_X)
719 return false;
720 break;
721
722 case 0316:
723 if (prefix->rex & REX_R)
724 return false;
725 break;
726
727 case 0317:
728 if (prefix->rex & REX_W)
729 return false;
730 break;
731
732 case 0320:
733 if (osize != 16)
734 return false;
735 else
736 o_used = true;
737 break;
738
739 case 0321:
740 if (osize != 32)
741 return false;
742 else
743 o_used = true;
744 break;
745
746 case 0322:
747 if (osize != (segsize == 16) ? 16 : 32)
748 return false;
749 else
750 o_used = true;
751 break;
752
753 case 0323:
754 ins->rex |= REX_W; /* 64-bit only instruction */
755 osize = 64;
756 o_used = true;
757 break;
758
759 case 0324:
760 if (osize != 64)
761 return false;
762 o_used = true;
763 break;
764
765 case 0325:
766 ins->rex |= REX_NH;
767 break;
768
769 case 0330:
770 {
771 int t = *r++, d = *data++;
772 if (d < t || d > t + 15)
773 return false;
774 else
775 ins->condition = d - t;
776 break;
777 }
778
779 case 0326:
780 if (prefix->rep == 0xF3)
781 return false;
782 break;
783
784 case 0331:
785 if (prefix->rep)
786 return false;
787 break;
788
789 case 0332:
790 if (prefix->rep != 0xF2)
791 return false;
792 drep = 0;
793 break;
794
795 case 0333:
796 if (prefix->rep != 0xF3)
797 return false;
798 drep = 0;
799 break;
800
801 case 0334:
802 if (lock) {
803 ins->rex |= REX_R;
804 lock = 0;
805 }
806 break;
807
808 case 0335:
809 if (drep == P_REP)
810 drep = P_REPE;
811 break;
812
813 case 0336:
814 case 0337:
815 break;
816
817 case 0340:
818 return false;
819
820 case 0341:
821 if (prefix->wait != 0x9B)
822 return false;
823 dwait = 0;
824 break;
825
826 case 0360:
827 if (prefix->osp || prefix->rep)
828 return false;
829 break;
830
831 case 0361:
832 if (!prefix->osp || prefix->rep)
833 return false;
834 o_used = true;
835 break;
836
837 case 0364:
838 if (prefix->osp)
839 return false;
840 break;
841
842 case 0365:
843 if (prefix->asp)
844 return false;
845 break;
846
847 case 0366:
848 if (!prefix->osp)
849 return false;
850 o_used = true;
851 break;
852
853 case 0367:
854 if (!prefix->asp)
855 return false;
856 a_used = true;
857 break;
858
859 case 0370:
860 case 0371:
861 break;
862
863 case 0374:
864 eat = EA_XMMVSIB;
865 break;
866
867 case 0375:
868 eat = EA_YMMVSIB;
869 break;
870
871 default:
872 return false; /* Unknown code */
873 }
874 }
875
876 if (!vex_ok && (ins->rex & REX_V))
877 return false;
878
879 /* REX cannot be combined with VEX */
880 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
881 return false;
882
883 /*
884 * Check for unused rep or a/o prefixes.
885 */
886 for (i = 0; i < t->operands; i++) {
887 if (ins->oprs[i].segment != SEG_RMREG)
888 a_used = true;
889 }
890
891 if (lock) {
892 if (ins->prefixes[PPS_LOCK])
893 return false;
894 ins->prefixes[PPS_LOCK] = P_LOCK;
895 }
896 if (drep) {
897 if (ins->prefixes[PPS_REP])
898 return false;
899 ins->prefixes[PPS_REP] = drep;
900 }
901 ins->prefixes[PPS_WAIT] = dwait;
902 if (!o_used) {
903 if (osize != ((segsize == 16) ? 16 : 32)) {
904 enum prefixes pfx = 0;
905
906 switch (osize) {
907 case 16:
908 pfx = P_O16;
909 break;
910 case 32:
911 pfx = P_O32;
912 break;
913 case 64:
914 pfx = P_O64;
915 break;
916 }
917
918 if (ins->prefixes[PPS_OSIZE])
919 return false;
920 ins->prefixes[PPS_OSIZE] = pfx;
921 }
922 }
923 if (!a_used && asize != segsize) {
924 if (ins->prefixes[PPS_ASIZE])
925 return false;
926 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
927 }
928
929 /* Fix: check for redundant REX prefixes */
930
931 return data - origdata;
932 }
933
934 /* Condition names for disassembly, sorted by x86 code */
935 static const char * const condition_name[16] = {
936 "o", "no", "c", "nc", "z", "nz", "na", "a",
937 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
938 };
939
940 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
941 int32_t offset, int autosync, uint32_t prefer)
942 {
943 const struct itemplate * const *p, * const *best_p;
944 const struct disasm_index *ix;
945 uint8_t *dp;
946 int length, best_length = 0;
947 char *segover;
948 int i, slen, colon, n;
949 uint8_t *origdata;
950 int works;
951 insn tmp_ins, ins;
952 uint32_t goodness, best;
953 int best_pref;
954 struct prefix_info prefix;
955 bool end_prefix;
956
957 memset(&ins, 0, sizeof ins);
958
959 /*
960 * Scan for prefixes.
961 */
962 memset(&prefix, 0, sizeof prefix);
963 prefix.asize = segsize;
964 prefix.osize = (segsize == 64) ? 32 : segsize;
965 segover = NULL;
966 origdata = data;
967
968 ix = itable;
969
970 end_prefix = false;
971 while (!end_prefix) {
972 switch (*data) {
973 case 0xF2:
974 case 0xF3:
975 prefix.rep = *data++;
976 break;
977
978 case 0x9B:
979 prefix.wait = *data++;
980 break;
981
982 case 0xF0:
983 prefix.lock = *data++;
984 break;
985
986 case 0x2E:
987 segover = "cs", prefix.seg = *data++;
988 break;
989 case 0x36:
990 segover = "ss", prefix.seg = *data++;
991 break;
992 case 0x3E:
993 segover = "ds", prefix.seg = *data++;
994 break;
995 case 0x26:
996 segover = "es", prefix.seg = *data++;
997 break;
998 case 0x64:
999 segover = "fs", prefix.seg = *data++;
1000 break;
1001 case 0x65:
1002 segover = "gs", prefix.seg = *data++;
1003 break;
1004
1005 case 0x66:
1006 prefix.osize = (segsize == 16) ? 32 : 16;
1007 prefix.osp = *data++;
1008 break;
1009 case 0x67:
1010 prefix.asize = (segsize == 32) ? 16 : 32;
1011 prefix.asp = *data++;
1012 break;
1013
1014 case 0xC4:
1015 case 0xC5:
1016 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1017 prefix.vex[0] = *data++;
1018 prefix.vex[1] = *data++;
1019
1020 prefix.rex = REX_V;
1021 prefix.vex_c = RV_VEX;
1022
1023 if (prefix.vex[0] == 0xc4) {
1024 prefix.vex[2] = *data++;
1025 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1026 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1027 prefix.vex_m = prefix.vex[1] & 0x1f;
1028 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1029 prefix.vex_lp = prefix.vex[2] & 7;
1030 } else {
1031 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1032 prefix.vex_m = 1;
1033 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1034 prefix.vex_lp = prefix.vex[1] & 7;
1035 }
1036
1037 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1038 }
1039 end_prefix = true;
1040 break;
1041
1042 case 0x8F:
1043 if ((data[1] & 030) != 0 &&
1044 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1045 prefix.vex[0] = *data++;
1046 prefix.vex[1] = *data++;
1047 prefix.vex[2] = *data++;
1048
1049 prefix.rex = REX_V;
1050 prefix.vex_c = RV_XOP;
1051
1052 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1053 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1054 prefix.vex_m = prefix.vex[1] & 0x1f;
1055 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1056 prefix.vex_lp = prefix.vex[2] & 7;
1057
1058 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1059 }
1060 end_prefix = true;
1061 break;
1062
1063 case REX_P + 0x0:
1064 case REX_P + 0x1:
1065 case REX_P + 0x2:
1066 case REX_P + 0x3:
1067 case REX_P + 0x4:
1068 case REX_P + 0x5:
1069 case REX_P + 0x6:
1070 case REX_P + 0x7:
1071 case REX_P + 0x8:
1072 case REX_P + 0x9:
1073 case REX_P + 0xA:
1074 case REX_P + 0xB:
1075 case REX_P + 0xC:
1076 case REX_P + 0xD:
1077 case REX_P + 0xE:
1078 case REX_P + 0xF:
1079 if (segsize == 64) {
1080 prefix.rex = *data++;
1081 if (prefix.rex & REX_W)
1082 prefix.osize = 64;
1083 }
1084 end_prefix = true;
1085 break;
1086
1087 default:
1088 end_prefix = true;
1089 break;
1090 }
1091 }
1092
1093 best = -1; /* Worst possible */
1094 best_p = NULL;
1095 best_pref = INT_MAX;
1096
1097 if (!ix)
1098 return 0; /* No instruction table at all... */
1099
1100 dp = data;
1101 ix += *dp++;
1102 while (ix->n == -1) {
1103 ix = (const struct disasm_index *)ix->p + *dp++;
1104 }
1105
1106 p = (const struct itemplate * const *)ix->p;
1107 for (n = ix->n; n; n--, p++) {
1108 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1109 works = true;
1110 /*
1111 * Final check to make sure the types of r/m match up.
1112 * XXX: Need to make sure this is actually correct.
1113 */
1114 for (i = 0; i < (*p)->operands; i++) {
1115 if (
1116 /* If it's a mem-only EA but we have a
1117 register, die. */
1118 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1119 is_class(MEMORY, (*p)->opd[i])) ||
1120 /* If it's a reg-only EA but we have a memory
1121 ref, die. */
1122 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1123 !(REG_EA & ~(*p)->opd[i]) &&
1124 !((*p)->opd[i] & REG_SMASK)) ||
1125 /* Register type mismatch (eg FS vs REG_DESS):
1126 die. */
1127 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1128 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1129 !whichreg((*p)->opd[i],
1130 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1131 ) {
1132 works = false;
1133 break;
1134 }
1135 }
1136
1137 /*
1138 * Note: we always prefer instructions which incorporate
1139 * prefixes in the instructions themselves. This is to allow
1140 * e.g. PAUSE to be preferred to REP NOP, and deal with
1141 * MMX/SSE instructions where prefixes are used to select
1142 * between MMX and SSE register sets or outright opcode
1143 * selection.
1144 */
1145 if (works) {
1146 int i, nprefix;
1147 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1148 nprefix = 0;
1149 for (i = 0; i < MAXPREFIX; i++)
1150 if (tmp_ins.prefixes[i])
1151 nprefix++;
1152 if (nprefix < best_pref ||
1153 (nprefix == best_pref && goodness < best)) {
1154 /* This is the best one found so far */
1155 best = goodness;
1156 best_p = p;
1157 best_pref = nprefix;
1158 best_length = length;
1159 ins = tmp_ins;
1160 }
1161 }
1162 }
1163 }
1164
1165 if (!best_p)
1166 return 0; /* no instruction was matched */
1167
1168 /* Pick the best match */
1169 p = best_p;
1170 length = best_length;
1171
1172 slen = 0;
1173
1174 /* TODO: snprintf returns the value that the string would have if
1175 * the buffer were long enough, and not the actual length of
1176 * the returned string, so each instance of using the return
1177 * value of snprintf should actually be checked to assure that
1178 * the return value is "sane." Maybe a macro wrapper could
1179 * be used for that purpose.
1180 */
1181 for (i = 0; i < MAXPREFIX; i++) {
1182 const char *prefix = prefix_name(ins.prefixes[i]);
1183 if (prefix)
1184 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1185 }
1186
1187 i = (*p)->opcode;
1188 if (i >= FIRST_COND_OPCODE)
1189 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1190 nasm_insn_names[i], condition_name[ins.condition]);
1191 else
1192 slen += snprintf(output + slen, outbufsize - slen, "%s",
1193 nasm_insn_names[i]);
1194
1195 colon = false;
1196 length += data - origdata; /* fix up for prefixes */
1197 for (i = 0; i < (*p)->operands; i++) {
1198 opflags_t t = (*p)->opd[i];
1199 const operand *o = &ins.oprs[i];
1200 int64_t offs;
1201
1202 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1203
1204 offs = o->offset;
1205 if (o->segment & SEG_RELATIVE) {
1206 offs += offset + length;
1207 /*
1208 * sort out wraparound
1209 */
1210 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1211 offs &= 0xffff;
1212 else if (segsize != 64)
1213 offs &= 0xffffffff;
1214
1215 /*
1216 * add sync marker, if autosync is on
1217 */
1218 if (autosync)
1219 add_sync(offs, 0L);
1220 }
1221
1222 if (t & COLON)
1223 colon = true;
1224 else
1225 colon = false;
1226
1227 if ((t & (REGISTER | FPUREG)) ||
1228 (o->segment & SEG_RMREG)) {
1229 enum reg_enum reg;
1230 reg = whichreg(t, o->basereg, ins.rex);
1231 if (t & TO)
1232 slen += snprintf(output + slen, outbufsize - slen, "to ");
1233 slen += snprintf(output + slen, outbufsize - slen, "%s",
1234 nasm_reg_names[reg-EXPR_REG_START]);
1235 } else if (!(UNITY & ~t)) {
1236 output[slen++] = '1';
1237 } else if (t & IMMEDIATE) {
1238 if (t & BITS8) {
1239 slen +=
1240 snprintf(output + slen, outbufsize - slen, "byte ");
1241 if (o->segment & SEG_SIGNED) {
1242 if (offs < 0) {
1243 offs *= -1;
1244 output[slen++] = '-';
1245 } else
1246 output[slen++] = '+';
1247 }
1248 } else if (t & BITS16) {
1249 slen +=
1250 snprintf(output + slen, outbufsize - slen, "word ");
1251 } else if (t & BITS32) {
1252 slen +=
1253 snprintf(output + slen, outbufsize - slen, "dword ");
1254 } else if (t & BITS64) {
1255 slen +=
1256 snprintf(output + slen, outbufsize - slen, "qword ");
1257 } else if (t & NEAR) {
1258 slen +=
1259 snprintf(output + slen, outbufsize - slen, "near ");
1260 } else if (t & SHORT) {
1261 slen +=
1262 snprintf(output + slen, outbufsize - slen, "short ");
1263 }
1264 slen +=
1265 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1266 offs);
1267 } else if (!(MEM_OFFS & ~t)) {
1268 slen +=
1269 snprintf(output + slen, outbufsize - slen,
1270 "[%s%s%s0x%"PRIx64"]",
1271 (segover ? segover : ""),
1272 (segover ? ":" : ""),
1273 (o->disp_size == 64 ? "qword " :
1274 o->disp_size == 32 ? "dword " :
1275 o->disp_size == 16 ? "word " : ""), offs);
1276 segover = NULL;
1277 } else if (is_class(REGMEM, t)) {
1278 int started = false;
1279 if (t & BITS8)
1280 slen +=
1281 snprintf(output + slen, outbufsize - slen, "byte ");
1282 if (t & BITS16)
1283 slen +=
1284 snprintf(output + slen, outbufsize - slen, "word ");
1285 if (t & BITS32)
1286 slen +=
1287 snprintf(output + slen, outbufsize - slen, "dword ");
1288 if (t & BITS64)
1289 slen +=
1290 snprintf(output + slen, outbufsize - slen, "qword ");
1291 if (t & BITS80)
1292 slen +=
1293 snprintf(output + slen, outbufsize - slen, "tword ");
1294 if (t & BITS128)
1295 slen +=
1296 snprintf(output + slen, outbufsize - slen, "oword ");
1297 if (t & BITS256)
1298 slen +=
1299 snprintf(output + slen, outbufsize - slen, "yword ");
1300 if (t & FAR)
1301 slen += snprintf(output + slen, outbufsize - slen, "far ");
1302 if (t & NEAR)
1303 slen +=
1304 snprintf(output + slen, outbufsize - slen, "near ");
1305 output[slen++] = '[';
1306 if (o->disp_size)
1307 slen += snprintf(output + slen, outbufsize - slen, "%s",
1308 (o->disp_size == 64 ? "qword " :
1309 o->disp_size == 32 ? "dword " :
1310 o->disp_size == 16 ? "word " :
1311 ""));
1312 if (o->eaflags & EAF_REL)
1313 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1314 if (segover) {
1315 slen +=
1316 snprintf(output + slen, outbufsize - slen, "%s:",
1317 segover);
1318 segover = NULL;
1319 }
1320 if (o->basereg != -1) {
1321 slen += snprintf(output + slen, outbufsize - slen, "%s",
1322 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1323 started = true;
1324 }
1325 if (o->indexreg != -1) {
1326 if (started)
1327 output[slen++] = '+';
1328 slen += snprintf(output + slen, outbufsize - slen, "%s",
1329 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1330 if (o->scale > 1)
1331 slen +=
1332 snprintf(output + slen, outbufsize - slen, "*%d",
1333 o->scale);
1334 started = true;
1335 }
1336
1337
1338 if (o->segment & SEG_DISP8) {
1339 const char *prefix;
1340 uint8_t offset = offs;
1341 if ((int8_t)offset < 0) {
1342 prefix = "-";
1343 offset = -offset;
1344 } else {
1345 prefix = "+";
1346 }
1347 slen +=
1348 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1349 prefix, offset);
1350 } else if (o->segment & SEG_DISP16) {
1351 const char *prefix;
1352 uint16_t offset = offs;
1353 if ((int16_t)offset < 0 && started) {
1354 offset = -offset;
1355 prefix = "-";
1356 } else {
1357 prefix = started ? "+" : "";
1358 }
1359 slen +=
1360 snprintf(output + slen, outbufsize - slen,
1361 "%s0x%"PRIx16"", prefix, offset);
1362 } else if (o->segment & SEG_DISP32) {
1363 if (prefix.asize == 64) {
1364 const char *prefix;
1365 uint64_t offset = (int64_t)(int32_t)offs;
1366 if ((int32_t)offs < 0 && started) {
1367 offset = -offset;
1368 prefix = "-";
1369 } else {
1370 prefix = started ? "+" : "";
1371 }
1372 slen +=
1373 snprintf(output + slen, outbufsize - slen,
1374 "%s0x%"PRIx64"", prefix, offset);
1375 } else {
1376 const char *prefix;
1377 uint32_t offset = offs;
1378 if ((int32_t) offset < 0 && started) {
1379 offset = -offset;
1380 prefix = "-";
1381 } else {
1382 prefix = started ? "+" : "";
1383 }
1384 slen +=
1385 snprintf(output + slen, outbufsize - slen,
1386 "%s0x%"PRIx32"", prefix, offset);
1387 }
1388 }
1389 output[slen++] = ']';
1390 } else {
1391 slen +=
1392 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1393 i);
1394 }
1395 }
1396 output[slen] = '\0';
1397 if (segover) { /* unused segment override */
1398 char *p = output;
1399 int count = slen + 1;
1400 while (count--)
1401 p[count + 3] = p[count];
1402 strncpy(output, segover, 2);
1403 output[2] = ' ';
1404 }
1405 return length;
1406 }
1407
1408 /*
1409 * This is called when we don't have a complete instruction. If it
1410 * is a standalone *single-byte* prefix show it as such, otherwise
1411 * print it as a literal.
1412 */
1413 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1414 {
1415 uint8_t byte = *data;
1416 const char *str = NULL;
1417
1418 switch (byte) {
1419 case 0xF2:
1420 str = "repne";
1421 break;
1422 case 0xF3:
1423 str = "rep";
1424 break;
1425 case 0x9B:
1426 str = "wait";
1427 break;
1428 case 0xF0:
1429 str = "lock";
1430 break;
1431 case 0x2E:
1432 str = "cs";
1433 break;
1434 case 0x36:
1435 str = "ss";
1436 break;
1437 case 0x3E:
1438 str = "ss";
1439 break;
1440 case 0x26:
1441 str = "es";
1442 break;
1443 case 0x64:
1444 str = "fs";
1445 break;
1446 case 0x65:
1447 str = "gs";
1448 break;
1449 case 0x66:
1450 str = (segsize == 16) ? "o32" : "o16";
1451 break;
1452 case 0x67:
1453 str = (segsize == 32) ? "a16" : "a32";
1454 break;
1455 case REX_P + 0x0:
1456 case REX_P + 0x1:
1457 case REX_P + 0x2:
1458 case REX_P + 0x3:
1459 case REX_P + 0x4:
1460 case REX_P + 0x5:
1461 case REX_P + 0x6:
1462 case REX_P + 0x7:
1463 case REX_P + 0x8:
1464 case REX_P + 0x9:
1465 case REX_P + 0xA:
1466 case REX_P + 0xB:
1467 case REX_P + 0xC:
1468 case REX_P + 0xD:
1469 case REX_P + 0xE:
1470 case REX_P + 0xF:
1471 if (segsize == 64) {
1472 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1473 (byte == REX_P) ? "" : ".",
1474 (byte & REX_W) ? "w" : "",
1475 (byte & REX_R) ? "r" : "",
1476 (byte & REX_X) ? "x" : "",
1477 (byte & REX_B) ? "b" : "");
1478 break;
1479 }
1480 /* else fall through */
1481 default:
1482 snprintf(output, outbufsize, "db 0x%02x", byte);
1483 break;
1484 }
1485
1486 if (str)
1487 snprintf(output, outbufsize, "%s", str);
1488
1489 return 1;
1490 }
The Netwide Assembler