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doc: Document DEFAULT BND/NOBND in changes, add use case
[nasm.git] / assemble.c
blobeeab9bbc9aa0e6617d871a51bc0c03acf1a4d393
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
71 *
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
78 * cc 000 0mm
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
80 * and wlp is:
81 * 00 wwl lpp
82 * [l0] ll = 0 (.128, .lz)
83 * [l1] ll = 1 (.256)
84 * [l2] ll = 2 (.512)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
86 *
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
91 *
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
94 * [f3] pp = 2
95 * [f2] pp = 3
96 *
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
99 *
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
105 *
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
108 * 00 wwl lpp
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
112 *
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
117 *
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
119 *
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
170 */
171
172 #include "compiler.h"
173
174 #include <stdio.h>
175 #include <string.h>
176 #include <inttypes.h>
177
178 #include "nasm.h"
179 #include "nasmlib.h"
180 #include "assemble.h"
181 #include "insns.h"
182 #include "tables.h"
183 #include "disp8.h"
184
185 enum match_result {
186 /*
187 * Matching errors. These should be sorted so that more specific
188 * errors come later in the sequence.
189 */
190 MERR_INVALOP,
191 MERR_OPSIZEMISSING,
192 MERR_OPSIZEMISMATCH,
193 MERR_BRNUMMISMATCH,
194 MERR_BADCPU,
195 MERR_BADMODE,
196 MERR_BADHLE,
197 MERR_ENCMISMATCH,
198 MERR_BADBND,
199 MERR_BADREPNE,
200 /*
201 * Matching success; the conditional ones first
202 */
203 MOK_JUMP, /* Matching OK but needs jmp_match() */
204 MOK_GOOD /* Matching unconditionally OK */
205 };
206
207 typedef struct {
208 enum ea_type type; /* what kind of EA is this? */
209 int sib_present; /* is a SIB byte necessary? */
210 int bytes; /* # of bytes of offset needed */
211 int size; /* lazy - this is sib+bytes+1 */
212 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
213 int8_t disp8; /* compressed displacement for EVEX */
214 } ea;
215
216 #define GEN_SIB(scale, index, base) \
217 (((scale) << 6) | ((index) << 3) | ((base)))
218
219 #define GEN_MODRM(mod, reg, rm) \
220 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
221
222 static iflag_t cpu; /* cpu level received from nasm.c */
223 static efunc errfunc;
224 static struct ofmt *outfmt;
225 static ListGen *list;
226
227 static int64_t calcsize(int32_t, int64_t, int, insn *,
228 const struct itemplate *);
229 static void gencode(int32_t segment, int64_t offset, int bits,
230 insn * ins, const struct itemplate *temp,
231 int64_t insn_end);
232 static enum match_result find_match(const struct itemplate **tempp,
233 insn *instruction,
234 int32_t segment, int64_t offset, int bits);
235 static enum match_result matches(const struct itemplate *, insn *, int bits);
236 static opflags_t regflag(const operand *);
237 static int32_t regval(const operand *);
238 static int rexflags(int, opflags_t, int);
239 static int op_rexflags(const operand *, int);
240 static int op_evexflags(const operand *, int, uint8_t);
241 static void add_asp(insn *, int);
242
243 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
244
245 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
246 {
247 return ins->prefixes[pos] == prefix;
248 }
249
250 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
251 {
252 if (ins->prefixes[pos])
253 errfunc(ERR_NONFATAL, "invalid %s prefix",
254 prefix_name(ins->prefixes[pos]));
255 }
256
257 static const char *size_name(int size)
258 {
259 switch (size) {
260 case 1:
261 return "byte";
262 case 2:
263 return "word";
264 case 4:
265 return "dword";
266 case 8:
267 return "qword";
268 case 10:
269 return "tword";
270 case 16:
271 return "oword";
272 case 32:
273 return "yword";
274 case 64:
275 return "zword";
276 default:
277 return "???";
278 }
279 }
280
281 static void warn_overflow(int pass, int size)
282 {
283 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
284 "%s data exceeds bounds", size_name(size));
285 }
286
287 static void warn_overflow_const(int64_t data, int size)
288 {
289 if (overflow_general(data, size))
290 warn_overflow(ERR_PASS1, size);
291 }
292
293 static void warn_overflow_opd(const struct operand *o, int size)
294 {
295 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
296 if (overflow_general(o->offset, size))
297 warn_overflow(ERR_PASS2, size);
298 }
299 }
300
301 /*
302 * This routine wrappers the real output format's output routine,
303 * in order to pass a copy of the data off to the listing file
304 * generator at the same time.
305 */
306 static void out(int64_t offset, int32_t segto, const void *data,
307 enum out_type type, uint64_t size,
308 int32_t segment, int32_t wrt)
309 {
310 static int32_t lineno = 0; /* static!!! */
311 static char *lnfname = NULL;
312 uint8_t p[8];
313
314 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
315 /*
316 * This is a non-relocated address, and we're going to
317 * convert it into RAWDATA format.
318 */
319 uint8_t *q = p;
320
321 if (size > 8) {
322 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
323 return;
324 }
325
326 WRITEADDR(q, *(int64_t *)data, size);
327 data = p;
328 type = OUT_RAWDATA;
329 }
330
331 list->output(offset, data, type, size);
332
333 /*
334 * this call to src_get determines when we call the
335 * debug-format-specific "linenum" function
336 * it updates lineno and lnfname to the current values
337 * returning 0 if "same as last time", -2 if lnfname
338 * changed, and the amount by which lineno changed,
339 * if it did. thus, these variables must be static
340 */
341
342 if (src_get(&lineno, &lnfname))
343 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
344
345 outfmt->output(segto, data, type, size, segment, wrt);
346 }
347
348 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
349 {
350 if (opx->segment != NO_SEG) {
351 uint64_t data = opx->offset;
352 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
353 } else {
354 uint8_t byte = opx->offset;
355 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
356 }
357 }
358
359 static bool jmp_match(int32_t segment, int64_t offset, int bits,
360 insn * ins, const struct itemplate *temp)
361 {
362 int64_t isize;
363 const uint8_t *code = temp->code;
364 uint8_t c = code[0];
365 bool is_byte;
366
367 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
368 return false;
369 if (!optimizing)
370 return false;
371 if (optimizing < 0 && c == 0371)
372 return false;
373
374 isize = calcsize(segment, offset, bits, ins, temp);
375
376 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
377 /* Be optimistic in pass 1 */
378 return true;
379
380 if (ins->oprs[0].segment != segment)
381 return false;
382
383 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
384 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
385
386 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
387 /* jmp short (opcode eb) cannot be used with bnd prefix. */
388 ins->prefixes[PPS_REP] = P_none;
389 errfunc(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
390 "jmp short does not init bnd regs - bnd prefix dropped.");
391 }
392
393 return is_byte;
394 }
395
396 int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
397 insn * instruction, struct ofmt *output, efunc error,
398 ListGen * listgen)
399 {
400 const struct itemplate *temp;
401 int j;
402 enum match_result m;
403 int64_t insn_end;
404 int32_t itimes;
405 int64_t start = offset;
406 int64_t wsize; /* size for DB etc. */
407
408 errfunc = error; /* to pass to other functions */
409 cpu = cp;
410 outfmt = output; /* likewise */
411 list = listgen; /* and again */
412
413 wsize = idata_bytes(instruction->opcode);
414 if (wsize == -1)
415 return 0;
416
417 if (wsize) {
418 extop *e;
419 int32_t t = instruction->times;
420 if (t < 0)
421 errfunc(ERR_PANIC,
422 "instruction->times < 0 (%ld) in assemble()", t);
423
424 while (t--) { /* repeat TIMES times */
425 list_for_each(e, instruction->eops) {
426 if (e->type == EOT_DB_NUMBER) {
427 if (wsize > 8) {
428 errfunc(ERR_NONFATAL,
429 "integer supplied to a DT, DO or DY"
430 " instruction");
431 } else {
432 out(offset, segment, &e->offset,
433 OUT_ADDRESS, wsize, e->segment, e->wrt);
434 offset += wsize;
435 }
436 } else if (e->type == EOT_DB_STRING ||
437 e->type == EOT_DB_STRING_FREE) {
438 int align;
439
440 out(offset, segment, e->stringval,
441 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
442 align = e->stringlen % wsize;
443
444 if (align) {
445 align = wsize - align;
446 out(offset, segment, zero_buffer,
447 OUT_RAWDATA, align, NO_SEG, NO_SEG);
448 }
449 offset += e->stringlen + align;
450 }
451 }
452 if (t > 0 && t == instruction->times - 1) {
453 /*
454 * Dummy call to list->output to give the offset to the
455 * listing module.
456 */
457 list->output(offset, NULL, OUT_RAWDATA, 0);
458 list->uplevel(LIST_TIMES);
459 }
460 }
461 if (instruction->times > 1)
462 list->downlevel(LIST_TIMES);
463 return offset - start;
464 }
465
466 if (instruction->opcode == I_INCBIN) {
467 const char *fname = instruction->eops->stringval;
468 FILE *fp;
469
470 fp = fopen(fname, "rb");
471 if (!fp) {
472 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
473 fname);
474 } else if (fseek(fp, 0L, SEEK_END) < 0) {
475 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
476 fname);
477 fclose(fp);
478 } else {
479 static char buf[4096];
480 size_t t = instruction->times;
481 size_t base = 0;
482 size_t len;
483
484 len = ftell(fp);
485 if (instruction->eops->next) {
486 base = instruction->eops->next->offset;
487 len -= base;
488 if (instruction->eops->next->next &&
489 len > (size_t)instruction->eops->next->next->offset)
490 len = (size_t)instruction->eops->next->next->offset;
491 }
492 /*
493 * Dummy call to list->output to give the offset to the
494 * listing module.
495 */
496 list->output(offset, NULL, OUT_RAWDATA, 0);
497 list->uplevel(LIST_INCBIN);
498 while (t--) {
499 size_t l;
500
501 fseek(fp, base, SEEK_SET);
502 l = len;
503 while (l > 0) {
504 int32_t m;
505 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
506 if (!m) {
507 /*
508 * This shouldn't happen unless the file
509 * actually changes while we are reading
510 * it.
511 */
512 error(ERR_NONFATAL,
513 "`incbin': unexpected EOF while"
514 " reading file `%s'", fname);
515 t = 0; /* Try to exit cleanly */
516 break;
517 }
518 out(offset, segment, buf, OUT_RAWDATA, m,
519 NO_SEG, NO_SEG);
520 l -= m;
521 }
522 }
523 list->downlevel(LIST_INCBIN);
524 if (instruction->times > 1) {
525 /*
526 * Dummy call to list->output to give the offset to the
527 * listing module.
528 */
529 list->output(offset, NULL, OUT_RAWDATA, 0);
530 list->uplevel(LIST_TIMES);
531 list->downlevel(LIST_TIMES);
532 }
533 fclose(fp);
534 return instruction->times * len;
535 }
536 return 0; /* if we're here, there's an error */
537 }
538
539 /* Check to see if we need an address-size prefix */
540 add_asp(instruction, bits);
541
542 m = find_match(&temp, instruction, segment, offset, bits);
543
544 if (m == MOK_GOOD) {
545 /* Matches! */
546 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
547 itimes = instruction->times;
548 if (insn_size < 0) /* shouldn't be, on pass two */
549 error(ERR_PANIC, "errors made it through from pass one");
550 else
551 while (itimes--) {
552 for (j = 0; j < MAXPREFIX; j++) {
553 uint8_t c = 0;
554 switch (instruction->prefixes[j]) {
555 case P_WAIT:
556 c = 0x9B;
557 break;
558 case P_LOCK:
559 c = 0xF0;
560 break;
561 case P_REPNE:
562 case P_REPNZ:
563 case P_XACQUIRE:
564 case P_BND:
565 c = 0xF2;
566 break;
567 case P_REPE:
568 case P_REPZ:
569 case P_REP:
570 case P_XRELEASE:
571 c = 0xF3;
572 break;
573 case R_CS:
574 if (bits == 64) {
575 error(ERR_WARNING | ERR_PASS2,
576 "cs segment base generated, but will be ignored in 64-bit mode");
577 }
578 c = 0x2E;
579 break;
580 case R_DS:
581 if (bits == 64) {
582 error(ERR_WARNING | ERR_PASS2,
583 "ds segment base generated, but will be ignored in 64-bit mode");
584 }
585 c = 0x3E;
586 break;
587 case R_ES:
588 if (bits == 64) {
589 error(ERR_WARNING | ERR_PASS2,
590 "es segment base generated, but will be ignored in 64-bit mode");
591 }
592 c = 0x26;
593 break;
594 case R_FS:
595 c = 0x64;
596 break;
597 case R_GS:
598 c = 0x65;
599 break;
600 case R_SS:
601 if (bits == 64) {
602 error(ERR_WARNING | ERR_PASS2,
603 "ss segment base generated, but will be ignored in 64-bit mode");
604 }
605 c = 0x36;
606 break;
607 case R_SEGR6:
608 case R_SEGR7:
609 error(ERR_NONFATAL,
610 "segr6 and segr7 cannot be used as prefixes");
611 break;
612 case P_A16:
613 if (bits == 64) {
614 error(ERR_NONFATAL,
615 "16-bit addressing is not supported "
616 "in 64-bit mode");
617 } else if (bits != 16)
618 c = 0x67;
619 break;
620 case P_A32:
621 if (bits != 32)
622 c = 0x67;
623 break;
624 case P_A64:
625 if (bits != 64) {
626 error(ERR_NONFATAL,
627 "64-bit addressing is only supported "
628 "in 64-bit mode");
629 }
630 break;
631 case P_ASP:
632 c = 0x67;
633 break;
634 case P_O16:
635 if (bits != 16)
636 c = 0x66;
637 break;
638 case P_O32:
639 if (bits == 16)
640 c = 0x66;
641 break;
642 case P_O64:
643 /* REX.W */
644 break;
645 case P_OSP:
646 c = 0x66;
647 break;
648 case P_EVEX:
649 case P_VEX3:
650 case P_VEX2:
651 case P_NOBND:
652 case P_none:
653 break;
654 default:
655 error(ERR_PANIC, "invalid instruction prefix");
656 }
657 if (c != 0) {
658 out(offset, segment, &c, OUT_RAWDATA, 1,
659 NO_SEG, NO_SEG);
660 offset++;
661 }
662 }
663 insn_end = offset + insn_size;
664 gencode(segment, offset, bits, instruction,
665 temp, insn_end);
666 offset += insn_size;
667 if (itimes > 0 && itimes == instruction->times - 1) {
668 /*
669 * Dummy call to list->output to give the offset to the
670 * listing module.
671 */
672 list->output(offset, NULL, OUT_RAWDATA, 0);
673 list->uplevel(LIST_TIMES);
674 }
675 }
676 if (instruction->times > 1)
677 list->downlevel(LIST_TIMES);
678 return offset - start;
679 } else {
680 /* No match */
681 switch (m) {
682 case MERR_OPSIZEMISSING:
683 error(ERR_NONFATAL, "operation size not specified");
684 break;
685 case MERR_OPSIZEMISMATCH:
686 error(ERR_NONFATAL, "mismatch in operand sizes");
687 break;
688 case MERR_BRNUMMISMATCH:
689 error(ERR_NONFATAL,
690 "mismatch in the number of broadcasting elements");
691 break;
692 case MERR_BADCPU:
693 error(ERR_NONFATAL, "no instruction for this cpu level");
694 break;
695 case MERR_BADMODE:
696 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
697 bits);
698 break;
699 case MERR_ENCMISMATCH:
700 error(ERR_NONFATAL, "specific encoding scheme not available");
701 break;
702 case MERR_BADBND:
703 error(ERR_NONFATAL, "bnd prefix is not allowed");
704 break;
705 case MERR_BADREPNE:
706 error(ERR_NONFATAL, "%s prefix is not allowed",
707 (has_prefix(instruction, PPS_REP, P_REPNE) ?
708 "repne" : "repnz"));
709 break;
710 default:
711 error(ERR_NONFATAL,
712 "invalid combination of opcode and operands");
713 break;
714 }
715 }
716 return 0;
717 }
718
719 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
720 insn * instruction, efunc error)
721 {
722 const struct itemplate *temp;
723 enum match_result m;
724
725 errfunc = error; /* to pass to other functions */
726 cpu = cp;
727
728 if (instruction->opcode == I_none)
729 return 0;
730
731 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
732 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
733 instruction->opcode == I_DT || instruction->opcode == I_DO ||
734 instruction->opcode == I_DY) {
735 extop *e;
736 int32_t isize, osize, wsize;
737
738 isize = 0;
739 wsize = idata_bytes(instruction->opcode);
740
741 list_for_each(e, instruction->eops) {
742 int32_t align;
743
744 osize = 0;
745 if (e->type == EOT_DB_NUMBER) {
746 osize = 1;
747 warn_overflow_const(e->offset, wsize);
748 } else if (e->type == EOT_DB_STRING ||
749 e->type == EOT_DB_STRING_FREE)
750 osize = e->stringlen;
751
752 align = (-osize) % wsize;
753 if (align < 0)
754 align += wsize;
755 isize += osize + align;
756 }
757 return isize * instruction->times;
758 }
759
760 if (instruction->opcode == I_INCBIN) {
761 const char *fname = instruction->eops->stringval;
762 FILE *fp;
763 int64_t val = 0;
764 size_t len;
765
766 fp = fopen(fname, "rb");
767 if (!fp)
768 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
769 fname);
770 else if (fseek(fp, 0L, SEEK_END) < 0)
771 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
772 fname);
773 else {
774 len = ftell(fp);
775 if (instruction->eops->next) {
776 len -= instruction->eops->next->offset;
777 if (instruction->eops->next->next &&
778 len > (size_t)instruction->eops->next->next->offset) {
779 len = (size_t)instruction->eops->next->next->offset;
780 }
781 }
782 val = instruction->times * len;
783 }
784 if (fp)
785 fclose(fp);
786 return val;
787 }
788
789 /* Check to see if we need an address-size prefix */
790 add_asp(instruction, bits);
791
792 m = find_match(&temp, instruction, segment, offset, bits);
793 if (m == MOK_GOOD) {
794 /* we've matched an instruction. */
795 int64_t isize;
796 int j;
797
798 isize = calcsize(segment, offset, bits, instruction, temp);
799 if (isize < 0)
800 return -1;
801 for (j = 0; j < MAXPREFIX; j++) {
802 switch (instruction->prefixes[j]) {
803 case P_A16:
804 if (bits != 16)
805 isize++;
806 break;
807 case P_A32:
808 if (bits != 32)
809 isize++;
810 break;
811 case P_O16:
812 if (bits != 16)
813 isize++;
814 break;
815 case P_O32:
816 if (bits == 16)
817 isize++;
818 break;
819 case P_A64:
820 case P_O64:
821 case P_EVEX:
822 case P_VEX3:
823 case P_VEX2:
824 case P_NOBND:
825 case P_none:
826 break;
827 default:
828 isize++;
829 break;
830 }
831 }
832 return isize * instruction->times;
833 } else {
834 return -1; /* didn't match any instruction */
835 }
836 }
837
838 static void bad_hle_warn(const insn * ins, uint8_t hleok)
839 {
840 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
841 enum whatwarn { w_none, w_lock, w_inval } ww;
842 static const enum whatwarn warn[2][4] =
843 {
844 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
845 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
846 };
847 unsigned int n;
848
849 n = (unsigned int)rep_pfx - P_XACQUIRE;
850 if (n > 1)
851 return; /* Not XACQUIRE/XRELEASE */
852
853 ww = warn[n][hleok];
854 if (!is_class(MEMORY, ins->oprs[0].type))
855 ww = w_inval; /* HLE requires operand 0 to be memory */
856
857 switch (ww) {
858 case w_none:
859 break;
860
861 case w_lock:
862 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
863 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
864 "%s with this instruction requires lock",
865 prefix_name(rep_pfx));
866 }
867 break;
868
869 case w_inval:
870 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
871 "%s invalid with this instruction",
872 prefix_name(rep_pfx));
873 break;
874 }
875 }
876
877 /* Common construct */
878 #define case3(x) case (x): case (x)+1: case (x)+2
879 #define case4(x) case3(x): case (x)+3
880
881 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
882 insn * ins, const struct itemplate *temp)
883 {
884 const uint8_t *codes = temp->code;
885 int64_t length = 0;
886 uint8_t c;
887 int rex_mask = ~0;
888 int op1, op2;
889 struct operand *opx;
890 uint8_t opex = 0;
891 enum ea_type eat;
892 uint8_t hleok = 0;
893 bool lockcheck = true;
894 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
895
896 ins->rex = 0; /* Ensure REX is reset */
897 eat = EA_SCALAR; /* Expect a scalar EA */
898 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
899
900 if (ins->prefixes[PPS_OSIZE] == P_O64)
901 ins->rex |= REX_W;
902
903 (void)segment; /* Don't warn that this parameter is unused */
904 (void)offset; /* Don't warn that this parameter is unused */
905
906 while (*codes) {
907 c = *codes++;
908 op1 = (c & 3) + ((opex & 1) << 2);
909 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
910 opx = &ins->oprs[op1];
911 opex = 0; /* For the next iteration */
912
913 switch (c) {
914 case4(01):
915 codes += c, length += c;
916 break;
917
918 case3(05):
919 opex = c;
920 break;
921
922 case4(010):
923 ins->rex |=
924 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
925 codes++, length++;
926 break;
927
928 case4(014):
929 /* this is an index reg of MIB operand */
930 mib_index = opx->basereg;
931 break;
932
933 case4(020):
934 case4(024):
935 length++;
936 break;
937
938 case4(030):
939 length += 2;
940 break;
941
942 case4(034):
943 if (opx->type & (BITS16 | BITS32 | BITS64))
944 length += (opx->type & BITS16) ? 2 : 4;
945 else
946 length += (bits == 16) ? 2 : 4;
947 break;
948
949 case4(040):
950 length += 4;
951 break;
952
953 case4(044):
954 length += ins->addr_size >> 3;
955 break;
956
957 case4(050):
958 length++;
959 break;
960
961 case4(054):
962 length += 8; /* MOV reg64/imm */
963 break;
964
965 case4(060):
966 length += 2;
967 break;
968
969 case4(064):
970 if (opx->type & (BITS16 | BITS32 | BITS64))
971 length += (opx->type & BITS16) ? 2 : 4;
972 else
973 length += (bits == 16) ? 2 : 4;
974 break;
975
976 case4(070):
977 length += 4;
978 break;
979
980 case4(074):
981 length += 2;
982 break;
983
984 case 0172:
985 case 0173:
986 codes++;
987 length++;
988 break;
989
990 case4(0174):
991 length++;
992 break;
993
994 case4(0240):
995 ins->rex |= REX_EV;
996 ins->vexreg = regval(opx);
997 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
998 ins->vex_cm = *codes++;
999 ins->vex_wlp = *codes++;
1000 ins->evex_tuple = (*codes++ - 0300);
1001 break;
1002
1003 case 0250:
1004 ins->rex |= REX_EV;
1005 ins->vexreg = 0;
1006 ins->vex_cm = *codes++;
1007 ins->vex_wlp = *codes++;
1008 ins->evex_tuple = (*codes++ - 0300);
1009 break;
1010
1011 case4(0254):
1012 length += 4;
1013 break;
1014
1015 case4(0260):
1016 ins->rex |= REX_V;
1017 ins->vexreg = regval(opx);
1018 ins->vex_cm = *codes++;
1019 ins->vex_wlp = *codes++;
1020 break;
1021
1022 case 0270:
1023 ins->rex |= REX_V;
1024 ins->vexreg = 0;
1025 ins->vex_cm = *codes++;
1026 ins->vex_wlp = *codes++;
1027 break;
1028
1029 case3(0271):
1030 hleok = c & 3;
1031 break;
1032
1033 case4(0274):
1034 length++;
1035 break;
1036
1037 case4(0300):
1038 break;
1039
1040 case 0310:
1041 if (bits == 64)
1042 return -1;
1043 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1044 break;
1045
1046 case 0311:
1047 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1048 break;
1049
1050 case 0312:
1051 break;
1052
1053 case 0313:
1054 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1055 has_prefix(ins, PPS_ASIZE, P_A32))
1056 return -1;
1057 break;
1058
1059 case4(0314):
1060 break;
1061
1062 case 0320:
1063 {
1064 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1065 if (pfx == P_O16)
1066 break;
1067 if (pfx != P_none)
1068 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1069 else
1070 ins->prefixes[PPS_OSIZE] = P_O16;
1071 break;
1072 }
1073
1074 case 0321:
1075 {
1076 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1077 if (pfx == P_O32)
1078 break;
1079 if (pfx != P_none)
1080 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1081 else
1082 ins->prefixes[PPS_OSIZE] = P_O32;
1083 break;
1084 }
1085
1086 case 0322:
1087 break;
1088
1089 case 0323:
1090 rex_mask &= ~REX_W;
1091 break;
1092
1093 case 0324:
1094 ins->rex |= REX_W;
1095 break;
1096
1097 case 0325:
1098 ins->rex |= REX_NH;
1099 break;
1100
1101 case 0326:
1102 break;
1103
1104 case 0330:
1105 codes++, length++;
1106 break;
1107
1108 case 0331:
1109 break;
1110
1111 case 0332:
1112 case 0333:
1113 length++;
1114 break;
1115
1116 case 0334:
1117 ins->rex |= REX_L;
1118 break;
1119
1120 case 0335:
1121 break;
1122
1123 case 0336:
1124 if (!ins->prefixes[PPS_REP])
1125 ins->prefixes[PPS_REP] = P_REP;
1126 break;
1127
1128 case 0337:
1129 if (!ins->prefixes[PPS_REP])
1130 ins->prefixes[PPS_REP] = P_REPNE;
1131 break;
1132
1133 case 0340:
1134 if (ins->oprs[0].segment != NO_SEG)
1135 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1136 " quantity of BSS space");
1137 else
1138 length += ins->oprs[0].offset;
1139 break;
1140
1141 case 0341:
1142 if (!ins->prefixes[PPS_WAIT])
1143 ins->prefixes[PPS_WAIT] = P_WAIT;
1144 break;
1145
1146 case 0360:
1147 break;
1148
1149 case 0361:
1150 length++;
1151 break;
1152
1153 case 0364:
1154 case 0365:
1155 break;
1156
1157 case 0366:
1158 case 0367:
1159 length++;
1160 break;
1161
1162 case 0370:
1163 case 0371:
1164 break;
1165
1166 case 0373:
1167 length++;
1168 break;
1169
1170 case 0374:
1171 eat = EA_XMMVSIB;
1172 break;
1173
1174 case 0375:
1175 eat = EA_YMMVSIB;
1176 break;
1177
1178 case 0376:
1179 eat = EA_ZMMVSIB;
1180 break;
1181
1182 case4(0100):
1183 case4(0110):
1184 case4(0120):
1185 case4(0130):
1186 case4(0200):
1187 case4(0204):
1188 case4(0210):
1189 case4(0214):
1190 case4(0220):
1191 case4(0224):
1192 case4(0230):
1193 case4(0234):
1194 {
1195 ea ea_data;
1196 int rfield;
1197 opflags_t rflags;
1198 struct operand *opy = &ins->oprs[op2];
1199 struct operand *op_er_sae;
1200
1201 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1202
1203 if (c <= 0177) {
1204 /* pick rfield from operand b (opx) */
1205 rflags = regflag(opx);
1206 rfield = nasm_regvals[opx->basereg];
1207 } else {
1208 rflags = 0;
1209 rfield = c & 7;
1210 }
1211
1212 /* EVEX.b1 : evex_brerop contains the operand position */
1213 op_er_sae = (ins->evex_brerop >= 0 ?
1214 &ins->oprs[ins->evex_brerop] : NULL);
1215
1216 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1217 /* set EVEX.b */
1218 ins->evex_p[2] |= EVEX_P2B;
1219 if (op_er_sae->decoflags & ER) {
1220 /* set EVEX.RC (rounding control) */
1221 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1222 & EVEX_P2RC;
1223 }
1224 } else {
1225 /* set EVEX.L'L (vector length) */
1226 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1227 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1228 if (opy->decoflags & BRDCAST_MASK) {
1229 /* set EVEX.b */
1230 ins->evex_p[2] |= EVEX_P2B;
1231 }
1232 }
1233
1234 if (itemp_has(temp, IF_MIB)) {
1235 opy->eaflags |= EAF_MIB;
1236 /*
1237 * if a separate form of MIB (ICC style) is used,
1238 * the index reg info is merged into mem operand
1239 */
1240 if (mib_index != R_none) {
1241 opy->indexreg = mib_index;
1242 opy->scale = 1;
1243 opy->hintbase = mib_index;
1244 opy->hinttype = EAH_NOTBASE;
1245 }
1246 }
1247
1248 if (process_ea(opy, &ea_data, bits,
1249 rfield, rflags, ins) != eat) {
1250 errfunc(ERR_NONFATAL, "invalid effective address");
1251 return -1;
1252 } else {
1253 ins->rex |= ea_data.rex;
1254 length += ea_data.size;
1255 }
1256 }
1257 break;
1258
1259 default:
1260 errfunc(ERR_PANIC, "internal instruction table corrupt"
1261 ": instruction code \\%o (0x%02X) given", c, c);
1262 break;
1263 }
1264 }
1265
1266 ins->rex &= rex_mask;
1267
1268 if (ins->rex & REX_NH) {
1269 if (ins->rex & REX_H) {
1270 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1271 return -1;
1272 }
1273 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1274 }
1275
1276 switch (ins->prefixes[PPS_VEX]) {
1277 case P_EVEX:
1278 if (!(ins->rex & REX_EV))
1279 return -1;
1280 break;
1281 case P_VEX3:
1282 case P_VEX2:
1283 if (!(ins->rex & REX_V))
1284 return -1;
1285 break;
1286 default:
1287 break;
1288 }
1289
1290 if (ins->rex & (REX_V | REX_EV)) {
1291 int bad32 = REX_R|REX_W|REX_X|REX_B;
1292
1293 if (ins->rex & REX_H) {
1294 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1295 return -1;
1296 }
1297 switch (ins->vex_wlp & 060) {
1298 case 000:
1299 case 040:
1300 ins->rex &= ~REX_W;
1301 break;
1302 case 020:
1303 ins->rex |= REX_W;
1304 bad32 &= ~REX_W;
1305 break;
1306 case 060:
1307 /* Follow REX_W */
1308 break;
1309 }
1310
1311 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1312 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1313 return -1;
1314 } else if (!(ins->rex & REX_EV) &&
1315 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1316 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1317 return -1;
1318 }
1319 if (ins->rex & REX_EV)
1320 length += 4;
1321 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1322 ins->prefixes[PPS_VEX] == P_VEX3)
1323 length += 3;
1324 else
1325 length += 2;
1326 } else if (ins->rex & REX_REAL) {
1327 if (ins->rex & REX_H) {
1328 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1329 return -1;
1330 } else if (bits == 64) {
1331 length++;
1332 } else if ((ins->rex & REX_L) &&
1333 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1334 iflag_ffs(&cpu) >= IF_X86_64) {
1335 /* LOCK-as-REX.R */
1336 assert_no_prefix(ins, PPS_LOCK);
1337 lockcheck = false; /* Already errored, no need for warning */
1338 length++;
1339 } else {
1340 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1341 return -1;
1342 }
1343 }
1344
1345 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1346 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1347 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1348 "instruction is not lockable");
1349 }
1350
1351 bad_hle_warn(ins, hleok);
1352
1353 /*
1354 * when BND prefix is set by DEFAULT directive,
1355 * BND prefix is added to every appropriate instruction line
1356 * unless it is overridden by NOBND prefix.
1357 */
1358 if (globalbnd &&
1359 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1360 ins->prefixes[PPS_REP] = P_BND;
1361
1362 return length;
1363 }
1364
1365 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1366 {
1367 if (bits == 64) {
1368 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1369 ins->rex = (ins->rex & REX_REAL) | REX_P;
1370 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1371 ins->rex = 0;
1372 return 1;
1373 }
1374 }
1375
1376 return 0;
1377 }
1378
1379 static void gencode(int32_t segment, int64_t offset, int bits,
1380 insn * ins, const struct itemplate *temp,
1381 int64_t insn_end)
1382 {
1383 uint8_t c;
1384 uint8_t bytes[4];
1385 int64_t size;
1386 int64_t data;
1387 int op1, op2;
1388 struct operand *opx;
1389 const uint8_t *codes = temp->code;
1390 uint8_t opex = 0;
1391 enum ea_type eat = EA_SCALAR;
1392
1393 while (*codes) {
1394 c = *codes++;
1395 op1 = (c & 3) + ((opex & 1) << 2);
1396 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1397 opx = &ins->oprs[op1];
1398 opex = 0; /* For the next iteration */
1399
1400 switch (c) {
1401 case 01:
1402 case 02:
1403 case 03:
1404 case 04:
1405 offset += emit_rex(ins, segment, offset, bits);
1406 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1407 codes += c;
1408 offset += c;
1409 break;
1410
1411 case 05:
1412 case 06:
1413 case 07:
1414 opex = c;
1415 break;
1416
1417 case4(010):
1418 offset += emit_rex(ins, segment, offset, bits);
1419 bytes[0] = *codes++ + (regval(opx) & 7);
1420 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1421 offset += 1;
1422 break;
1423
1424 case4(014):
1425 break;
1426
1427 case4(020):
1428 if (opx->offset < -256 || opx->offset > 255) {
1429 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1430 "byte value exceeds bounds");
1431 }
1432 out_imm8(offset, segment, opx);
1433 offset += 1;
1434 break;
1435
1436 case4(024):
1437 if (opx->offset < 0 || opx->offset > 255)
1438 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1439 "unsigned byte value exceeds bounds");
1440 out_imm8(offset, segment, opx);
1441 offset += 1;
1442 break;
1443
1444 case4(030):
1445 warn_overflow_opd(opx, 2);
1446 data = opx->offset;
1447 out(offset, segment, &data, OUT_ADDRESS, 2,
1448 opx->segment, opx->wrt);
1449 offset += 2;
1450 break;
1451
1452 case4(034):
1453 if (opx->type & (BITS16 | BITS32))
1454 size = (opx->type & BITS16) ? 2 : 4;
1455 else
1456 size = (bits == 16) ? 2 : 4;
1457 warn_overflow_opd(opx, size);
1458 data = opx->offset;
1459 out(offset, segment, &data, OUT_ADDRESS, size,
1460 opx->segment, opx->wrt);
1461 offset += size;
1462 break;
1463
1464 case4(040):
1465 warn_overflow_opd(opx, 4);
1466 data = opx->offset;
1467 out(offset, segment, &data, OUT_ADDRESS, 4,
1468 opx->segment, opx->wrt);
1469 offset += 4;
1470 break;
1471
1472 case4(044):
1473 data = opx->offset;
1474 size = ins->addr_size >> 3;
1475 warn_overflow_opd(opx, size);
1476 out(offset, segment, &data, OUT_ADDRESS, size,
1477 opx->segment, opx->wrt);
1478 offset += size;
1479 break;
1480
1481 case4(050):
1482 if (opx->segment != segment) {
1483 data = opx->offset;
1484 out(offset, segment, &data,
1485 OUT_REL1ADR, insn_end - offset,
1486 opx->segment, opx->wrt);
1487 } else {
1488 data = opx->offset - insn_end;
1489 if (data > 127 || data < -128)
1490 errfunc(ERR_NONFATAL, "short jump is out of range");
1491 out(offset, segment, &data,
1492 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1493 }
1494 offset += 1;
1495 break;
1496
1497 case4(054):
1498 data = (int64_t)opx->offset;
1499 out(offset, segment, &data, OUT_ADDRESS, 8,
1500 opx->segment, opx->wrt);
1501 offset += 8;
1502 break;
1503
1504 case4(060):
1505 if (opx->segment != segment) {
1506 data = opx->offset;
1507 out(offset, segment, &data,
1508 OUT_REL2ADR, insn_end - offset,
1509 opx->segment, opx->wrt);
1510 } else {
1511 data = opx->offset - insn_end;
1512 out(offset, segment, &data,
1513 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1514 }
1515 offset += 2;
1516 break;
1517
1518 case4(064):
1519 if (opx->type & (BITS16 | BITS32 | BITS64))
1520 size = (opx->type & BITS16) ? 2 : 4;
1521 else
1522 size = (bits == 16) ? 2 : 4;
1523 if (opx->segment != segment) {
1524 data = opx->offset;
1525 out(offset, segment, &data,
1526 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1527 insn_end - offset, opx->segment, opx->wrt);
1528 } else {
1529 data = opx->offset - insn_end;
1530 out(offset, segment, &data,
1531 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1532 }
1533 offset += size;
1534 break;
1535
1536 case4(070):
1537 if (opx->segment != segment) {
1538 data = opx->offset;
1539 out(offset, segment, &data,
1540 OUT_REL4ADR, insn_end - offset,
1541 opx->segment, opx->wrt);
1542 } else {
1543 data = opx->offset - insn_end;
1544 out(offset, segment, &data,
1545 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1546 }
1547 offset += 4;
1548 break;
1549
1550 case4(074):
1551 if (opx->segment == NO_SEG)
1552 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1553 " relocatable");
1554 data = 0;
1555 out(offset, segment, &data, OUT_ADDRESS, 2,
1556 outfmt->segbase(1 + opx->segment),
1557 opx->wrt);
1558 offset += 2;
1559 break;
1560
1561 case 0172:
1562 c = *codes++;
1563 opx = &ins->oprs[c >> 3];
1564 bytes[0] = nasm_regvals[opx->basereg] << 4;
1565 opx = &ins->oprs[c & 7];
1566 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1567 errfunc(ERR_NONFATAL,
1568 "non-absolute expression not permitted as argument %d",
1569 c & 7);
1570 } else {
1571 if (opx->offset & ~15) {
1572 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1573 "four-bit argument exceeds bounds");
1574 }
1575 bytes[0] |= opx->offset & 15;
1576 }
1577 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1578 offset++;
1579 break;
1580
1581 case 0173:
1582 c = *codes++;
1583 opx = &ins->oprs[c >> 4];
1584 bytes[0] = nasm_regvals[opx->basereg] << 4;
1585 bytes[0] |= c & 15;
1586 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1587 offset++;
1588 break;
1589
1590 case4(0174):
1591 bytes[0] = nasm_regvals[opx->basereg] << 4;
1592 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1593 offset++;
1594 break;
1595
1596 case4(0254):
1597 data = opx->offset;
1598 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1599 (int32_t)data != (int64_t)data) {
1600 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1601 "signed dword immediate exceeds bounds");
1602 }
1603 out(offset, segment, &data, OUT_ADDRESS, 4,
1604 opx->segment, opx->wrt);
1605 offset += 4;
1606 break;
1607
1608 case4(0240):
1609 case 0250:
1610 codes += 3;
1611 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1612 EVEX_P2Z | EVEX_P2AAA, 2);
1613 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1614 bytes[0] = 0x62;
1615 /* EVEX.X can be set by either REX or EVEX for different reasons */
1616 bytes[1] = ((((ins->rex & 7) << 5) |
1617 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1618 (ins->vex_cm & 3);
1619 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1620 ((~ins->vexreg & 15) << 3) |
1621 (1 << 2) | (ins->vex_wlp & 3);
1622 bytes[3] = ins->evex_p[2];
1623 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1624 offset += 4;
1625 break;
1626
1627 case4(0260):
1628 case 0270:
1629 codes += 2;
1630 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1631 ins->prefixes[PPS_VEX] == P_VEX3) {
1632 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1633 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1634 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1635 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1636 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1637 offset += 3;
1638 } else {
1639 bytes[0] = 0xc5;
1640 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1641 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1642 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1643 offset += 2;
1644 }
1645 break;
1646
1647 case 0271:
1648 case 0272:
1649 case 0273:
1650 break;
1651
1652 case4(0274):
1653 {
1654 uint64_t uv, um;
1655 int s;
1656
1657 if (ins->rex & REX_W)
1658 s = 64;
1659 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1660 s = 16;
1661 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1662 s = 32;
1663 else
1664 s = bits;
1665
1666 um = (uint64_t)2 << (s-1);
1667 uv = opx->offset;
1668
1669 if (uv > 127 && uv < (uint64_t)-128 &&
1670 (uv < um-128 || uv > um-1)) {
1671 /* If this wasn't explicitly byte-sized, warn as though we
1672 * had fallen through to the imm16/32/64 case.
1673 */
1674 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1675 "%s value exceeds bounds",
1676 (opx->type & BITS8) ? "signed byte" :
1677 s == 16 ? "word" :
1678 s == 32 ? "dword" :
1679 "signed dword");
1680 }
1681 if (opx->segment != NO_SEG) {
1682 data = uv;
1683 out(offset, segment, &data, OUT_ADDRESS, 1,
1684 opx->segment, opx->wrt);
1685 } else {
1686 bytes[0] = uv;
1687 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1688 NO_SEG);
1689 }
1690 offset += 1;
1691 break;
1692 }
1693
1694 case4(0300):
1695 break;
1696
1697 case 0310:
1698 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1699 *bytes = 0x67;
1700 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1701 offset += 1;
1702 } else
1703 offset += 0;
1704 break;
1705
1706 case 0311:
1707 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1708 *bytes = 0x67;
1709 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1710 offset += 1;
1711 } else
1712 offset += 0;
1713 break;
1714
1715 case 0312:
1716 break;
1717
1718 case 0313:
1719 ins->rex = 0;
1720 break;
1721
1722 case4(0314):
1723 break;
1724
1725 case 0320:
1726 case 0321:
1727 break;
1728
1729 case 0322:
1730 case 0323:
1731 break;
1732
1733 case 0324:
1734 ins->rex |= REX_W;
1735 break;
1736
1737 case 0325:
1738 break;
1739
1740 case 0326:
1741 break;
1742
1743 case 0330:
1744 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1745 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1746 offset += 1;
1747 break;
1748
1749 case 0331:
1750 break;
1751
1752 case 0332:
1753 case 0333:
1754 *bytes = c - 0332 + 0xF2;
1755 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1756 offset += 1;
1757 break;
1758
1759 case 0334:
1760 if (ins->rex & REX_R) {
1761 *bytes = 0xF0;
1762 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1763 offset += 1;
1764 }
1765 ins->rex &= ~(REX_L|REX_R);
1766 break;
1767
1768 case 0335:
1769 break;
1770
1771 case 0336:
1772 case 0337:
1773 break;
1774
1775 case 0340:
1776 if (ins->oprs[0].segment != NO_SEG)
1777 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1778 else {
1779 int64_t size = ins->oprs[0].offset;
1780 if (size > 0)
1781 out(offset, segment, NULL,
1782 OUT_RESERVE, size, NO_SEG, NO_SEG);
1783 offset += size;
1784 }
1785 break;
1786
1787 case 0341:
1788 break;
1789
1790 case 0360:
1791 break;
1792
1793 case 0361:
1794 bytes[0] = 0x66;
1795 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1796 offset += 1;
1797 break;
1798
1799 case 0364:
1800 case 0365:
1801 break;
1802
1803 case 0366:
1804 case 0367:
1805 *bytes = c - 0366 + 0x66;
1806 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1807 offset += 1;
1808 break;
1809
1810 case3(0370):
1811 break;
1812
1813 case 0373:
1814 *bytes = bits == 16 ? 3 : 5;
1815 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1816 offset += 1;
1817 break;
1818
1819 case 0374:
1820 eat = EA_XMMVSIB;
1821 break;
1822
1823 case 0375:
1824 eat = EA_YMMVSIB;
1825 break;
1826
1827 case 0376:
1828 eat = EA_ZMMVSIB;
1829 break;
1830
1831 case4(0100):
1832 case4(0110):
1833 case4(0120):
1834 case4(0130):
1835 case4(0200):
1836 case4(0204):
1837 case4(0210):
1838 case4(0214):
1839 case4(0220):
1840 case4(0224):
1841 case4(0230):
1842 case4(0234):
1843 {
1844 ea ea_data;
1845 int rfield;
1846 opflags_t rflags;
1847 uint8_t *p;
1848 int32_t s;
1849 struct operand *opy = &ins->oprs[op2];
1850
1851 if (c <= 0177) {
1852 /* pick rfield from operand b (opx) */
1853 rflags = regflag(opx);
1854 rfield = nasm_regvals[opx->basereg];
1855 } else {
1856 /* rfield is constant */
1857 rflags = 0;
1858 rfield = c & 7;
1859 }
1860
1861 if (process_ea(opy, &ea_data, bits,
1862 rfield, rflags, ins) != eat)
1863 errfunc(ERR_NONFATAL, "invalid effective address");
1864
1865 p = bytes;
1866 *p++ = ea_data.modrm;
1867 if (ea_data.sib_present)
1868 *p++ = ea_data.sib;
1869
1870 s = p - bytes;
1871 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1872
1873 /*
1874 * Make sure the address gets the right offset in case
1875 * the line breaks in the .lst file (BR 1197827)
1876 */
1877 offset += s;
1878 s = 0;
1879
1880 switch (ea_data.bytes) {
1881 case 0:
1882 break;
1883 case 1:
1884 case 2:
1885 case 4:
1886 case 8:
1887 /* use compressed displacement, if available */
1888 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1889 s += ea_data.bytes;
1890 if (ea_data.rip) {
1891 if (opy->segment == segment) {
1892 data -= insn_end;
1893 if (overflow_signed(data, ea_data.bytes))
1894 warn_overflow(ERR_PASS2, ea_data.bytes);
1895 out(offset, segment, &data, OUT_ADDRESS,
1896 ea_data.bytes, NO_SEG, NO_SEG);
1897 } else {
1898 /* overflow check in output/linker? */
1899 out(offset, segment, &data, OUT_REL4ADR,
1900 insn_end - offset, opy->segment, opy->wrt);
1901 }
1902 } else {
1903 if (overflow_general(data, ins->addr_size >> 3) ||
1904 signed_bits(data, ins->addr_size) !=
1905 signed_bits(data, ea_data.bytes * 8))
1906 warn_overflow(ERR_PASS2, ea_data.bytes);
1907
1908 out(offset, segment, &data, OUT_ADDRESS,
1909 ea_data.bytes, opy->segment, opy->wrt);
1910 }
1911 break;
1912 default:
1913 /* Impossible! */
1914 errfunc(ERR_PANIC,
1915 "Invalid amount of bytes (%d) for offset?!",
1916 ea_data.bytes);
1917 break;
1918 }
1919 offset += s;
1920 }
1921 break;
1922
1923 default:
1924 errfunc(ERR_PANIC, "internal instruction table corrupt"
1925 ": instruction code \\%o (0x%02X) given", c, c);
1926 break;
1927 }
1928 }
1929 }
1930
1931 static opflags_t regflag(const operand * o)
1932 {
1933 if (!is_register(o->basereg))
1934 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1935 return nasm_reg_flags[o->basereg];
1936 }
1937
1938 static int32_t regval(const operand * o)
1939 {
1940 if (!is_register(o->basereg))
1941 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1942 return nasm_regvals[o->basereg];
1943 }
1944
1945 static int op_rexflags(const operand * o, int mask)
1946 {
1947 opflags_t flags;
1948 int val;
1949
1950 if (!is_register(o->basereg))
1951 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1952
1953 flags = nasm_reg_flags[o->basereg];
1954 val = nasm_regvals[o->basereg];
1955
1956 return rexflags(val, flags, mask);
1957 }
1958
1959 static int rexflags(int val, opflags_t flags, int mask)
1960 {
1961 int rex = 0;
1962
1963 if (val >= 0 && (val & 8))
1964 rex |= REX_B|REX_X|REX_R;
1965 if (flags & BITS64)
1966 rex |= REX_W;
1967 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1968 rex |= REX_H;
1969 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1970 rex |= REX_P;
1971
1972 return rex & mask;
1973 }
1974
1975 static int evexflags(int val, decoflags_t deco,
1976 int mask, uint8_t byte)
1977 {
1978 int evex = 0;
1979
1980 switch (byte) {
1981 case 0:
1982 if (val >= 0 && (val & 16))
1983 evex |= (EVEX_P0RP | EVEX_P0X);
1984 break;
1985 case 2:
1986 if (val >= 0 && (val & 16))
1987 evex |= EVEX_P2VP;
1988 if (deco & Z)
1989 evex |= EVEX_P2Z;
1990 if (deco & OPMASK_MASK)
1991 evex |= deco & EVEX_P2AAA;
1992 break;
1993 }
1994 return evex & mask;
1995 }
1996
1997 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1998 {
1999 int val;
2000
2001 if (!is_register(o->basereg))
2002 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
2003
2004 val = nasm_regvals[o->basereg];
2005
2006 return evexflags(val, o->decoflags, mask, byte);
2007 }
2008
2009 static enum match_result find_match(const struct itemplate **tempp,
2010 insn *instruction,
2011 int32_t segment, int64_t offset, int bits)
2012 {
2013 const struct itemplate *temp;
2014 enum match_result m, merr;
2015 opflags_t xsizeflags[MAX_OPERANDS];
2016 bool opsizemissing = false;
2017 int8_t broadcast = instruction->evex_brerop;
2018 int i;
2019
2020 /* broadcasting uses a different data element size */
2021 for (i = 0; i < instruction->operands; i++)
2022 if (i == broadcast)
2023 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2024 else
2025 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2026
2027 merr = MERR_INVALOP;
2028
2029 for (temp = nasm_instructions[instruction->opcode];
2030 temp->opcode != I_none; temp++) {
2031 m = matches(temp, instruction, bits);
2032 if (m == MOK_JUMP) {
2033 if (jmp_match(segment, offset, bits, instruction, temp))
2034 m = MOK_GOOD;
2035 else
2036 m = MERR_INVALOP;
2037 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2038 /*
2039 * Missing operand size and a candidate for fuzzy matching...
2040 */
2041 for (i = 0; i < temp->operands; i++)
2042 if (i == broadcast)
2043 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2044 else
2045 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2046 opsizemissing = true;
2047 }
2048 if (m > merr)
2049 merr = m;
2050 if (merr == MOK_GOOD)
2051 goto done;
2052 }
2053
2054 /* No match, but see if we can get a fuzzy operand size match... */
2055 if (!opsizemissing)
2056 goto done;
2057
2058 for (i = 0; i < instruction->operands; i++) {
2059 /*
2060 * We ignore extrinsic operand sizes on registers, so we should
2061 * never try to fuzzy-match on them. This also resolves the case
2062 * when we have e.g. "xmmrm128" in two different positions.
2063 */
2064 if (is_class(REGISTER, instruction->oprs[i].type))
2065 continue;
2066
2067 /* This tests if xsizeflags[i] has more than one bit set */
2068 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2069 goto done; /* No luck */
2070
2071 if (i == broadcast) {
2072 instruction->oprs[i].decoflags |= xsizeflags[i];
2073 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2074 BITS32 : BITS64);
2075 } else {
2076 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2077 }
2078 }
2079
2080 /* Try matching again... */
2081 for (temp = nasm_instructions[instruction->opcode];
2082 temp->opcode != I_none; temp++) {
2083 m = matches(temp, instruction, bits);
2084 if (m == MOK_JUMP) {
2085 if (jmp_match(segment, offset, bits, instruction, temp))
2086 m = MOK_GOOD;
2087 else
2088 m = MERR_INVALOP;
2089 }
2090 if (m > merr)
2091 merr = m;
2092 if (merr == MOK_GOOD)
2093 goto done;
2094 }
2095
2096 done:
2097 *tempp = temp;
2098 return merr;
2099 }
2100
2101 static enum match_result matches(const struct itemplate *itemp,
2102 insn *instruction, int bits)
2103 {
2104 opflags_t size[MAX_OPERANDS], asize;
2105 bool opsizemissing = false;
2106 int i, oprs;
2107
2108 /*
2109 * Check the opcode
2110 */
2111 if (itemp->opcode != instruction->opcode)
2112 return MERR_INVALOP;
2113
2114 /*
2115 * Count the operands
2116 */
2117 if (itemp->operands != instruction->operands)
2118 return MERR_INVALOP;
2119
2120 /*
2121 * Is it legal?
2122 */
2123 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2124 return MERR_INVALOP;
2125
2126 /*
2127 * {evex} available?
2128 */
2129 switch (instruction->prefixes[PPS_VEX]) {
2130 case P_EVEX:
2131 if (!itemp_has(itemp, IF_EVEX))
2132 return MERR_ENCMISMATCH;
2133 break;
2134 case P_VEX3:
2135 case P_VEX2:
2136 if (!itemp_has(itemp, IF_VEX))
2137 return MERR_ENCMISMATCH;
2138 break;
2139 default:
2140 break;
2141 }
2142
2143 /*
2144 * Check that no spurious colons or TOs are present
2145 */
2146 for (i = 0; i < itemp->operands; i++)
2147 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2148 return MERR_INVALOP;
2149
2150 /*
2151 * Process size flags
2152 */
2153 switch (itemp_smask(itemp)) {
2154 case IF_GENBIT(IF_SB):
2155 asize = BITS8;
2156 break;
2157 case IF_GENBIT(IF_SW):
2158 asize = BITS16;
2159 break;
2160 case IF_GENBIT(IF_SD):
2161 asize = BITS32;
2162 break;
2163 case IF_GENBIT(IF_SQ):
2164 asize = BITS64;
2165 break;
2166 case IF_GENBIT(IF_SO):
2167 asize = BITS128;
2168 break;
2169 case IF_GENBIT(IF_SY):
2170 asize = BITS256;
2171 break;
2172 case IF_GENBIT(IF_SZ):
2173 asize = BITS512;
2174 break;
2175 case IF_GENBIT(IF_SIZE):
2176 switch (bits) {
2177 case 16:
2178 asize = BITS16;
2179 break;
2180 case 32:
2181 asize = BITS32;
2182 break;
2183 case 64:
2184 asize = BITS64;
2185 break;
2186 default:
2187 asize = 0;
2188 break;
2189 }
2190 break;
2191 default:
2192 asize = 0;
2193 break;
2194 }
2195
2196 if (itemp_armask(itemp)) {
2197 /* S- flags only apply to a specific operand */
2198 i = itemp_arg(itemp);
2199 memset(size, 0, sizeof size);
2200 size[i] = asize;
2201 } else {
2202 /* S- flags apply to all operands */
2203 for (i = 0; i < MAX_OPERANDS; i++)
2204 size[i] = asize;
2205 }
2206
2207 /*
2208 * Check that the operand flags all match up,
2209 * it's a bit tricky so lets be verbose:
2210 *
2211 * 1) Find out the size of operand. If instruction
2212 * doesn't have one specified -- we're trying to
2213 * guess it either from template (IF_S* flag) or
2214 * from code bits.
2215 *
2216 * 2) If template operand do not match the instruction OR
2217 * template has an operand size specified AND this size differ
2218 * from which instruction has (perhaps we got it from code bits)
2219 * we are:
2220 * a) Check that only size of instruction and operand is differ
2221 * other characteristics do match
2222 * b) Perhaps it's a register specified in instruction so
2223 * for such a case we just mark that operand as "size
2224 * missing" and this will turn on fuzzy operand size
2225 * logic facility (handled by a caller)
2226 */
2227 for (i = 0; i < itemp->operands; i++) {
2228 opflags_t type = instruction->oprs[i].type;
2229 decoflags_t deco = instruction->oprs[i].decoflags;
2230 bool is_broadcast = deco & BRDCAST_MASK;
2231 uint8_t brcast_num = 0;
2232 opflags_t template_opsize, insn_opsize;
2233
2234 if (!(type & SIZE_MASK))
2235 type |= size[i];
2236
2237 insn_opsize = type & SIZE_MASK;
2238 if (!is_broadcast) {
2239 template_opsize = itemp->opd[i] & SIZE_MASK;
2240 } else {
2241 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2242 /*
2243 * when broadcasting, the element size depends on
2244 * the instruction type. decorator flag should match.
2245 */
2246
2247 if (deco_brsize) {
2248 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2249 /* calculate the proper number : {1to<brcast_num>} */
2250 brcast_num = (itemp->opd[i] & SIZE_MASK) / BITS128 *
2251 BITS64 / template_opsize * 2;
2252 } else {
2253 template_opsize = 0;
2254 }
2255 }
2256
2257 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2258 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2259 return MERR_INVALOP;
2260 } else if (template_opsize) {
2261 if (template_opsize != insn_opsize) {
2262 if (insn_opsize) {
2263 return MERR_INVALOP;
2264 } else if (!is_class(REGISTER, type)) {
2265 /*
2266 * Note: we don't honor extrinsic operand sizes for registers,
2267 * so "missing operand size" for a register should be
2268 * considered a wildcard match rather than an error.
2269 */
2270 opsizemissing = true;
2271 }
2272 } else if (is_broadcast &&
2273 (brcast_num !=
2274 (8U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2275 /*
2276 * broadcasting opsize matches but the number of repeated memory
2277 * element does not match.
2278 * if 64b double precision float is broadcasted to zmm (512b),
2279 * broadcasting decorator must be {1to8}.
2280 */
2281 return MERR_BRNUMMISMATCH;
2282 }
2283 }
2284 }
2285
2286 if (opsizemissing)
2287 return MERR_OPSIZEMISSING;
2288
2289 /*
2290 * Check operand sizes
2291 */
2292 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2293 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2294 for (i = 0; i < oprs; i++) {
2295 asize = itemp->opd[i] & SIZE_MASK;
2296 if (asize) {
2297 for (i = 0; i < oprs; i++)
2298 size[i] = asize;
2299 break;
2300 }
2301 }
2302 } else {
2303 oprs = itemp->operands;
2304 }
2305
2306 for (i = 0; i < itemp->operands; i++) {
2307 if (!(itemp->opd[i] & SIZE_MASK) &&
2308 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2309 return MERR_OPSIZEMISMATCH;
2310 }
2311
2312 /*
2313 * Check template is okay at the set cpu level
2314 */
2315 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2316 return MERR_BADCPU;
2317
2318 /*
2319 * Verify the appropriate long mode flag.
2320 */
2321 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2322 return MERR_BADMODE;
2323
2324 /*
2325 * If we have a HLE prefix, look for the NOHLE flag
2326 */
2327 if (itemp_has(itemp, IF_NOHLE) &&
2328 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2329 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2330 return MERR_BADHLE;
2331
2332 /*
2333 * Check if special handling needed for Jumps
2334 */
2335 if ((itemp->code[0] & ~1) == 0370)
2336 return MOK_JUMP;
2337
2338 /*
2339 * Check if BND prefix is allowed.
2340 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2341 */
2342 if (!itemp_has(itemp, IF_BND) &&
2343 (has_prefix(instruction, PPS_REP, P_BND) ||
2344 has_prefix(instruction, PPS_REP, P_NOBND)))
2345 return MERR_BADBND;
2346 else if (itemp_has(itemp, IF_BND) &&
2347 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2348 has_prefix(instruction, PPS_REP, P_REPNZ)))
2349 return MERR_BADREPNE;
2350
2351 return MOK_GOOD;
2352 }
2353
2354 /*
2355 * Check if ModR/M.mod should/can be 01.
2356 * - EAF_BYTEOFFS is set
2357 * - offset can fit in a byte when EVEX is not used
2358 * - offset can be compressed when EVEX is used
2359 */
2360 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2361 (o >= -128 && o <= 127 && \
2362 seg == NO_SEG && !forw_ref && \
2363 !(input->eaflags & EAF_WORDOFFS) && \
2364 !(ins->rex & REX_EV)) || \
2365 (ins->rex & REX_EV && \
2366 is_disp8n(input, ins, &output->disp8)))
2367
2368 static enum ea_type process_ea(operand *input, ea *output, int bits,
2369 int rfield, opflags_t rflags, insn *ins)
2370 {
2371 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2372 int addrbits = ins->addr_size;
2373 int eaflags = input->eaflags;
2374
2375 output->type = EA_SCALAR;
2376 output->rip = false;
2377 output->disp8 = 0;
2378
2379 /* REX flags for the rfield operand */
2380 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2381 /* EVEX.R' flag for the REG operand */
2382 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2383
2384 if (is_class(REGISTER, input->type)) {
2385 /*
2386 * It's a direct register.
2387 */
2388 if (!is_register(input->basereg))
2389 goto err;
2390
2391 if (!is_reg_class(REG_EA, input->basereg))
2392 goto err;
2393
2394 /* broadcasting is not available with a direct register operand. */
2395 if (input->decoflags & BRDCAST_MASK) {
2396 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2397 goto err;
2398 }
2399
2400 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2401 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2402 output->sib_present = false; /* no SIB necessary */
2403 output->bytes = 0; /* no offset necessary either */
2404 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2405 } else {
2406 /*
2407 * It's a memory reference.
2408 */
2409
2410 /* Embedded rounding or SAE is not available with a mem ref operand. */
2411 if (input->decoflags & (ER | SAE)) {
2412 nasm_error(ERR_NONFATAL,
2413 "Embedded rounding is available only with reg-reg op.");
2414 return -1;
2415 }
2416
2417 if (input->basereg == -1 &&
2418 (input->indexreg == -1 || input->scale == 0)) {
2419 /*
2420 * It's a pure offset.
2421 */
2422 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2423 input->segment == NO_SEG) {
2424 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2425 input->type &= ~IP_REL;
2426 input->type |= MEMORY;
2427 }
2428
2429 if (bits == 64 &&
2430 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2431 nasm_error(ERR_NONFATAL, "RIP-relative addressing is prohibited for mib.");
2432 return -1;
2433 }
2434
2435 if (eaflags & EAF_BYTEOFFS ||
2436 (eaflags & EAF_WORDOFFS &&
2437 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2438 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2439 }
2440
2441 if (bits == 64 && (~input->type & IP_REL)) {
2442 output->sib_present = true;
2443 output->sib = GEN_SIB(0, 4, 5);
2444 output->bytes = 4;
2445 output->modrm = GEN_MODRM(0, rfield, 4);
2446 output->rip = false;
2447 } else {
2448 output->sib_present = false;
2449 output->bytes = (addrbits != 16 ? 4 : 2);
2450 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2451 output->rip = bits == 64;
2452 }
2453 } else {
2454 /*
2455 * It's an indirection.
2456 */
2457 int i = input->indexreg, b = input->basereg, s = input->scale;
2458 int32_t seg = input->segment;
2459 int hb = input->hintbase, ht = input->hinttype;
2460 int t, it, bt; /* register numbers */
2461 opflags_t x, ix, bx; /* register flags */
2462
2463 if (s == 0)
2464 i = -1; /* make this easy, at least */
2465
2466 if (is_register(i)) {
2467 it = nasm_regvals[i];
2468 ix = nasm_reg_flags[i];
2469 } else {
2470 it = -1;
2471 ix = 0;
2472 }
2473
2474 if (is_register(b)) {
2475 bt = nasm_regvals[b];
2476 bx = nasm_reg_flags[b];
2477 } else {
2478 bt = -1;
2479 bx = 0;
2480 }
2481
2482 /* if either one are a vector register... */
2483 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2484 opflags_t sok = BITS32 | BITS64;
2485 int32_t o = input->offset;
2486 int mod, scale, index, base;
2487
2488 /*
2489 * For a vector SIB, one has to be a vector and the other,
2490 * if present, a GPR. The vector must be the index operand.
2491 */
2492 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2493 if (s == 0)
2494 s = 1;
2495 else if (s != 1)
2496 goto err;
2497
2498 t = bt, bt = it, it = t;
2499 x = bx, bx = ix, ix = x;
2500 }
2501
2502 if (bt != -1) {
2503 if (REG_GPR & ~bx)
2504 goto err;
2505 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2506 sok &= bx;
2507 else
2508 goto err;
2509 }
2510
2511 /*
2512 * While we're here, ensure the user didn't specify
2513 * WORD or QWORD
2514 */
2515 if (input->disp_size == 16 || input->disp_size == 64)
2516 goto err;
2517
2518 if (addrbits == 16 ||
2519 (addrbits == 32 && !(sok & BITS32)) ||
2520 (addrbits == 64 && !(sok & BITS64)))
2521 goto err;
2522
2523 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2524 : ((ix & YMMREG & ~REG_EA)
2525 ? EA_YMMVSIB : EA_XMMVSIB));
2526
2527 output->rex |= rexflags(it, ix, REX_X);
2528 output->rex |= rexflags(bt, bx, REX_B);
2529 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2530
2531 index = it & 7; /* it is known to be != -1 */
2532
2533 switch (s) {
2534 case 1:
2535 scale = 0;
2536 break;
2537 case 2:
2538 scale = 1;
2539 break;
2540 case 4:
2541 scale = 2;
2542 break;
2543 case 8:
2544 scale = 3;
2545 break;
2546 default: /* then what the smeg is it? */
2547 goto err; /* panic */
2548 }
2549
2550 if (bt == -1) {
2551 base = 5;
2552 mod = 0;
2553 } else {
2554 base = (bt & 7);
2555 if (base != REG_NUM_EBP && o == 0 &&
2556 seg == NO_SEG && !forw_ref &&
2557 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2558 mod = 0;
2559 else if (IS_MOD_01())
2560 mod = 1;
2561 else
2562 mod = 2;
2563 }
2564
2565 output->sib_present = true;
2566 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2567 output->modrm = GEN_MODRM(mod, rfield, 4);
2568 output->sib = GEN_SIB(scale, index, base);
2569 } else if ((ix|bx) & (BITS32|BITS64)) {
2570 /*
2571 * it must be a 32/64-bit memory reference. Firstly we have
2572 * to check that all registers involved are type E/Rxx.
2573 */
2574 opflags_t sok = BITS32 | BITS64;
2575 int32_t o = input->offset;
2576
2577 if (it != -1) {
2578 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2579 sok &= ix;
2580 else
2581 goto err;
2582 }
2583
2584 if (bt != -1) {
2585 if (REG_GPR & ~bx)
2586 goto err; /* Invalid register */
2587 if (~sok & bx & SIZE_MASK)
2588 goto err; /* Invalid size */
2589 sok &= bx;
2590 }
2591
2592 /*
2593 * While we're here, ensure the user didn't specify
2594 * WORD or QWORD
2595 */
2596 if (input->disp_size == 16 || input->disp_size == 64)
2597 goto err;
2598
2599 if (addrbits == 16 ||
2600 (addrbits == 32 && !(sok & BITS32)) ||
2601 (addrbits == 64 && !(sok & BITS64)))
2602 goto err;
2603
2604 /* now reorganize base/index */
2605 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2606 ((hb == b && ht == EAH_NOTBASE) ||
2607 (hb == i && ht == EAH_MAKEBASE))) {
2608 /* swap if hints say so */
2609 t = bt, bt = it, it = t;
2610 x = bx, bx = ix, ix = x;
2611 }
2612
2613 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2614 /* make single reg base, unless hint */
2615 bt = it, bx = ix, it = -1, ix = 0;
2616 }
2617 if (eaflags & EAF_MIB) {
2618 /* only for mib operands */
2619 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2620 /*
2621 * make a single reg index [reg*1].
2622 * gas uses this form for an explicit index register.
2623 */
2624 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2625 }
2626 if ((ht == EAH_SUMMED) && bt == -1) {
2627 /* separate once summed index into [base, index] */
2628 bt = it, bx = ix, s--;
2629 }
2630 } else {
2631 if (((s == 2 && it != REG_NUM_ESP &&
2632 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2633 s == 3 || s == 5 || s == 9) && bt == -1) {
2634 /* convert 3*EAX to EAX+2*EAX */
2635 bt = it, bx = ix, s--;
2636 }
2637 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2638 (eaflags & EAF_TIMESTWO) &&
2639 (hb == b && ht == EAH_NOTBASE)) {
2640 /*
2641 * convert [NOSPLIT EAX*1]
2642 * to sib format with 0x0 displacement - [EAX*1+0].
2643 */
2644 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2645 }
2646 }
2647 if (s == 1 && it == REG_NUM_ESP) {
2648 /* swap ESP into base if scale is 1 */
2649 t = it, it = bt, bt = t;
2650 x = ix, ix = bx, bx = x;
2651 }
2652 if (it == REG_NUM_ESP ||
2653 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2654 goto err; /* wrong, for various reasons */
2655
2656 output->rex |= rexflags(it, ix, REX_X);
2657 output->rex |= rexflags(bt, bx, REX_B);
2658
2659 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2660 /* no SIB needed */
2661 int mod, rm;
2662
2663 if (bt == -1) {
2664 rm = 5;
2665 mod = 0;
2666 } else {
2667 rm = (bt & 7);
2668 if (rm != REG_NUM_EBP && o == 0 &&
2669 seg == NO_SEG && !forw_ref &&
2670 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2671 mod = 0;
2672 else if (IS_MOD_01())
2673 mod = 1;
2674 else
2675 mod = 2;
2676 }
2677
2678 output->sib_present = false;
2679 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2680 output->modrm = GEN_MODRM(mod, rfield, rm);
2681 } else {
2682 /* we need a SIB */
2683 int mod, scale, index, base;
2684
2685 if (it == -1)
2686 index = 4, s = 1;
2687 else
2688 index = (it & 7);
2689
2690 switch (s) {
2691 case 1:
2692 scale = 0;
2693 break;
2694 case 2:
2695 scale = 1;
2696 break;
2697 case 4:
2698 scale = 2;
2699 break;
2700 case 8:
2701 scale = 3;
2702 break;
2703 default: /* then what the smeg is it? */
2704 goto err; /* panic */
2705 }
2706
2707 if (bt == -1) {
2708 base = 5;
2709 mod = 0;
2710 } else {
2711 base = (bt & 7);
2712 if (base != REG_NUM_EBP && o == 0 &&
2713 seg == NO_SEG && !forw_ref &&
2714 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2715 mod = 0;
2716 else if (IS_MOD_01())
2717 mod = 1;
2718 else
2719 mod = 2;
2720 }
2721
2722 output->sib_present = true;
2723 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2724 output->modrm = GEN_MODRM(mod, rfield, 4);
2725 output->sib = GEN_SIB(scale, index, base);
2726 }
2727 } else { /* it's 16-bit */
2728 int mod, rm;
2729 int16_t o = input->offset;
2730
2731 /* check for 64-bit long mode */
2732 if (addrbits == 64)
2733 goto err;
2734
2735 /* check all registers are BX, BP, SI or DI */
2736 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2737 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2738 goto err;
2739
2740 /* ensure the user didn't specify DWORD/QWORD */
2741 if (input->disp_size == 32 || input->disp_size == 64)
2742 goto err;
2743
2744 if (s != 1 && i != -1)
2745 goto err; /* no can do, in 16-bit EA */
2746 if (b == -1 && i != -1) {
2747 int tmp = b;
2748 b = i;
2749 i = tmp;
2750 } /* swap */
2751 if ((b == R_SI || b == R_DI) && i != -1) {
2752 int tmp = b;
2753 b = i;
2754 i = tmp;
2755 }
2756 /* have BX/BP as base, SI/DI index */
2757 if (b == i)
2758 goto err; /* shouldn't ever happen, in theory */
2759 if (i != -1 && b != -1 &&
2760 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2761 goto err; /* invalid combinations */
2762 if (b == -1) /* pure offset: handled above */
2763 goto err; /* so if it gets to here, panic! */
2764
2765 rm = -1;
2766 if (i != -1)
2767 switch (i * 256 + b) {
2768 case R_SI * 256 + R_BX:
2769 rm = 0;
2770 break;
2771 case R_DI * 256 + R_BX:
2772 rm = 1;
2773 break;
2774 case R_SI * 256 + R_BP:
2775 rm = 2;
2776 break;
2777 case R_DI * 256 + R_BP:
2778 rm = 3;
2779 break;
2780 } else
2781 switch (b) {
2782 case R_SI:
2783 rm = 4;
2784 break;
2785 case R_DI:
2786 rm = 5;
2787 break;
2788 case R_BP:
2789 rm = 6;
2790 break;
2791 case R_BX:
2792 rm = 7;
2793 break;
2794 }
2795 if (rm == -1) /* can't happen, in theory */
2796 goto err; /* so panic if it does */
2797
2798 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2799 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2800 mod = 0;
2801 else if (IS_MOD_01())
2802 mod = 1;
2803 else
2804 mod = 2;
2805
2806 output->sib_present = false; /* no SIB - it's 16-bit */
2807 output->bytes = mod; /* bytes of offset needed */
2808 output->modrm = GEN_MODRM(mod, rfield, rm);
2809 }
2810 }
2811 }
2812
2813 output->size = 1 + output->sib_present + output->bytes;
2814 return output->type;
2815
2816 err:
2817 return output->type = EA_INVALID;
2818 }
2819
2820 static void add_asp(insn *ins, int addrbits)
2821 {
2822 int j, valid;
2823 int defdisp;
2824
2825 valid = (addrbits == 64) ? 64|32 : 32|16;
2826
2827 switch (ins->prefixes[PPS_ASIZE]) {
2828 case P_A16:
2829 valid &= 16;
2830 break;
2831 case P_A32:
2832 valid &= 32;
2833 break;
2834 case P_A64:
2835 valid &= 64;
2836 break;
2837 case P_ASP:
2838 valid &= (addrbits == 32) ? 16 : 32;
2839 break;
2840 default:
2841 break;
2842 }
2843
2844 for (j = 0; j < ins->operands; j++) {
2845 if (is_class(MEMORY, ins->oprs[j].type)) {
2846 opflags_t i, b;
2847
2848 /* Verify as Register */
2849 if (!is_register(ins->oprs[j].indexreg))
2850 i = 0;
2851 else
2852 i = nasm_reg_flags[ins->oprs[j].indexreg];
2853
2854 /* Verify as Register */
2855 if (!is_register(ins->oprs[j].basereg))
2856 b = 0;
2857 else
2858 b = nasm_reg_flags[ins->oprs[j].basereg];
2859
2860 if (ins->oprs[j].scale == 0)
2861 i = 0;
2862
2863 if (!i && !b) {
2864 int ds = ins->oprs[j].disp_size;
2865 if ((addrbits != 64 && ds > 8) ||
2866 (addrbits == 64 && ds == 16))
2867 valid &= ds;
2868 } else {
2869 if (!(REG16 & ~b))
2870 valid &= 16;
2871 if (!(REG32 & ~b))
2872 valid &= 32;
2873 if (!(REG64 & ~b))
2874 valid &= 64;
2875
2876 if (!(REG16 & ~i))
2877 valid &= 16;
2878 if (!(REG32 & ~i))
2879 valid &= 32;
2880 if (!(REG64 & ~i))
2881 valid &= 64;
2882 }
2883 }
2884 }
2885
2886 if (valid & addrbits) {
2887 ins->addr_size = addrbits;
2888 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2889 /* Add an address size prefix */
2890 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2891 ins->addr_size = (addrbits == 32) ? 16 : 32;
2892 } else {
2893 /* Impossible... */
2894 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2895 ins->addr_size = addrbits; /* Error recovery */
2896 }
2897
2898 defdisp = ins->addr_size == 16 ? 16 : 32;
2899
2900 for (j = 0; j < ins->operands; j++) {
2901 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2902 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2903 /*
2904 * mem_offs sizes must match the address size; if not,
2905 * strip the MEM_OFFS bit and match only EA instructions
2906 */
2907 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2908 }
2909 }
2910 }
The Netwide Assembler