insns.dat: Add BLCI
[nasm.git] / insns.h
blobd25891035732f2adda9a82fa9ff9dd517abbaa3e
1 /* insns.h header file for insns.c
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 */
9 #ifndef NASM_INSNS_H
10 #define NASM_INSNS_H
12 #include "nasm.h"
13 #include "tokens.h"
15 struct itemplate {
16 enum opcode opcode; /* the token, passed from "parser.c" */
17 int operands; /* number of operands */
18 opflags_t opd[MAX_OPERANDS]; /* bit flags for operand types */
19 const uint8_t *code; /* the code it assembles to */
20 uint32_t flags; /* some flags */
23 /* Disassembler table structure */
26 * If n == -1, then p points to another table of 256
27 * struct disasm_index, otherwise p points to a list of n
28 * struct itemplates to consider.
30 struct disasm_index {
31 const void *p;
32 int n;
35 /* Tables for the assembler and disassembler, respectively */
36 extern const struct itemplate * const nasm_instructions[];
37 extern const struct disasm_index itable[256];
38 extern const struct disasm_index * const itable_vex[2][32][4];
40 /* Common table for the byte codes */
41 extern const uint8_t nasm_bytecodes[];
44 * this define is used to signify the end of an itemplate
46 #define ITEMPLATE_END {-1,-1,{-1,-1,-1},NULL,0}
49 * Instruction template flags. These specify which processor
50 * targets the instruction is eligible for, whether it is
51 * privileged or undocumented, and also specify extra error
52 * checking on the matching of the instruction.
54 * IF_SM stands for Size Match: any operand whose size is not
55 * explicitly specified by the template is `really' intended to be
56 * the same size as the first size-specified operand.
57 * Non-specification is tolerated in the input instruction, but
58 * _wrong_ specification is not.
60 * IF_SM2 invokes Size Match on only the first _two_ operands, for
61 * three-operand instructions such as SHLD: it implies that the
62 * first two operands must match in size, but that the third is
63 * required to be _unspecified_.
65 * IF_SB invokes Size Byte: operands with unspecified size in the
66 * template are really bytes, and so no non-byte specification in
67 * the input instruction will be tolerated. IF_SW similarly invokes
68 * Size Word, and IF_SD invokes Size Doubleword.
70 * (The default state if neither IF_SM nor IF_SM2 is specified is
71 * that any operand with unspecified size in the template is
72 * required to have unspecified size in the instruction too...)
75 #define IF_SM 0x00000001UL /* size match */
76 #define IF_SM2 0x00000002UL /* size match first two operands */
77 #define IF_SB 0x00000004UL /* unsized operands can't be non-byte */
78 #define IF_SW 0x00000008UL /* unsized operands can't be non-word */
79 #define IF_SD 0x0000000CUL /* unsized operands can't be non-dword */
80 #define IF_SQ 0x00000010UL /* unsized operands can't be non-qword */
81 #define IF_SO 0x00000014UL /* unsized operands can't be non-oword */
82 #define IF_SY 0x00000018UL /* unsized operands can't be non-yword */
83 #define IF_SZ 0x00000038UL /* unsized operands must match the bitsize */
84 #define IF_SX 0x0000003CUL /* unsized operands not allowed */
85 #define IF_SMASK 0x0000003CUL /* mask for unsized argument size */
86 #define IF_AR0 0x00000040UL /* SB, SW, SD applies to argument 0 */
87 #define IF_AR1 0x00000080UL /* SB, SW, SD applies to argument 1 */
88 #define IF_AR2 0x000000C0UL /* SB, SW, SD applies to argument 2 */
89 #define IF_AR3 0x00000100UL /* SB, SW, SD applies to argument 3 */
90 #define IF_AR4 0x00000140UL /* SB, SW, SD applies to argument 4 */
91 #define IF_ARMASK 0x000001C0UL /* mask for unsized argument spec */
92 #define IF_ARSHFT 6 /* LSB in IF_ARMASK */
93 #define IF_OPT 0x00000200UL /* optimizing assembly only */
94 /* The next 3 bits aren't actually used for anything */
95 #define IF_PRIV 0x00000000UL /* it's a privileged instruction */
96 #define IF_SMM 0x00000000UL /* it's only valid in SMM */
97 #define IF_PROT 0x00000000UL /* it's protected mode only */
98 #define IF_LOCK 0x00000400UL /* lockable if operand 0 is memory */
99 #define IF_NOLONG 0x00000800UL /* it's not available in long mode */
100 #define IF_LONG 0x00001000UL /* long mode instruction */
101 #define IF_NOHLE 0x00002000UL /* HLE prefixes forbidden */
102 /* These flags are currently not used for anything - intended for insn set */
103 #define IF_UNDOC 0x00000000UL /* it's an undocumented instruction */
104 #define IF_FPU 0x00000000UL /* it's an FPU instruction */
105 #define IF_MMX 0x00000000UL /* it's an MMX instruction */
106 #define IF_3DNOW 0x00000000UL /* it's a 3DNow! instruction */
107 #define IF_SSE 0x00000000UL /* it's a SSE (KNI, MMX2) instruction */
108 #define IF_SSE2 0x00000000UL /* it's a SSE2 instruction */
109 #define IF_SSE3 0x00000000UL /* it's a SSE3 (PNI) instruction */
110 #define IF_VMX 0x00000000UL /* it's a VMX instruction */
111 #define IF_SSSE3 0x00000000UL /* it's an SSSE3 instruction */
112 #define IF_SSE4A 0x00000000UL /* AMD SSE4a */
113 #define IF_SSE41 0x00000000UL /* it's an SSE4.1 instruction */
114 #define IF_SSE42 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */
115 #define IF_SSE5 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */
116 #define IF_AVX 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */
117 #define IF_AVX2 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */
118 #define IF_FMA 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */
119 #define IF_BMI1 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */
120 #define IF_BMI2 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */
121 #define IF_TBM 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */
122 #define IF_HLE 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */
123 #define IF_RTM 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */
124 #define IF_INVPCID 0x00000000UL /* HACK NEED TO REORGANIZE THESE BITS */
125 #define IF_PMASK 0xFF000000UL /* the mask for processor types */
126 #define IF_PLEVEL 0x0F000000UL /* the mask for processor instr. level */
127 /* also the highest possible processor */
128 #define IF_PFMASK 0xF01FF800UL /* the mask for disassembly "prefer" */
129 #define IF_8086 0x00000000UL /* 8086 instruction */
130 #define IF_186 0x01000000UL /* 186+ instruction */
131 #define IF_286 0x02000000UL /* 286+ instruction */
132 #define IF_386 0x03000000UL /* 386+ instruction */
133 #define IF_486 0x04000000UL /* 486+ instruction */
134 #define IF_PENT 0x05000000UL /* Pentium instruction */
135 #define IF_P6 0x06000000UL /* P6 instruction */
136 #define IF_KATMAI 0x07000000UL /* Katmai instructions */
137 #define IF_WILLAMETTE 0x08000000UL /* Willamette instructions */
138 #define IF_PRESCOTT 0x09000000UL /* Prescott instructions */
139 #define IF_X86_64 0x0A000000UL /* x86-64 instruction (long or legacy mode) */
140 #define IF_NEHALEM 0x0B000000UL /* Nehalem instruction */
141 #define IF_WESTMERE 0x0C000000UL /* Westmere instruction */
142 #define IF_SANDYBRIDGE 0x0D000000UL /* Sandy Bridge instruction */
143 #define IF_FUTURE 0x0E000000UL /* Future processor (not yet disclosed) */
144 #define IF_X64 (IF_LONG|IF_X86_64)
145 #define IF_IA64 0x0F000000UL /* IA64 instructions (in x86 mode) */
146 #define IF_CYRIX 0x10000000UL /* Cyrix-specific instruction */
147 #define IF_AMD 0x20000000UL /* AMD-specific instruction */
149 #endif /* NASM_INSNS_H */