1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2016 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * Bytecode specification
38 * ----------------------
41 * Codes Mnemonic Explanation
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
85 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
88 * [l0] ll = 0 (.128, .lz)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
178 #include "compiler.h"
183 #include <inttypes.h>
187 #include "assemble.h"
195 * Matching errors. These should be sorted so that more specific
196 * errors come later in the sequence.
209 * Matching success; the conditional ones first
211 MOK_JUMP
, /* Matching OK but needs jmp_match() */
212 MOK_GOOD
/* Matching unconditionally OK */
216 enum ea_type type
; /* what kind of EA is this? */
217 int sib_present
; /* is a SIB byte necessary? */
218 int bytes
; /* # of bytes of offset needed */
219 int size
; /* lazy - this is sib+bytes+1 */
220 uint8_t modrm
, sib
, rex
, rip
; /* the bytes themselves */
221 int8_t disp8
; /* compressed displacement for EVEX */
224 #define GEN_SIB(scale, index, base) \
225 (((scale) << 6) | ((index) << 3) | ((base)))
227 #define GEN_MODRM(mod, reg, rm) \
228 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
230 static iflag_t cpu
; /* cpu level received from nasm.c */
232 static int64_t calcsize(int32_t, int64_t, int, insn
*,
233 const struct itemplate
*);
234 static void gencode(int32_t segment
, int64_t offset
, int bits
,
235 insn
* ins
, const struct itemplate
*temp
,
237 static enum match_result
find_match(const struct itemplate
**tempp
,
239 int32_t segment
, int64_t offset
, int bits
);
240 static enum match_result
matches(const struct itemplate
*, insn
*, int bits
);
241 static opflags_t
regflag(const operand
*);
242 static int32_t regval(const operand
*);
243 static int rexflags(int, opflags_t
, int);
244 static int op_rexflags(const operand
*, int);
245 static int op_evexflags(const operand
*, int, uint8_t);
246 static void add_asp(insn
*, int);
248 static enum ea_type
process_ea(operand
*, ea
*, int, int, opflags_t
, insn
*);
250 static int has_prefix(insn
* ins
, enum prefix_pos pos
, int prefix
)
252 return ins
->prefixes
[pos
] == prefix
;
255 static void assert_no_prefix(insn
* ins
, enum prefix_pos pos
)
257 if (ins
->prefixes
[pos
])
258 nasm_error(ERR_NONFATAL
, "invalid %s prefix",
259 prefix_name(ins
->prefixes
[pos
]));
262 static const char *size_name(int size
)
286 static void warn_overflow(int pass
, int size
)
288 nasm_error(ERR_WARNING
| pass
| ERR_WARN_NOV
,
289 "%s data exceeds bounds", size_name(size
));
292 static void warn_overflow_const(int64_t data
, int size
)
294 if (overflow_general(data
, size
))
295 warn_overflow(ERR_PASS1
, size
);
298 static void warn_overflow_opd(const struct operand
*o
, int size
)
300 if (o
->wrt
== NO_SEG
&& o
->segment
== NO_SEG
) {
301 if (overflow_general(o
->offset
, size
))
302 warn_overflow(ERR_PASS2
, size
);
307 * Size of an address relocation, or zero if not an address
309 static int addrsize(enum out_type type
, uint64_t size
)
313 return abs((int)size
);
328 * This routine wrappers the real output format's output routine,
329 * in order to pass a copy of the data off to the listing file
330 * generator at the same time, flatten unnecessary relocations,
331 * and verify backend compatibility.
333 static void out(int64_t offset
, int32_t segto
, const void *data
,
334 enum out_type type
, uint64_t size
,
335 int32_t segment
, int32_t wrt
)
337 static int32_t lineno
= 0; /* static!!! */
338 static const char *lnfname
= NULL
;
340 int asize
= addrsize(type
, size
); /* Address size in bytes */
341 const int amax
= ofmt
->maxbits
>> 3; /* Maximum address size in bytes */
343 if (type
== OUT_ADDRESS
&& segment
== NO_SEG
&& wrt
== NO_SEG
) {
345 * This is a non-relocated address, and we're going to
346 * convert it into RAWDATA format.
351 nasm_panic(0, "OUT_ADDRESS with size > 8");
355 WRITEADDR(q
, *(int64_t *)data
, asize
);
359 asize
= 0; /* No longer an address */
362 lfmt
->output(offset
, data
, type
, size
);
365 * this call to src_get determines when we call the
366 * debug-format-specific "linenum" function
367 * it updates lineno and lnfname to the current values
368 * returning 0 if "same as last time", -2 if lnfname
369 * changed, and the amount by which lineno changed,
370 * if it did. thus, these variables must be static
373 if (src_get(&lineno
, &lnfname
))
374 dfmt
->linenum(lnfname
, lineno
, segto
);
376 if (asize
&& asize
> amax
) {
377 if (type
!= OUT_ADDRESS
|| (int)size
< 0) {
378 nasm_error(ERR_NONFATAL
,
379 "%d-bit signed relocation unsupported by output format %s\n",
380 asize
<< 3, ofmt
->shortname
);
383 nasm_error(ERR_WARNING
| ERR_WARN_ZEXTRELOC
,
384 "%d-bit unsigned relocation zero-extended from %d bits\n",
385 asize
<< 3, ofmt
->maxbits
);
386 ofmt
->output(segto
, data
, type
, amax
, segment
, wrt
);
391 segment
= wrt
= NO_SEG
;
394 ofmt
->output(segto
, data
, type
, size
, segment
, wrt
);
397 static void out_imm8(int64_t offset
, int32_t segment
,
398 struct operand
*opx
, int asize
)
400 if (opx
->segment
!= NO_SEG
) {
401 uint64_t data
= opx
->offset
;
402 out(offset
, segment
, &data
, OUT_ADDRESS
, asize
, opx
->segment
, opx
->wrt
);
404 uint8_t byte
= opx
->offset
;
405 out(offset
, segment
, &byte
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
409 static bool jmp_match(int32_t segment
, int64_t offset
, int bits
,
410 insn
* ins
, const struct itemplate
*temp
)
413 const uint8_t *code
= temp
->code
;
417 if (((c
& ~1) != 0370) || (ins
->oprs
[0].type
& STRICT
))
421 if (optimizing
< 0 && c
== 0371)
424 isize
= calcsize(segment
, offset
, bits
, ins
, temp
);
426 if (ins
->oprs
[0].opflags
& OPFLAG_UNKNOWN
)
427 /* Be optimistic in pass 1 */
430 if (ins
->oprs
[0].segment
!= segment
)
433 isize
= ins
->oprs
[0].offset
- offset
- isize
; /* isize is delta */
434 is_byte
= (isize
>= -128 && isize
<= 127); /* is it byte size? */
436 if (is_byte
&& c
== 0371 && ins
->prefixes
[PPS_REP
] == P_BND
) {
437 /* jmp short (opcode eb) cannot be used with bnd prefix. */
438 ins
->prefixes
[PPS_REP
] = P_none
;
439 nasm_error(ERR_WARNING
| ERR_WARN_BND
| ERR_PASS2
,
440 "jmp short does not init bnd regs - bnd prefix dropped.");
446 int64_t assemble(int32_t segment
, int64_t offset
, int bits
, iflag_t cp
,
449 const struct itemplate
*temp
;
454 int64_t start
= offset
;
455 int64_t wsize
; /* size for DB etc. */
459 wsize
= idata_bytes(instruction
->opcode
);
465 int32_t t
= instruction
->times
;
467 nasm_panic(0, "instruction->times < 0 (%"PRId32
") in assemble()", t
);
469 while (t
--) { /* repeat TIMES times */
470 list_for_each(e
, instruction
->eops
) {
471 if (e
->type
== EOT_DB_NUMBER
) {
473 nasm_error(ERR_NONFATAL
,
474 "integer supplied to a DT, DO or DY"
477 out(offset
, segment
, &e
->offset
,
478 OUT_ADDRESS
, wsize
, e
->segment
, e
->wrt
);
481 } else if (e
->type
== EOT_DB_STRING
||
482 e
->type
== EOT_DB_STRING_FREE
) {
485 out(offset
, segment
, e
->stringval
,
486 OUT_RAWDATA
, e
->stringlen
, NO_SEG
, NO_SEG
);
487 align
= e
->stringlen
% wsize
;
490 align
= wsize
- align
;
491 out(offset
, segment
, zero_buffer
,
492 OUT_RAWDATA
, align
, NO_SEG
, NO_SEG
);
494 offset
+= e
->stringlen
+ align
;
497 if (t
> 0 && t
== instruction
->times
- 1) {
499 * Dummy call to lfmt->output to give the offset to the
502 lfmt
->output(offset
, NULL
, OUT_RAWDATA
, 0);
503 lfmt
->uplevel(LIST_TIMES
);
506 if (instruction
->times
> 1)
507 lfmt
->downlevel(LIST_TIMES
);
508 return offset
- start
;
511 if (instruction
->opcode
== I_INCBIN
) {
512 const char *fname
= instruction
->eops
->stringval
;
515 fp
= fopen(fname
, "rb");
517 nasm_error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
519 } else if (fseek(fp
, 0L, SEEK_END
) < 0) {
520 nasm_error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
524 static char buf
[4096];
525 size_t t
= instruction
->times
;
530 if (instruction
->eops
->next
) {
531 base
= instruction
->eops
->next
->offset
;
533 if (instruction
->eops
->next
->next
&&
534 len
> (size_t)instruction
->eops
->next
->next
->offset
)
535 len
= (size_t)instruction
->eops
->next
->next
->offset
;
538 * Dummy call to lfmt->output to give the offset to the
541 lfmt
->output(offset
, NULL
, OUT_RAWDATA
, 0);
542 lfmt
->uplevel(LIST_INCBIN
);
546 fseek(fp
, base
, SEEK_SET
);
550 m
= fread(buf
, 1, l
> sizeof(buf
) ? sizeof(buf
) : l
, fp
);
553 * This shouldn't happen unless the file
554 * actually changes while we are reading
557 nasm_error(ERR_NONFATAL
,
558 "`incbin': unexpected EOF while"
559 " reading file `%s'", fname
);
560 t
= 0; /* Try to exit cleanly */
563 out(offset
, segment
, buf
, OUT_RAWDATA
, m
,
568 lfmt
->downlevel(LIST_INCBIN
);
569 if (instruction
->times
> 1) {
571 * Dummy call to lfmt->output to give the offset to the
574 lfmt
->output(offset
, NULL
, OUT_RAWDATA
, 0);
575 lfmt
->uplevel(LIST_TIMES
);
576 lfmt
->downlevel(LIST_TIMES
);
579 return instruction
->times
* len
;
581 return 0; /* if we're here, there's an error */
584 /* Check to see if we need an address-size prefix */
585 add_asp(instruction
, bits
);
587 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
591 int64_t insn_size
= calcsize(segment
, offset
, bits
, instruction
, temp
);
592 itimes
= instruction
->times
;
593 if (insn_size
< 0) /* shouldn't be, on pass two */
594 nasm_panic(0, "errors made it through from pass one");
597 for (j
= 0; j
< MAXPREFIX
; j
++) {
599 switch (instruction
->prefixes
[j
]) {
620 nasm_error(ERR_WARNING
| ERR_PASS2
,
621 "cs segment base generated, but will be ignored in 64-bit mode");
627 nasm_error(ERR_WARNING
| ERR_PASS2
,
628 "ds segment base generated, but will be ignored in 64-bit mode");
634 nasm_error(ERR_WARNING
| ERR_PASS2
,
635 "es segment base generated, but will be ignored in 64-bit mode");
647 nasm_error(ERR_WARNING
| ERR_PASS2
,
648 "ss segment base generated, but will be ignored in 64-bit mode");
654 nasm_error(ERR_NONFATAL
,
655 "segr6 and segr7 cannot be used as prefixes");
659 nasm_error(ERR_NONFATAL
,
660 "16-bit addressing is not supported "
662 } else if (bits
!= 16)
671 nasm_error(ERR_NONFATAL
,
672 "64-bit addressing is only supported "
700 nasm_panic(0, "invalid instruction prefix");
703 out(offset
, segment
, &c
, OUT_RAWDATA
, 1,
708 insn_end
= offset
+ insn_size
;
709 gencode(segment
, offset
, bits
, instruction
,
712 if (itimes
> 0 && itimes
== instruction
->times
- 1) {
714 * Dummy call to lfmt->output to give the offset to the
717 lfmt
->output(offset
, NULL
, OUT_RAWDATA
, 0);
718 lfmt
->uplevel(LIST_TIMES
);
721 if (instruction
->times
> 1)
722 lfmt
->downlevel(LIST_TIMES
);
723 return offset
- start
;
727 case MERR_OPSIZEMISSING
:
728 nasm_error(ERR_NONFATAL
, "operation size not specified");
730 case MERR_OPSIZEMISMATCH
:
731 nasm_error(ERR_NONFATAL
, "mismatch in operand sizes");
733 case MERR_BRNUMMISMATCH
:
734 nasm_error(ERR_NONFATAL
,
735 "mismatch in the number of broadcasting elements");
738 nasm_error(ERR_NONFATAL
, "no instruction for this cpu level");
741 nasm_error(ERR_NONFATAL
, "instruction not supported in %d-bit mode",
744 case MERR_ENCMISMATCH
:
745 nasm_error(ERR_NONFATAL
, "specific encoding scheme not available");
748 nasm_error(ERR_NONFATAL
, "bnd prefix is not allowed");
751 nasm_error(ERR_NONFATAL
, "%s prefix is not allowed",
752 (has_prefix(instruction
, PPS_REP
, P_REPNE
) ?
756 nasm_error(ERR_NONFATAL
,
757 "invalid combination of opcode and operands");
764 int64_t insn_size(int32_t segment
, int64_t offset
, int bits
, iflag_t cp
,
767 const struct itemplate
*temp
;
772 if (instruction
->opcode
== I_none
)
775 if (instruction
->opcode
== I_DB
|| instruction
->opcode
== I_DW
||
776 instruction
->opcode
== I_DD
|| instruction
->opcode
== I_DQ
||
777 instruction
->opcode
== I_DT
|| instruction
->opcode
== I_DO
||
778 instruction
->opcode
== I_DY
) {
780 int32_t isize
, osize
, wsize
;
783 wsize
= idata_bytes(instruction
->opcode
);
785 list_for_each(e
, instruction
->eops
) {
789 if (e
->type
== EOT_DB_NUMBER
) {
791 warn_overflow_const(e
->offset
, wsize
);
792 } else if (e
->type
== EOT_DB_STRING
||
793 e
->type
== EOT_DB_STRING_FREE
)
794 osize
= e
->stringlen
;
796 align
= (-osize
) % wsize
;
799 isize
+= osize
+ align
;
801 return isize
* instruction
->times
;
804 if (instruction
->opcode
== I_INCBIN
) {
805 const char *fname
= instruction
->eops
->stringval
;
810 fp
= fopen(fname
, "rb");
812 nasm_error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
814 else if (fseek(fp
, 0L, SEEK_END
) < 0)
815 nasm_error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
819 if (instruction
->eops
->next
) {
820 len
-= instruction
->eops
->next
->offset
;
821 if (instruction
->eops
->next
->next
&&
822 len
> (size_t)instruction
->eops
->next
->next
->offset
) {
823 len
= (size_t)instruction
->eops
->next
->next
->offset
;
826 val
= instruction
->times
* len
;
833 /* Check to see if we need an address-size prefix */
834 add_asp(instruction
, bits
);
836 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
838 /* we've matched an instruction. */
842 isize
= calcsize(segment
, offset
, bits
, instruction
, temp
);
845 for (j
= 0; j
< MAXPREFIX
; j
++) {
846 switch (instruction
->prefixes
[j
]) {
876 return isize
* instruction
->times
;
878 return -1; /* didn't match any instruction */
882 static void bad_hle_warn(const insn
* ins
, uint8_t hleok
)
884 enum prefixes rep_pfx
= ins
->prefixes
[PPS_REP
];
885 enum whatwarn
{ w_none
, w_lock
, w_inval
} ww
;
886 static const enum whatwarn warn
[2][4] =
888 { w_inval
, w_inval
, w_none
, w_lock
}, /* XACQUIRE */
889 { w_inval
, w_none
, w_none
, w_lock
}, /* XRELEASE */
893 n
= (unsigned int)rep_pfx
- P_XACQUIRE
;
895 return; /* Not XACQUIRE/XRELEASE */
898 if (!is_class(MEMORY
, ins
->oprs
[0].type
))
899 ww
= w_inval
; /* HLE requires operand 0 to be memory */
906 if (ins
->prefixes
[PPS_LOCK
] != P_LOCK
) {
907 nasm_error(ERR_WARNING
| ERR_WARN_HLE
| ERR_PASS2
,
908 "%s with this instruction requires lock",
909 prefix_name(rep_pfx
));
914 nasm_error(ERR_WARNING
| ERR_WARN_HLE
| ERR_PASS2
,
915 "%s invalid with this instruction",
916 prefix_name(rep_pfx
));
921 /* Common construct */
922 #define case3(x) case (x): case (x)+1: case (x)+2
923 #define case4(x) case3(x): case (x)+3
925 static int64_t calcsize(int32_t segment
, int64_t offset
, int bits
,
926 insn
* ins
, const struct itemplate
*temp
)
928 const uint8_t *codes
= temp
->code
;
937 bool lockcheck
= true;
938 enum reg_enum mib_index
= R_none
; /* For a separate index MIB reg form */
940 ins
->rex
= 0; /* Ensure REX is reset */
941 eat
= EA_SCALAR
; /* Expect a scalar EA */
942 memset(ins
->evex_p
, 0, 3); /* Ensure EVEX is reset */
944 if (ins
->prefixes
[PPS_OSIZE
] == P_O64
)
947 (void)segment
; /* Don't warn that this parameter is unused */
948 (void)offset
; /* Don't warn that this parameter is unused */
952 op1
= (c
& 3) + ((opex
& 1) << 2);
953 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
954 opx
= &ins
->oprs
[op1
];
955 opex
= 0; /* For the next iteration */
959 codes
+= c
, length
+= c
;
968 op_rexflags(opx
, REX_B
|REX_H
|REX_P
|REX_W
);
973 /* this is an index reg of MIB operand */
974 mib_index
= opx
->basereg
;
987 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
988 length
+= (opx
->type
& BITS16
) ? 2 : 4;
990 length
+= (bits
== 16) ? 2 : 4;
998 length
+= ins
->addr_size
>> 3;
1006 length
+= 8; /* MOV reg64/imm */
1014 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1015 length
+= (opx
->type
& BITS16
) ? 2 : 4;
1017 length
+= (bits
== 16) ? 2 : 4;
1040 ins
->vexreg
= regval(opx
);
1041 ins
->evex_p
[2] |= op_evexflags(opx
, EVEX_P2VP
, 2); /* High-16 NDS */
1042 ins
->vex_cm
= *codes
++;
1043 ins
->vex_wlp
= *codes
++;
1044 ins
->evex_tuple
= (*codes
++ - 0300);
1050 ins
->vex_cm
= *codes
++;
1051 ins
->vex_wlp
= *codes
++;
1052 ins
->evex_tuple
= (*codes
++ - 0300);
1061 ins
->vexreg
= regval(opx
);
1062 ins
->vex_cm
= *codes
++;
1063 ins
->vex_wlp
= *codes
++;
1069 ins
->vex_cm
= *codes
++;
1070 ins
->vex_wlp
= *codes
++;
1087 length
+= (bits
!= 16) && !has_prefix(ins
, PPS_ASIZE
, P_A16
);
1091 length
+= (bits
!= 32) && !has_prefix(ins
, PPS_ASIZE
, P_A32
);
1098 if (bits
!= 64 || has_prefix(ins
, PPS_ASIZE
, P_A16
) ||
1099 has_prefix(ins
, PPS_ASIZE
, P_A32
))
1108 enum prefixes pfx
= ins
->prefixes
[PPS_OSIZE
];
1112 nasm_error(ERR_WARNING
| ERR_PASS2
, "invalid operand size prefix");
1114 ins
->prefixes
[PPS_OSIZE
] = P_O16
;
1120 enum prefixes pfx
= ins
->prefixes
[PPS_OSIZE
];
1124 nasm_error(ERR_WARNING
| ERR_PASS2
, "invalid operand size prefix");
1126 ins
->prefixes
[PPS_OSIZE
] = P_O32
;
1168 if (!ins
->prefixes
[PPS_REP
])
1169 ins
->prefixes
[PPS_REP
] = P_REP
;
1173 if (!ins
->prefixes
[PPS_REP
])
1174 ins
->prefixes
[PPS_REP
] = P_REPNE
;
1178 if (ins
->oprs
[0].segment
!= NO_SEG
)
1179 nasm_error(ERR_NONFATAL
, "attempt to reserve non-constant"
1180 " quantity of BSS space");
1181 else if (ins
->oprs
[0].opflags
& OPFLAG_FORWARD
)
1182 nasm_error(ERR_WARNING
| ERR_PASS1
,
1183 "forward reference in RESx can have unpredictable results");
1185 length
+= ins
->oprs
[0].offset
;
1189 if (!ins
->prefixes
[PPS_WAIT
])
1190 ins
->prefixes
[PPS_WAIT
] = P_WAIT
;
1245 struct operand
*opy
= &ins
->oprs
[op2
];
1246 struct operand
*op_er_sae
;
1248 ea_data
.rex
= 0; /* Ensure ea.REX is initially 0 */
1251 /* pick rfield from operand b (opx) */
1252 rflags
= regflag(opx
);
1253 rfield
= nasm_regvals
[opx
->basereg
];
1259 /* EVEX.b1 : evex_brerop contains the operand position */
1260 op_er_sae
= (ins
->evex_brerop
>= 0 ?
1261 &ins
->oprs
[ins
->evex_brerop
] : NULL
);
1263 if (op_er_sae
&& (op_er_sae
->decoflags
& (ER
| SAE
))) {
1265 ins
->evex_p
[2] |= EVEX_P2B
;
1266 if (op_er_sae
->decoflags
& ER
) {
1267 /* set EVEX.RC (rounding control) */
1268 ins
->evex_p
[2] |= ((ins
->evex_rm
- BRC_RN
) << 5)
1272 /* set EVEX.L'L (vector length) */
1273 ins
->evex_p
[2] |= ((ins
->vex_wlp
<< (5 - 2)) & EVEX_P2LL
);
1274 ins
->evex_p
[1] |= ((ins
->vex_wlp
<< (7 - 4)) & EVEX_P1W
);
1275 if (opy
->decoflags
& BRDCAST_MASK
) {
1277 ins
->evex_p
[2] |= EVEX_P2B
;
1281 if (itemp_has(temp
, IF_MIB
)) {
1282 opy
->eaflags
|= EAF_MIB
;
1284 * if a separate form of MIB (ICC style) is used,
1285 * the index reg info is merged into mem operand
1287 if (mib_index
!= R_none
) {
1288 opy
->indexreg
= mib_index
;
1290 opy
->hintbase
= mib_index
;
1291 opy
->hinttype
= EAH_NOTBASE
;
1295 if (process_ea(opy
, &ea_data
, bits
,
1296 rfield
, rflags
, ins
) != eat
) {
1297 nasm_error(ERR_NONFATAL
, "invalid effective address");
1300 ins
->rex
|= ea_data
.rex
;
1301 length
+= ea_data
.size
;
1307 nasm_panic(0, "internal instruction table corrupt"
1308 ": instruction code \\%o (0x%02X) given", c
, c
);
1313 ins
->rex
&= rex_mask
;
1315 if (ins
->rex
& REX_NH
) {
1316 if (ins
->rex
& REX_H
) {
1317 nasm_error(ERR_NONFATAL
, "instruction cannot use high registers");
1320 ins
->rex
&= ~REX_P
; /* Don't force REX prefix due to high reg */
1323 switch (ins
->prefixes
[PPS_VEX
]) {
1325 if (!(ins
->rex
& REX_EV
))
1330 if (!(ins
->rex
& REX_V
))
1337 if (ins
->rex
& (REX_V
| REX_EV
)) {
1338 int bad32
= REX_R
|REX_W
|REX_X
|REX_B
;
1340 if (ins
->rex
& REX_H
) {
1341 nasm_error(ERR_NONFATAL
, "cannot use high register in AVX instruction");
1344 switch (ins
->vex_wlp
& 060) {
1358 if (bits
!= 64 && ((ins
->rex
& bad32
) || ins
->vexreg
> 7)) {
1359 nasm_error(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1361 } else if (!(ins
->rex
& REX_EV
) &&
1362 ((ins
->vexreg
> 15) || (ins
->evex_p
[0] & 0xf0))) {
1363 nasm_error(ERR_NONFATAL
, "invalid high-16 register in non-AVX-512");
1366 if (ins
->rex
& REX_EV
)
1368 else if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
)) ||
1369 ins
->prefixes
[PPS_VEX
] == P_VEX3
)
1373 } else if (ins
->rex
& REX_MASK
) {
1374 if (ins
->rex
& REX_H
) {
1375 nasm_error(ERR_NONFATAL
, "cannot use high register in rex instruction");
1377 } else if (bits
== 64) {
1379 } else if ((ins
->rex
& REX_L
) &&
1380 !(ins
->rex
& (REX_P
|REX_W
|REX_X
|REX_B
)) &&
1381 iflag_ffs(&cpu
) >= IF_X86_64
) {
1383 assert_no_prefix(ins
, PPS_LOCK
);
1384 lockcheck
= false; /* Already errored, no need for warning */
1387 nasm_error(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1392 if (has_prefix(ins
, PPS_LOCK
, P_LOCK
) && lockcheck
&&
1393 (!itemp_has(temp
,IF_LOCK
) || !is_class(MEMORY
, ins
->oprs
[0].type
))) {
1394 nasm_error(ERR_WARNING
| ERR_WARN_LOCK
| ERR_PASS2
,
1395 "instruction is not lockable");
1398 bad_hle_warn(ins
, hleok
);
1401 * when BND prefix is set by DEFAULT directive,
1402 * BND prefix is added to every appropriate instruction line
1403 * unless it is overridden by NOBND prefix.
1406 (itemp_has(temp
, IF_BND
) && !has_prefix(ins
, PPS_REP
, P_NOBND
)))
1407 ins
->prefixes
[PPS_REP
] = P_BND
;
1412 static inline unsigned int emit_rex(insn
*ins
, int32_t segment
, int64_t offset
, int bits
)
1415 if ((ins
->rex
& REX_MASK
) &&
1416 !(ins
->rex
& (REX_V
| REX_EV
)) &&
1418 int rex
= (ins
->rex
& REX_MASK
) | REX_P
;
1419 out(offset
, segment
, &rex
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1420 ins
->rex_done
= true;
1428 static void gencode(int32_t segment
, int64_t offset
, int bits
,
1429 insn
* ins
, const struct itemplate
*temp
,
1437 struct operand
*opx
;
1438 const uint8_t *codes
= temp
->code
;
1440 enum ea_type eat
= EA_SCALAR
;
1443 ins
->rex_done
= false;
1447 op1
= (c
& 3) + ((opex
& 1) << 2);
1448 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
1449 opx
= &ins
->oprs
[op1
];
1450 opex
= 0; /* For the next iteration */
1457 offset
+= emit_rex(ins
, segment
, offset
, bits
);
1458 out(offset
, segment
, codes
, OUT_RAWDATA
, c
, NO_SEG
, NO_SEG
);
1470 offset
+= emit_rex(ins
, segment
, offset
, bits
);
1471 bytes
[0] = *codes
++ + (regval(opx
) & 7);
1472 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1480 if (opx
->offset
< -256 || opx
->offset
> 255) {
1481 nasm_error(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1482 "byte value exceeds bounds");
1484 out_imm8(offset
, segment
, opx
, -1);
1489 if (opx
->offset
< 0 || opx
->offset
> 255)
1490 nasm_error(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1491 "unsigned byte value exceeds bounds");
1492 out_imm8(offset
, segment
, opx
, 1);
1497 warn_overflow_opd(opx
, 2);
1499 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1500 opx
->segment
, opx
->wrt
);
1505 if (opx
->type
& (BITS16
| BITS32
))
1506 size
= (opx
->type
& BITS16
) ? 2 : 4;
1508 size
= (bits
== 16) ? 2 : 4;
1509 warn_overflow_opd(opx
, size
);
1511 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1512 opx
->segment
, opx
->wrt
);
1517 warn_overflow_opd(opx
, 4);
1519 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1520 opx
->segment
, opx
->wrt
);
1526 size
= ins
->addr_size
>> 3;
1527 warn_overflow_opd(opx
, size
);
1528 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1529 opx
->segment
, opx
->wrt
);
1534 if (opx
->segment
!= segment
) {
1536 out(offset
, segment
, &data
,
1537 OUT_REL1ADR
, insn_end
- offset
,
1538 opx
->segment
, opx
->wrt
);
1540 data
= opx
->offset
- insn_end
;
1541 if (data
> 127 || data
< -128)
1542 nasm_error(ERR_NONFATAL
, "short jump is out of range");
1543 out(offset
, segment
, &data
,
1544 OUT_ADDRESS
, 1, NO_SEG
, NO_SEG
);
1550 data
= (int64_t)opx
->offset
;
1551 out(offset
, segment
, &data
, OUT_ADDRESS
, 8,
1552 opx
->segment
, opx
->wrt
);
1557 if (opx
->segment
!= segment
) {
1559 out(offset
, segment
, &data
,
1560 OUT_REL2ADR
, insn_end
- offset
,
1561 opx
->segment
, opx
->wrt
);
1563 data
= opx
->offset
- insn_end
;
1564 out(offset
, segment
, &data
,
1565 OUT_ADDRESS
, 2, NO_SEG
, NO_SEG
);
1571 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1572 size
= (opx
->type
& BITS16
) ? 2 : 4;
1574 size
= (bits
== 16) ? 2 : 4;
1575 if (opx
->segment
!= segment
) {
1577 out(offset
, segment
, &data
,
1578 size
== 2 ? OUT_REL2ADR
: OUT_REL4ADR
,
1579 insn_end
- offset
, opx
->segment
, opx
->wrt
);
1581 data
= opx
->offset
- insn_end
;
1582 out(offset
, segment
, &data
,
1583 OUT_ADDRESS
, size
, NO_SEG
, NO_SEG
);
1589 if (opx
->segment
!= segment
) {
1591 out(offset
, segment
, &data
,
1592 OUT_REL4ADR
, insn_end
- offset
,
1593 opx
->segment
, opx
->wrt
);
1595 data
= opx
->offset
- insn_end
;
1596 out(offset
, segment
, &data
,
1597 OUT_ADDRESS
, 4, NO_SEG
, NO_SEG
);
1603 if (opx
->segment
== NO_SEG
)
1604 nasm_error(ERR_NONFATAL
, "value referenced by FAR is not"
1607 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1608 ofmt
->segbase(1 + opx
->segment
),
1615 int mask
= ins
->prefixes
[PPS_VEX
] == P_EVEX
? 7 : 15;
1616 const struct operand
*opy
;
1619 opx
= &ins
->oprs
[c
>> 3];
1620 opy
= &ins
->oprs
[c
& 7];
1621 if (opy
->segment
!= NO_SEG
|| opy
->wrt
!= NO_SEG
) {
1622 nasm_error(ERR_NONFATAL
,
1623 "non-absolute expression not permitted as argument %d",
1625 } else if (opy
->offset
& ~mask
) {
1626 nasm_error(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1627 "is4 argument exceeds bounds");
1629 c
= opy
->offset
& mask
;
1635 opx
= &ins
->oprs
[c
>> 4];
1642 r
= nasm_regvals
[opx
->basereg
];
1643 bytes
[0] = (r
<< 4) | ((r
& 0x10) >> 1) | c
;
1644 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1650 if (opx
->wrt
== NO_SEG
&& opx
->segment
== NO_SEG
&&
1651 (int32_t)data
!= (int64_t)data
) {
1652 nasm_error(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1653 "signed dword immediate exceeds bounds");
1655 out(offset
, segment
, &data
, OUT_ADDRESS
, -4,
1656 opx
->segment
, opx
->wrt
);
1663 ins
->evex_p
[2] |= op_evexflags(&ins
->oprs
[0],
1664 EVEX_P2Z
| EVEX_P2AAA
, 2);
1665 ins
->evex_p
[2] ^= EVEX_P2VP
; /* 1's complement */
1667 /* EVEX.X can be set by either REX or EVEX for different reasons */
1668 bytes
[1] = ((((ins
->rex
& 7) << 5) |
1669 (ins
->evex_p
[0] & (EVEX_P0X
| EVEX_P0RP
))) ^ 0xf0) |
1671 bytes
[2] = ((ins
->rex
& REX_W
) << (7 - 3)) |
1672 ((~ins
->vexreg
& 15) << 3) |
1673 (1 << 2) | (ins
->vex_wlp
& 3);
1674 bytes
[3] = ins
->evex_p
[2];
1675 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 4, NO_SEG
, NO_SEG
);
1682 if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
)) ||
1683 ins
->prefixes
[PPS_VEX
] == P_VEX3
) {
1684 bytes
[0] = (ins
->vex_cm
>> 6) ? 0x8f : 0xc4;
1685 bytes
[1] = (ins
->vex_cm
& 31) | ((~ins
->rex
& 7) << 5);
1686 bytes
[2] = ((ins
->rex
& REX_W
) << (7-3)) |
1687 ((~ins
->vexreg
& 15)<< 3) | (ins
->vex_wlp
& 07);
1688 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 3, NO_SEG
, NO_SEG
);
1692 bytes
[1] = ((~ins
->rex
& REX_R
) << (7-2)) |
1693 ((~ins
->vexreg
& 15) << 3) | (ins
->vex_wlp
& 07);
1694 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 2, NO_SEG
, NO_SEG
);
1709 if (ins
->rex
& REX_W
)
1711 else if (ins
->prefixes
[PPS_OSIZE
] == P_O16
)
1713 else if (ins
->prefixes
[PPS_OSIZE
] == P_O32
)
1718 um
= (uint64_t)2 << (s
-1);
1721 if (uv
> 127 && uv
< (uint64_t)-128 &&
1722 (uv
< um
-128 || uv
> um
-1)) {
1723 /* If this wasn't explicitly byte-sized, warn as though we
1724 * had fallen through to the imm16/32/64 case.
1726 nasm_error(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1727 "%s value exceeds bounds",
1728 (opx
->type
& BITS8
) ? "signed byte" :
1733 if (opx
->segment
!= NO_SEG
) {
1735 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1736 opx
->segment
, opx
->wrt
);
1739 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1750 if (bits
== 32 && !has_prefix(ins
, PPS_ASIZE
, P_A16
)) {
1752 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1759 if (bits
!= 32 && !has_prefix(ins
, PPS_ASIZE
, P_A32
)) {
1761 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1796 *bytes
= *codes
++ ^ get_cond_opcode(ins
->condition
);
1797 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1806 *bytes
= c
- 0332 + 0xF2;
1807 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1812 if (ins
->rex
& REX_R
) {
1814 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1817 ins
->rex
&= ~(REX_L
|REX_R
);
1828 if (ins
->oprs
[0].segment
!= NO_SEG
)
1829 nasm_panic(0, "non-constant BSS size in pass two");
1831 int64_t size
= ins
->oprs
[0].offset
;
1833 out(offset
, segment
, NULL
,
1834 OUT_RESERVE
, size
, NO_SEG
, NO_SEG
);
1847 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1857 *bytes
= c
- 0366 + 0x66;
1858 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1866 *bytes
= bits
== 16 ? 3 : 5;
1867 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1901 struct operand
*opy
= &ins
->oprs
[op2
];
1904 /* pick rfield from operand b (opx) */
1905 rflags
= regflag(opx
);
1906 rfield
= nasm_regvals
[opx
->basereg
];
1908 /* rfield is constant */
1913 if (process_ea(opy
, &ea_data
, bits
,
1914 rfield
, rflags
, ins
) != eat
)
1915 nasm_error(ERR_NONFATAL
, "invalid effective address");
1918 *p
++ = ea_data
.modrm
;
1919 if (ea_data
.sib_present
)
1923 out(offset
, segment
, bytes
, OUT_RAWDATA
, s
, NO_SEG
, NO_SEG
);
1926 * Make sure the address gets the right offset in case
1927 * the line breaks in the .lst file (BR 1197827)
1932 if (ea_data
.bytes
) {
1933 /* use compressed displacement, if available */
1934 data
= ea_data
.disp8
? ea_data
.disp8
: opy
->offset
;
1937 if (opy
->segment
== segment
) {
1939 if (overflow_signed(data
, ea_data
.bytes
))
1940 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1941 out(offset
, segment
, &data
, OUT_ADDRESS
,
1942 ea_data
.bytes
, NO_SEG
, NO_SEG
);
1944 /* overflow check in output/linker? */
1945 out(offset
, segment
, &data
, OUT_REL4ADR
,
1946 insn_end
- offset
, opy
->segment
, opy
->wrt
);
1949 int asize
= ins
->addr_size
>> 3;
1950 int atype
= ea_data
.bytes
;
1952 if (overflow_general(data
, asize
) ||
1953 signed_bits(data
, ins
->addr_size
) !=
1954 signed_bits(data
, ea_data
.bytes
<< 3))
1955 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1957 if (asize
> ea_data
.bytes
) {
1959 * If the address isn't the full width of
1960 * the address size, treat is as signed...
1965 out(offset
, segment
, &data
, OUT_ADDRESS
,
1966 atype
, opy
->segment
, opy
->wrt
);
1974 nasm_panic(0, "internal instruction table corrupt"
1975 ": instruction code \\%o (0x%02X) given", c
, c
);
1981 static opflags_t
regflag(const operand
* o
)
1983 if (!is_register(o
->basereg
))
1984 nasm_panic(0, "invalid operand passed to regflag()");
1985 return nasm_reg_flags
[o
->basereg
];
1988 static int32_t regval(const operand
* o
)
1990 if (!is_register(o
->basereg
))
1991 nasm_panic(0, "invalid operand passed to regval()");
1992 return nasm_regvals
[o
->basereg
];
1995 static int op_rexflags(const operand
* o
, int mask
)
2000 if (!is_register(o
->basereg
))
2001 nasm_panic(0, "invalid operand passed to op_rexflags()");
2003 flags
= nasm_reg_flags
[o
->basereg
];
2004 val
= nasm_regvals
[o
->basereg
];
2006 return rexflags(val
, flags
, mask
);
2009 static int rexflags(int val
, opflags_t flags
, int mask
)
2013 if (val
>= 0 && (val
& 8))
2014 rex
|= REX_B
|REX_X
|REX_R
;
2017 if (!(REG_HIGH
& ~flags
)) /* AH, CH, DH, BH */
2019 else if (!(REG8
& ~flags
) && val
>= 4) /* SPL, BPL, SIL, DIL */
2025 static int evexflags(int val
, decoflags_t deco
,
2026 int mask
, uint8_t byte
)
2032 if (val
>= 0 && (val
& 16))
2033 evex
|= (EVEX_P0RP
| EVEX_P0X
);
2036 if (val
>= 0 && (val
& 16))
2040 if (deco
& OPMASK_MASK
)
2041 evex
|= deco
& EVEX_P2AAA
;
2047 static int op_evexflags(const operand
* o
, int mask
, uint8_t byte
)
2051 val
= nasm_regvals
[o
->basereg
];
2053 return evexflags(val
, o
->decoflags
, mask
, byte
);
2056 static enum match_result
find_match(const struct itemplate
**tempp
,
2058 int32_t segment
, int64_t offset
, int bits
)
2060 const struct itemplate
*temp
;
2061 enum match_result m
, merr
;
2062 opflags_t xsizeflags
[MAX_OPERANDS
];
2063 bool opsizemissing
= false;
2064 int8_t broadcast
= instruction
->evex_brerop
;
2067 /* broadcasting uses a different data element size */
2068 for (i
= 0; i
< instruction
->operands
; i
++)
2070 xsizeflags
[i
] = instruction
->oprs
[i
].decoflags
& BRSIZE_MASK
;
2072 xsizeflags
[i
] = instruction
->oprs
[i
].type
& SIZE_MASK
;
2074 merr
= MERR_INVALOP
;
2076 for (temp
= nasm_instructions
[instruction
->opcode
];
2077 temp
->opcode
!= I_none
; temp
++) {
2078 m
= matches(temp
, instruction
, bits
);
2079 if (m
== MOK_JUMP
) {
2080 if (jmp_match(segment
, offset
, bits
, instruction
, temp
))
2084 } else if (m
== MERR_OPSIZEMISSING
&& !itemp_has(temp
, IF_SX
)) {
2086 * Missing operand size and a candidate for fuzzy matching...
2088 for (i
= 0; i
< temp
->operands
; i
++)
2090 xsizeflags
[i
] |= temp
->deco
[i
] & BRSIZE_MASK
;
2092 xsizeflags
[i
] |= temp
->opd
[i
] & SIZE_MASK
;
2093 opsizemissing
= true;
2097 if (merr
== MOK_GOOD
)
2101 /* No match, but see if we can get a fuzzy operand size match... */
2105 for (i
= 0; i
< instruction
->operands
; i
++) {
2107 * We ignore extrinsic operand sizes on registers, so we should
2108 * never try to fuzzy-match on them. This also resolves the case
2109 * when we have e.g. "xmmrm128" in two different positions.
2111 if (is_class(REGISTER
, instruction
->oprs
[i
].type
))
2114 /* This tests if xsizeflags[i] has more than one bit set */
2115 if ((xsizeflags
[i
] & (xsizeflags
[i
]-1)))
2116 goto done
; /* No luck */
2118 if (i
== broadcast
) {
2119 instruction
->oprs
[i
].decoflags
|= xsizeflags
[i
];
2120 instruction
->oprs
[i
].type
|= (xsizeflags
[i
] == BR_BITS32
?
2123 instruction
->oprs
[i
].type
|= xsizeflags
[i
]; /* Set the size */
2127 /* Try matching again... */
2128 for (temp
= nasm_instructions
[instruction
->opcode
];
2129 temp
->opcode
!= I_none
; temp
++) {
2130 m
= matches(temp
, instruction
, bits
);
2131 if (m
== MOK_JUMP
) {
2132 if (jmp_match(segment
, offset
, bits
, instruction
, temp
))
2139 if (merr
== MOK_GOOD
)
2148 static uint8_t get_broadcast_num(opflags_t opflags
, opflags_t brsize
)
2150 opflags_t opsize
= opflags
& SIZE_MASK
;
2154 * Due to discontinuity between BITS64 and BITS128 (BITS80),
2155 * this cannot be a simple arithmetic calculation.
2157 if (brsize
> BITS64
)
2158 nasm_error(ERR_FATAL
,
2159 "size of broadcasting element is greater than 64 bits");
2163 brcast_num
= BITS64
/ brsize
;
2166 brcast_num
= (opsize
/ BITS128
) * (BITS64
/ brsize
) * 2;
2173 static enum match_result
matches(const struct itemplate
*itemp
,
2174 insn
*instruction
, int bits
)
2176 opflags_t size
[MAX_OPERANDS
], asize
;
2177 bool opsizemissing
= false;
2183 if (itemp
->opcode
!= instruction
->opcode
)
2184 return MERR_INVALOP
;
2187 * Count the operands
2189 if (itemp
->operands
!= instruction
->operands
)
2190 return MERR_INVALOP
;
2195 if (!(optimizing
> 0) && itemp_has(itemp
, IF_OPT
))
2196 return MERR_INVALOP
;
2201 switch (instruction
->prefixes
[PPS_VEX
]) {
2203 if (!itemp_has(itemp
, IF_EVEX
))
2204 return MERR_ENCMISMATCH
;
2208 if (!itemp_has(itemp
, IF_VEX
))
2209 return MERR_ENCMISMATCH
;
2216 * Check that no spurious colons or TOs are present
2218 for (i
= 0; i
< itemp
->operands
; i
++)
2219 if (instruction
->oprs
[i
].type
& ~itemp
->opd
[i
] & (COLON
| TO
))
2220 return MERR_INVALOP
;
2223 * Process size flags
2225 switch (itemp_smask(itemp
)) {
2226 case IF_GENBIT(IF_SB
):
2229 case IF_GENBIT(IF_SW
):
2232 case IF_GENBIT(IF_SD
):
2235 case IF_GENBIT(IF_SQ
):
2238 case IF_GENBIT(IF_SO
):
2241 case IF_GENBIT(IF_SY
):
2244 case IF_GENBIT(IF_SZ
):
2247 case IF_GENBIT(IF_SIZE
):
2268 if (itemp_armask(itemp
)) {
2269 /* S- flags only apply to a specific operand */
2270 i
= itemp_arg(itemp
);
2271 memset(size
, 0, sizeof size
);
2274 /* S- flags apply to all operands */
2275 for (i
= 0; i
< MAX_OPERANDS
; i
++)
2280 * Check that the operand flags all match up,
2281 * it's a bit tricky so lets be verbose:
2283 * 1) Find out the size of operand. If instruction
2284 * doesn't have one specified -- we're trying to
2285 * guess it either from template (IF_S* flag) or
2288 * 2) If template operand do not match the instruction OR
2289 * template has an operand size specified AND this size differ
2290 * from which instruction has (perhaps we got it from code bits)
2292 * a) Check that only size of instruction and operand is differ
2293 * other characteristics do match
2294 * b) Perhaps it's a register specified in instruction so
2295 * for such a case we just mark that operand as "size
2296 * missing" and this will turn on fuzzy operand size
2297 * logic facility (handled by a caller)
2299 for (i
= 0; i
< itemp
->operands
; i
++) {
2300 opflags_t type
= instruction
->oprs
[i
].type
;
2301 decoflags_t deco
= instruction
->oprs
[i
].decoflags
;
2302 bool is_broadcast
= deco
& BRDCAST_MASK
;
2303 uint8_t brcast_num
= 0;
2304 opflags_t template_opsize
, insn_opsize
;
2306 if (!(type
& SIZE_MASK
))
2309 insn_opsize
= type
& SIZE_MASK
;
2310 if (!is_broadcast
) {
2311 template_opsize
= itemp
->opd
[i
] & SIZE_MASK
;
2313 decoflags_t deco_brsize
= itemp
->deco
[i
] & BRSIZE_MASK
;
2315 * when broadcasting, the element size depends on
2316 * the instruction type. decorator flag should match.
2320 template_opsize
= (deco_brsize
== BR_BITS32
? BITS32
: BITS64
);
2321 /* calculate the proper number : {1to<brcast_num>} */
2322 brcast_num
= get_broadcast_num(itemp
->opd
[i
], template_opsize
);
2324 template_opsize
= 0;
2328 if ((itemp
->opd
[i
] & ~type
& ~SIZE_MASK
) ||
2329 (deco
& ~itemp
->deco
[i
] & ~BRNUM_MASK
)) {
2330 return MERR_INVALOP
;
2331 } else if (template_opsize
) {
2332 if (template_opsize
!= insn_opsize
) {
2334 return MERR_INVALOP
;
2335 } else if (!is_class(REGISTER
, type
)) {
2337 * Note: we don't honor extrinsic operand sizes for registers,
2338 * so "missing operand size" for a register should be
2339 * considered a wildcard match rather than an error.
2341 opsizemissing
= true;
2343 } else if (is_broadcast
&&
2345 (2U << ((deco
& BRNUM_MASK
) >> BRNUM_SHIFT
)))) {
2347 * broadcasting opsize matches but the number of repeated memory
2348 * element does not match.
2349 * if 64b double precision float is broadcasted to ymm (256b),
2350 * broadcasting decorator must be {1to4}.
2352 return MERR_BRNUMMISMATCH
;
2358 return MERR_OPSIZEMISSING
;
2361 * Check operand sizes
2363 if (itemp_has(itemp
, IF_SM
) || itemp_has(itemp
, IF_SM2
)) {
2364 oprs
= (itemp_has(itemp
, IF_SM2
) ? 2 : itemp
->operands
);
2365 for (i
= 0; i
< oprs
; i
++) {
2366 asize
= itemp
->opd
[i
] & SIZE_MASK
;
2368 for (i
= 0; i
< oprs
; i
++)
2374 oprs
= itemp
->operands
;
2377 for (i
= 0; i
< itemp
->operands
; i
++) {
2378 if (!(itemp
->opd
[i
] & SIZE_MASK
) &&
2379 (instruction
->oprs
[i
].type
& SIZE_MASK
& ~size
[i
]))
2380 return MERR_OPSIZEMISMATCH
;
2384 * Check template is okay at the set cpu level
2386 if (iflag_cmp_cpu_level(&insns_flags
[itemp
->iflag_idx
], &cpu
) > 0)
2390 * Verify the appropriate long mode flag.
2392 if (itemp_has(itemp
, (bits
== 64 ? IF_NOLONG
: IF_LONG
)))
2393 return MERR_BADMODE
;
2396 * If we have a HLE prefix, look for the NOHLE flag
2398 if (itemp_has(itemp
, IF_NOHLE
) &&
2399 (has_prefix(instruction
, PPS_REP
, P_XACQUIRE
) ||
2400 has_prefix(instruction
, PPS_REP
, P_XRELEASE
)))
2404 * Check if special handling needed for Jumps
2406 if ((itemp
->code
[0] & ~1) == 0370)
2410 * Check if BND prefix is allowed.
2411 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2413 if (!itemp_has(itemp
, IF_BND
) &&
2414 (has_prefix(instruction
, PPS_REP
, P_BND
) ||
2415 has_prefix(instruction
, PPS_REP
, P_NOBND
)))
2417 else if (itemp_has(itemp
, IF_BND
) &&
2418 (has_prefix(instruction
, PPS_REP
, P_REPNE
) ||
2419 has_prefix(instruction
, PPS_REP
, P_REPNZ
)))
2420 return MERR_BADREPNE
;
2426 * Check if ModR/M.mod should/can be 01.
2427 * - EAF_BYTEOFFS is set
2428 * - offset can fit in a byte when EVEX is not used
2429 * - offset can be compressed when EVEX is used
2431 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2432 (o >= -128 && o <= 127 && \
2433 seg == NO_SEG && !forw_ref && \
2434 !(input->eaflags & EAF_WORDOFFS) && \
2435 !(ins->rex & REX_EV)) || \
2436 (ins->rex & REX_EV && \
2437 is_disp8n(input, ins, &output->disp8)))
2439 static enum ea_type
process_ea(operand
*input
, ea
*output
, int bits
,
2440 int rfield
, opflags_t rflags
, insn
*ins
)
2442 bool forw_ref
= !!(input
->opflags
& OPFLAG_UNKNOWN
);
2443 int addrbits
= ins
->addr_size
;
2444 int eaflags
= input
->eaflags
;
2446 output
->type
= EA_SCALAR
;
2447 output
->rip
= false;
2450 /* REX flags for the rfield operand */
2451 output
->rex
|= rexflags(rfield
, rflags
, REX_R
| REX_P
| REX_W
| REX_H
);
2452 /* EVEX.R' flag for the REG operand */
2453 ins
->evex_p
[0] |= evexflags(rfield
, 0, EVEX_P0RP
, 0);
2455 if (is_class(REGISTER
, input
->type
)) {
2457 * It's a direct register.
2459 if (!is_register(input
->basereg
))
2462 if (!is_reg_class(REG_EA
, input
->basereg
))
2465 /* broadcasting is not available with a direct register operand. */
2466 if (input
->decoflags
& BRDCAST_MASK
) {
2467 nasm_error(ERR_NONFATAL
, "Broadcasting not allowed from a register");
2471 output
->rex
|= op_rexflags(input
, REX_B
| REX_P
| REX_W
| REX_H
);
2472 ins
->evex_p
[0] |= op_evexflags(input
, EVEX_P0X
, 0);
2473 output
->sib_present
= false; /* no SIB necessary */
2474 output
->bytes
= 0; /* no offset necessary either */
2475 output
->modrm
= GEN_MODRM(3, rfield
, nasm_regvals
[input
->basereg
]);
2478 * It's a memory reference.
2481 /* Embedded rounding or SAE is not available with a mem ref operand. */
2482 if (input
->decoflags
& (ER
| SAE
)) {
2483 nasm_error(ERR_NONFATAL
,
2484 "Embedded rounding is available only with reg-reg op.");
2488 if (input
->basereg
== -1 &&
2489 (input
->indexreg
== -1 || input
->scale
== 0)) {
2491 * It's a pure offset.
2493 if (bits
== 64 && ((input
->type
& IP_REL
) == IP_REL
) &&
2494 input
->segment
== NO_SEG
) {
2495 nasm_error(ERR_WARNING
| ERR_PASS1
, "absolute address can not be RIP-relative");
2496 input
->type
&= ~IP_REL
;
2497 input
->type
|= MEMORY
;
2501 !(IP_REL
& ~input
->type
) && (eaflags
& EAF_MIB
)) {
2502 nasm_error(ERR_NONFATAL
, "RIP-relative addressing is prohibited for mib.");
2506 if (eaflags
& EAF_BYTEOFFS
||
2507 (eaflags
& EAF_WORDOFFS
&&
2508 input
->disp_size
!= (addrbits
!= 16 ? 32 : 16))) {
2509 nasm_error(ERR_WARNING
| ERR_PASS1
, "displacement size ignored on absolute address");
2512 if (bits
== 64 && (~input
->type
& IP_REL
)) {
2513 output
->sib_present
= true;
2514 output
->sib
= GEN_SIB(0, 4, 5);
2516 output
->modrm
= GEN_MODRM(0, rfield
, 4);
2517 output
->rip
= false;
2519 output
->sib_present
= false;
2520 output
->bytes
= (addrbits
!= 16 ? 4 : 2);
2521 output
->modrm
= GEN_MODRM(0, rfield
, (addrbits
!= 16 ? 5 : 6));
2522 output
->rip
= bits
== 64;
2526 * It's an indirection.
2528 int i
= input
->indexreg
, b
= input
->basereg
, s
= input
->scale
;
2529 int32_t seg
= input
->segment
;
2530 int hb
= input
->hintbase
, ht
= input
->hinttype
;
2531 int t
, it
, bt
; /* register numbers */
2532 opflags_t x
, ix
, bx
; /* register flags */
2535 i
= -1; /* make this easy, at least */
2537 if (is_register(i
)) {
2538 it
= nasm_regvals
[i
];
2539 ix
= nasm_reg_flags
[i
];
2545 if (is_register(b
)) {
2546 bt
= nasm_regvals
[b
];
2547 bx
= nasm_reg_flags
[b
];
2553 /* if either one are a vector register... */
2554 if ((ix
|bx
) & (XMMREG
|YMMREG
|ZMMREG
) & ~REG_EA
) {
2555 opflags_t sok
= BITS32
| BITS64
;
2556 int32_t o
= input
->offset
;
2557 int mod
, scale
, index
, base
;
2560 * For a vector SIB, one has to be a vector and the other,
2561 * if present, a GPR. The vector must be the index operand.
2563 if (it
== -1 || (bx
& (XMMREG
|YMMREG
|ZMMREG
) & ~REG_EA
)) {
2569 t
= bt
, bt
= it
, it
= t
;
2570 x
= bx
, bx
= ix
, ix
= x
;
2576 if (!(REG64
& ~bx
) || !(REG32
& ~bx
))
2583 * While we're here, ensure the user didn't specify
2586 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2589 if (addrbits
== 16 ||
2590 (addrbits
== 32 && !(sok
& BITS32
)) ||
2591 (addrbits
== 64 && !(sok
& BITS64
)))
2594 output
->type
= ((ix
& ZMMREG
& ~REG_EA
) ? EA_ZMMVSIB
2595 : ((ix
& YMMREG
& ~REG_EA
)
2596 ? EA_YMMVSIB
: EA_XMMVSIB
));
2598 output
->rex
|= rexflags(it
, ix
, REX_X
);
2599 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2600 ins
->evex_p
[2] |= evexflags(it
, 0, EVEX_P2VP
, 2);
2602 index
= it
& 7; /* it is known to be != -1 */
2617 default: /* then what the smeg is it? */
2618 goto err
; /* panic */
2626 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2627 seg
== NO_SEG
&& !forw_ref
&&
2628 !(eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2630 else if (IS_MOD_01())
2636 output
->sib_present
= true;
2637 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2638 output
->modrm
= GEN_MODRM(mod
, rfield
, 4);
2639 output
->sib
= GEN_SIB(scale
, index
, base
);
2640 } else if ((ix
|bx
) & (BITS32
|BITS64
)) {
2642 * it must be a 32/64-bit memory reference. Firstly we have
2643 * to check that all registers involved are type E/Rxx.
2645 opflags_t sok
= BITS32
| BITS64
;
2646 int32_t o
= input
->offset
;
2649 if (!(REG64
& ~ix
) || !(REG32
& ~ix
))
2657 goto err
; /* Invalid register */
2658 if (~sok
& bx
& SIZE_MASK
)
2659 goto err
; /* Invalid size */
2664 * While we're here, ensure the user didn't specify
2667 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2670 if (addrbits
== 16 ||
2671 (addrbits
== 32 && !(sok
& BITS32
)) ||
2672 (addrbits
== 64 && !(sok
& BITS64
)))
2675 /* now reorganize base/index */
2676 if (s
== 1 && bt
!= it
&& bt
!= -1 && it
!= -1 &&
2677 ((hb
== b
&& ht
== EAH_NOTBASE
) ||
2678 (hb
== i
&& ht
== EAH_MAKEBASE
))) {
2679 /* swap if hints say so */
2680 t
= bt
, bt
= it
, it
= t
;
2681 x
= bx
, bx
= ix
, ix
= x
;
2684 if (bt
== -1 && s
== 1 && !(hb
== i
&& ht
== EAH_NOTBASE
)) {
2685 /* make single reg base, unless hint */
2686 bt
= it
, bx
= ix
, it
= -1, ix
= 0;
2688 if (eaflags
& EAF_MIB
) {
2689 /* only for mib operands */
2690 if (it
== -1 && (hb
== b
&& ht
== EAH_NOTBASE
)) {
2692 * make a single reg index [reg*1].
2693 * gas uses this form for an explicit index register.
2695 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2697 if ((ht
== EAH_SUMMED
) && bt
== -1) {
2698 /* separate once summed index into [base, index] */
2699 bt
= it
, bx
= ix
, s
--;
2702 if (((s
== 2 && it
!= REG_NUM_ESP
&&
2703 (!(eaflags
& EAF_TIMESTWO
) || (ht
== EAH_SUMMED
))) ||
2704 s
== 3 || s
== 5 || s
== 9) && bt
== -1) {
2705 /* convert 3*EAX to EAX+2*EAX */
2706 bt
= it
, bx
= ix
, s
--;
2708 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
&&
2709 (eaflags
& EAF_TIMESTWO
) &&
2710 (hb
== b
&& ht
== EAH_NOTBASE
)) {
2712 * convert [NOSPLIT EAX*1]
2713 * to sib format with 0x0 displacement - [EAX*1+0].
2715 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2718 if (s
== 1 && it
== REG_NUM_ESP
) {
2719 /* swap ESP into base if scale is 1 */
2720 t
= it
, it
= bt
, bt
= t
;
2721 x
= ix
, ix
= bx
, bx
= x
;
2723 if (it
== REG_NUM_ESP
||
2724 (s
!= 1 && s
!= 2 && s
!= 4 && s
!= 8 && it
!= -1))
2725 goto err
; /* wrong, for various reasons */
2727 output
->rex
|= rexflags(it
, ix
, REX_X
);
2728 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2730 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
) {
2739 if (rm
!= REG_NUM_EBP
&& o
== 0 &&
2740 seg
== NO_SEG
&& !forw_ref
&&
2741 !(eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2743 else if (IS_MOD_01())
2749 output
->sib_present
= false;
2750 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2751 output
->modrm
= GEN_MODRM(mod
, rfield
, rm
);
2754 int mod
, scale
, index
, base
;
2774 default: /* then what the smeg is it? */
2775 goto err
; /* panic */
2783 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2784 seg
== NO_SEG
&& !forw_ref
&&
2785 !(eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2787 else if (IS_MOD_01())
2793 output
->sib_present
= true;
2794 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2795 output
->modrm
= GEN_MODRM(mod
, rfield
, 4);
2796 output
->sib
= GEN_SIB(scale
, index
, base
);
2798 } else { /* it's 16-bit */
2800 int16_t o
= input
->offset
;
2802 /* check for 64-bit long mode */
2806 /* check all registers are BX, BP, SI or DI */
2807 if ((b
!= -1 && b
!= R_BP
&& b
!= R_BX
&& b
!= R_SI
&& b
!= R_DI
) ||
2808 (i
!= -1 && i
!= R_BP
&& i
!= R_BX
&& i
!= R_SI
&& i
!= R_DI
))
2811 /* ensure the user didn't specify DWORD/QWORD */
2812 if (input
->disp_size
== 32 || input
->disp_size
== 64)
2815 if (s
!= 1 && i
!= -1)
2816 goto err
; /* no can do, in 16-bit EA */
2817 if (b
== -1 && i
!= -1) {
2822 if ((b
== R_SI
|| b
== R_DI
) && i
!= -1) {
2827 /* have BX/BP as base, SI/DI index */
2829 goto err
; /* shouldn't ever happen, in theory */
2830 if (i
!= -1 && b
!= -1 &&
2831 (i
== R_BP
|| i
== R_BX
|| b
== R_SI
|| b
== R_DI
))
2832 goto err
; /* invalid combinations */
2833 if (b
== -1) /* pure offset: handled above */
2834 goto err
; /* so if it gets to here, panic! */
2838 switch (i
* 256 + b
) {
2839 case R_SI
* 256 + R_BX
:
2842 case R_DI
* 256 + R_BX
:
2845 case R_SI
* 256 + R_BP
:
2848 case R_DI
* 256 + R_BP
:
2866 if (rm
== -1) /* can't happen, in theory */
2867 goto err
; /* so panic if it does */
2869 if (o
== 0 && seg
== NO_SEG
&& !forw_ref
&& rm
!= 6 &&
2870 !(eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2872 else if (IS_MOD_01())
2877 output
->sib_present
= false; /* no SIB - it's 16-bit */
2878 output
->bytes
= mod
; /* bytes of offset needed */
2879 output
->modrm
= GEN_MODRM(mod
, rfield
, rm
);
2884 output
->size
= 1 + output
->sib_present
+ output
->bytes
;
2885 return output
->type
;
2888 return output
->type
= EA_INVALID
;
2891 static void add_asp(insn
*ins
, int addrbits
)
2896 valid
= (addrbits
== 64) ? 64|32 : 32|16;
2898 switch (ins
->prefixes
[PPS_ASIZE
]) {
2909 valid
&= (addrbits
== 32) ? 16 : 32;
2915 for (j
= 0; j
< ins
->operands
; j
++) {
2916 if (is_class(MEMORY
, ins
->oprs
[j
].type
)) {
2919 /* Verify as Register */
2920 if (!is_register(ins
->oprs
[j
].indexreg
))
2923 i
= nasm_reg_flags
[ins
->oprs
[j
].indexreg
];
2925 /* Verify as Register */
2926 if (!is_register(ins
->oprs
[j
].basereg
))
2929 b
= nasm_reg_flags
[ins
->oprs
[j
].basereg
];
2931 if (ins
->oprs
[j
].scale
== 0)
2935 int ds
= ins
->oprs
[j
].disp_size
;
2936 if ((addrbits
!= 64 && ds
> 8) ||
2937 (addrbits
== 64 && ds
== 16))
2957 if (valid
& addrbits
) {
2958 ins
->addr_size
= addrbits
;
2959 } else if (valid
& ((addrbits
== 32) ? 16 : 32)) {
2960 /* Add an address size prefix */
2961 ins
->prefixes
[PPS_ASIZE
] = (addrbits
== 32) ? P_A16
: P_A32
;;
2962 ins
->addr_size
= (addrbits
== 32) ? 16 : 32;
2965 nasm_error(ERR_NONFATAL
, "impossible combination of address sizes");
2966 ins
->addr_size
= addrbits
; /* Error recovery */
2969 defdisp
= ins
->addr_size
== 16 ? 16 : 32;
2971 for (j
= 0; j
< ins
->operands
; j
++) {
2972 if (!(MEM_OFFS
& ~ins
->oprs
[j
].type
) &&
2973 (ins
->oprs
[j
].disp_size
? ins
->oprs
[j
].disp_size
: defdisp
) != ins
->addr_size
) {
2975 * mem_offs sizes must match the address size; if not,
2976 * strip the MEM_OFFS bit and match only EA instructions
2978 ins
->oprs
[j
].type
&= ~(MEM_OFFS
& ~MEMORY
);