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assemble: Emit signed relocations where appropriate
[nasm.git] / assemble.c
blob52a352fa8a1eabbfe53403f320f489c853e46382
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
71 *
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
78 * cc 000 0mm
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
80 * and wlp is:
81 * 00 wwl lpp
82 * [l0] ll = 0 (.128, .lz)
83 * [l1] ll = 1 (.256)
84 * [l2] ll = 2 (.512)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
86 *
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
91 *
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
94 * [f3] pp = 2
95 * [f2] pp = 3
96 *
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
99 *
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
105 *
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
108 * 00 wwl lpp
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
112 *
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
117 *
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
119 *
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
170 */
171
172 #include "compiler.h"
173
174 #include <stdio.h>
175 #include <string.h>
176 #include <stdlib.h>
177 #include <inttypes.h>
178
179 #include "nasm.h"
180 #include "nasmlib.h"
181 #include "assemble.h"
182 #include "insns.h"
183 #include "tables.h"
184 #include "disp8.h"
185
186 enum match_result {
187 /*
188 * Matching errors. These should be sorted so that more specific
189 * errors come later in the sequence.
190 */
191 MERR_INVALOP,
192 MERR_OPSIZEMISSING,
193 MERR_OPSIZEMISMATCH,
194 MERR_BRNUMMISMATCH,
195 MERR_BADCPU,
196 MERR_BADMODE,
197 MERR_BADHLE,
198 MERR_ENCMISMATCH,
199 MERR_BADBND,
200 /*
201 * Matching success; the conditional ones first
202 */
203 MOK_JUMP, /* Matching OK but needs jmp_match() */
204 MOK_GOOD /* Matching unconditionally OK */
205 };
206
207 typedef struct {
208 enum ea_type type; /* what kind of EA is this? */
209 int sib_present; /* is a SIB byte necessary? */
210 int bytes; /* # of bytes of offset needed */
211 int size; /* lazy - this is sib+bytes+1 */
212 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
213 int8_t disp8; /* compressed displacement for EVEX */
214 } ea;
215
216 #define GEN_SIB(scale, index, base) \
217 (((scale) << 6) | ((index) << 3) | ((base)))
218
219 #define GEN_MODRM(mod, reg, rm) \
220 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
221
222 static iflag_t cpu; /* cpu level received from nasm.c */
223 static efunc errfunc;
224 static struct ofmt *outfmt;
225 static ListGen *list;
226
227 static int64_t calcsize(int32_t, int64_t, int, insn *,
228 const struct itemplate *);
229 static void gencode(int32_t segment, int64_t offset, int bits,
230 insn * ins, const struct itemplate *temp,
231 int64_t insn_end);
232 static enum match_result find_match(const struct itemplate **tempp,
233 insn *instruction,
234 int32_t segment, int64_t offset, int bits);
235 static enum match_result matches(const struct itemplate *, insn *, int bits);
236 static opflags_t regflag(const operand *);
237 static int32_t regval(const operand *);
238 static int rexflags(int, opflags_t, int);
239 static int op_rexflags(const operand *, int);
240 static int op_evexflags(const operand *, int, uint8_t);
241 static void add_asp(insn *, int);
242
243 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
244
245 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
246 {
247 return ins->prefixes[pos] == prefix;
248 }
249
250 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
251 {
252 if (ins->prefixes[pos])
253 errfunc(ERR_NONFATAL, "invalid %s prefix",
254 prefix_name(ins->prefixes[pos]));
255 }
256
257 static const char *size_name(int size)
258 {
259 switch (size) {
260 case 1:
261 return "byte";
262 case 2:
263 return "word";
264 case 4:
265 return "dword";
266 case 8:
267 return "qword";
268 case 10:
269 return "tword";
270 case 16:
271 return "oword";
272 case 32:
273 return "yword";
274 case 64:
275 return "zword";
276 default:
277 return "???";
278 }
279 }
280
281 static void warn_overflow(int pass, int size)
282 {
283 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
284 "%s data exceeds bounds", size_name(size));
285 }
286
287 static void warn_overflow_const(int64_t data, int size)
288 {
289 if (overflow_general(data, size))
290 warn_overflow(ERR_PASS1, size);
291 }
292
293 static void warn_overflow_opd(const struct operand *o, int size)
294 {
295 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
296 if (overflow_general(o->offset, size))
297 warn_overflow(ERR_PASS2, size);
298 }
299 }
300
301 /*
302 * This routine wrappers the real output format's output routine,
303 * in order to pass a copy of the data off to the listing file
304 * generator at the same time.
305 */
306 static void out(int64_t offset, int32_t segto, const void *data,
307 enum out_type type, uint64_t size,
308 int32_t segment, int32_t wrt)
309 {
310 static int32_t lineno = 0; /* static!!! */
311 static char *lnfname = NULL;
312 uint8_t p[8];
313
314 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
315 /*
316 * This is a non-relocated address, and we're going to
317 * convert it into RAWDATA format.
318 */
319 uint8_t *q = p;
320
321 size = abs((int)size);
322 if (size > 8) {
323 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
324 return;
325 }
326
327 WRITEADDR(q, *(int64_t *)data, size);
328 data = p;
329 type = OUT_RAWDATA;
330 }
331
332 list->output(offset, data, type, size);
333
334 /*
335 * this call to src_get determines when we call the
336 * debug-format-specific "linenum" function
337 * it updates lineno and lnfname to the current values
338 * returning 0 if "same as last time", -2 if lnfname
339 * changed, and the amount by which lineno changed,
340 * if it did. thus, these variables must be static
341 */
342
343 if (src_get(&lineno, &lnfname))
344 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
345
346 outfmt->output(segto, data, type, size, segment, wrt);
347 }
348
349 static void out_imm8(int64_t offset, int32_t segment,
350 struct operand *opx, int asize)
351 {
352 if (opx->segment != NO_SEG) {
353 uint64_t data = opx->offset;
354 out(offset, segment, &data, OUT_ADDRESS, asize, opx->segment, opx->wrt);
355 } else {
356 uint8_t byte = opx->offset;
357 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
358 }
359 }
360
361 static bool jmp_match(int32_t segment, int64_t offset, int bits,
362 insn * ins, const struct itemplate *temp)
363 {
364 int64_t isize;
365 const uint8_t *code = temp->code;
366 uint8_t c = code[0];
367 bool is_byte;
368
369 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
370 return false;
371 if (!optimizing)
372 return false;
373 if (optimizing < 0 && c == 0371)
374 return false;
375
376 isize = calcsize(segment, offset, bits, ins, temp);
377
378 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
379 /* Be optimistic in pass 1 */
380 return true;
381
382 if (ins->oprs[0].segment != segment)
383 return false;
384
385 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
386 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
387
388 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
389 /* jmp short (opcode eb) cannot be used with bnd prefix. */
390 ins->prefixes[PPS_REP] = P_none;
391 }
392
393 return is_byte;
394 }
395
396 int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
397 insn * instruction, struct ofmt *output, efunc error,
398 ListGen * listgen)
399 {
400 const struct itemplate *temp;
401 int j;
402 enum match_result m;
403 int64_t insn_end;
404 int32_t itimes;
405 int64_t start = offset;
406 int64_t wsize; /* size for DB etc. */
407
408 errfunc = error; /* to pass to other functions */
409 cpu = cp;
410 outfmt = output; /* likewise */
411 list = listgen; /* and again */
412
413 wsize = idata_bytes(instruction->opcode);
414 if (wsize == -1)
415 return 0;
416
417 if (wsize) {
418 extop *e;
419 int32_t t = instruction->times;
420 if (t < 0)
421 errfunc(ERR_PANIC,
422 "instruction->times < 0 (%ld) in assemble()", t);
423
424 while (t--) { /* repeat TIMES times */
425 list_for_each(e, instruction->eops) {
426 if (e->type == EOT_DB_NUMBER) {
427 if (wsize > 8) {
428 errfunc(ERR_NONFATAL,
429 "integer supplied to a DT, DO or DY"
430 " instruction");
431 } else {
432 out(offset, segment, &e->offset,
433 OUT_ADDRESS, wsize, e->segment, e->wrt);
434 offset += wsize;
435 }
436 } else if (e->type == EOT_DB_STRING ||
437 e->type == EOT_DB_STRING_FREE) {
438 int align;
439
440 out(offset, segment, e->stringval,
441 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
442 align = e->stringlen % wsize;
443
444 if (align) {
445 align = wsize - align;
446 out(offset, segment, zero_buffer,
447 OUT_RAWDATA, align, NO_SEG, NO_SEG);
448 }
449 offset += e->stringlen + align;
450 }
451 }
452 if (t > 0 && t == instruction->times - 1) {
453 /*
454 * Dummy call to list->output to give the offset to the
455 * listing module.
456 */
457 list->output(offset, NULL, OUT_RAWDATA, 0);
458 list->uplevel(LIST_TIMES);
459 }
460 }
461 if (instruction->times > 1)
462 list->downlevel(LIST_TIMES);
463 return offset - start;
464 }
465
466 if (instruction->opcode == I_INCBIN) {
467 const char *fname = instruction->eops->stringval;
468 FILE *fp;
469
470 fp = fopen(fname, "rb");
471 if (!fp) {
472 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
473 fname);
474 } else if (fseek(fp, 0L, SEEK_END) < 0) {
475 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
476 fname);
477 fclose(fp);
478 } else {
479 static char buf[4096];
480 size_t t = instruction->times;
481 size_t base = 0;
482 size_t len;
483
484 len = ftell(fp);
485 if (instruction->eops->next) {
486 base = instruction->eops->next->offset;
487 len -= base;
488 if (instruction->eops->next->next &&
489 len > (size_t)instruction->eops->next->next->offset)
490 len = (size_t)instruction->eops->next->next->offset;
491 }
492 /*
493 * Dummy call to list->output to give the offset to the
494 * listing module.
495 */
496 list->output(offset, NULL, OUT_RAWDATA, 0);
497 list->uplevel(LIST_INCBIN);
498 while (t--) {
499 size_t l;
500
501 fseek(fp, base, SEEK_SET);
502 l = len;
503 while (l > 0) {
504 int32_t m;
505 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
506 if (!m) {
507 /*
508 * This shouldn't happen unless the file
509 * actually changes while we are reading
510 * it.
511 */
512 error(ERR_NONFATAL,
513 "`incbin': unexpected EOF while"
514 " reading file `%s'", fname);
515 t = 0; /* Try to exit cleanly */
516 break;
517 }
518 out(offset, segment, buf, OUT_RAWDATA, m,
519 NO_SEG, NO_SEG);
520 l -= m;
521 }
522 }
523 list->downlevel(LIST_INCBIN);
524 if (instruction->times > 1) {
525 /*
526 * Dummy call to list->output to give the offset to the
527 * listing module.
528 */
529 list->output(offset, NULL, OUT_RAWDATA, 0);
530 list->uplevel(LIST_TIMES);
531 list->downlevel(LIST_TIMES);
532 }
533 fclose(fp);
534 return instruction->times * len;
535 }
536 return 0; /* if we're here, there's an error */
537 }
538
539 /* Check to see if we need an address-size prefix */
540 add_asp(instruction, bits);
541
542 m = find_match(&temp, instruction, segment, offset, bits);
543
544 if (m == MOK_GOOD) {
545 /* Matches! */
546 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
547 itimes = instruction->times;
548 if (insn_size < 0) /* shouldn't be, on pass two */
549 error(ERR_PANIC, "errors made it through from pass one");
550 else
551 while (itimes--) {
552 for (j = 0; j < MAXPREFIX; j++) {
553 uint8_t c = 0;
554 switch (instruction->prefixes[j]) {
555 case P_WAIT:
556 c = 0x9B;
557 break;
558 case P_LOCK:
559 c = 0xF0;
560 break;
561 case P_REPNE:
562 case P_REPNZ:
563 case P_XACQUIRE:
564 case P_BND:
565 c = 0xF2;
566 break;
567 case P_REPE:
568 case P_REPZ:
569 case P_REP:
570 case P_XRELEASE:
571 c = 0xF3;
572 break;
573 case R_CS:
574 if (bits == 64) {
575 error(ERR_WARNING | ERR_PASS2,
576 "cs segment base generated, but will be ignored in 64-bit mode");
577 }
578 c = 0x2E;
579 break;
580 case R_DS:
581 if (bits == 64) {
582 error(ERR_WARNING | ERR_PASS2,
583 "ds segment base generated, but will be ignored in 64-bit mode");
584 }
585 c = 0x3E;
586 break;
587 case R_ES:
588 if (bits == 64) {
589 error(ERR_WARNING | ERR_PASS2,
590 "es segment base generated, but will be ignored in 64-bit mode");
591 }
592 c = 0x26;
593 break;
594 case R_FS:
595 c = 0x64;
596 break;
597 case R_GS:
598 c = 0x65;
599 break;
600 case R_SS:
601 if (bits == 64) {
602 error(ERR_WARNING | ERR_PASS2,
603 "ss segment base generated, but will be ignored in 64-bit mode");
604 }
605 c = 0x36;
606 break;
607 case R_SEGR6:
608 case R_SEGR7:
609 error(ERR_NONFATAL,
610 "segr6 and segr7 cannot be used as prefixes");
611 break;
612 case P_A16:
613 if (bits == 64) {
614 error(ERR_NONFATAL,
615 "16-bit addressing is not supported "
616 "in 64-bit mode");
617 } else if (bits != 16)
618 c = 0x67;
619 break;
620 case P_A32:
621 if (bits != 32)
622 c = 0x67;
623 break;
624 case P_A64:
625 if (bits != 64) {
626 error(ERR_NONFATAL,
627 "64-bit addressing is only supported "
628 "in 64-bit mode");
629 }
630 break;
631 case P_ASP:
632 c = 0x67;
633 break;
634 case P_O16:
635 if (bits != 16)
636 c = 0x66;
637 break;
638 case P_O32:
639 if (bits == 16)
640 c = 0x66;
641 break;
642 case P_O64:
643 /* REX.W */
644 break;
645 case P_OSP:
646 c = 0x66;
647 break;
648 case P_EVEX:
649 /* EVEX */
650 break;
651 case P_none:
652 break;
653 default:
654 error(ERR_PANIC, "invalid instruction prefix");
655 }
656 if (c != 0) {
657 out(offset, segment, &c, OUT_RAWDATA, 1,
658 NO_SEG, NO_SEG);
659 offset++;
660 }
661 }
662 insn_end = offset + insn_size;
663 gencode(segment, offset, bits, instruction,
664 temp, insn_end);
665 offset += insn_size;
666 if (itimes > 0 && itimes == instruction->times - 1) {
667 /*
668 * Dummy call to list->output to give the offset to the
669 * listing module.
670 */
671 list->output(offset, NULL, OUT_RAWDATA, 0);
672 list->uplevel(LIST_TIMES);
673 }
674 }
675 if (instruction->times > 1)
676 list->downlevel(LIST_TIMES);
677 return offset - start;
678 } else {
679 /* No match */
680 switch (m) {
681 case MERR_OPSIZEMISSING:
682 error(ERR_NONFATAL, "operation size not specified");
683 break;
684 case MERR_OPSIZEMISMATCH:
685 error(ERR_NONFATAL, "mismatch in operand sizes");
686 break;
687 case MERR_BRNUMMISMATCH:
688 error(ERR_NONFATAL,
689 "mismatch in the number of broadcasting elements");
690 break;
691 case MERR_BADCPU:
692 error(ERR_NONFATAL, "no instruction for this cpu level");
693 break;
694 case MERR_BADMODE:
695 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
696 bits);
697 break;
698 case MERR_BADBND:
699 error(ERR_NONFATAL, "bnd prefix is not allowed");
700 break;
701 default:
702 error(ERR_NONFATAL,
703 "invalid combination of opcode and operands");
704 break;
705 }
706 }
707 return 0;
708 }
709
710 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
711 insn * instruction, efunc error)
712 {
713 const struct itemplate *temp;
714 enum match_result m;
715
716 errfunc = error; /* to pass to other functions */
717 cpu = cp;
718
719 if (instruction->opcode == I_none)
720 return 0;
721
722 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
723 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
724 instruction->opcode == I_DT || instruction->opcode == I_DO ||
725 instruction->opcode == I_DY) {
726 extop *e;
727 int32_t isize, osize, wsize;
728
729 isize = 0;
730 wsize = idata_bytes(instruction->opcode);
731
732 list_for_each(e, instruction->eops) {
733 int32_t align;
734
735 osize = 0;
736 if (e->type == EOT_DB_NUMBER) {
737 osize = 1;
738 warn_overflow_const(e->offset, wsize);
739 } else if (e->type == EOT_DB_STRING ||
740 e->type == EOT_DB_STRING_FREE)
741 osize = e->stringlen;
742
743 align = (-osize) % wsize;
744 if (align < 0)
745 align += wsize;
746 isize += osize + align;
747 }
748 return isize * instruction->times;
749 }
750
751 if (instruction->opcode == I_INCBIN) {
752 const char *fname = instruction->eops->stringval;
753 FILE *fp;
754 int64_t val = 0;
755 size_t len;
756
757 fp = fopen(fname, "rb");
758 if (!fp)
759 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
760 fname);
761 else if (fseek(fp, 0L, SEEK_END) < 0)
762 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
763 fname);
764 else {
765 len = ftell(fp);
766 if (instruction->eops->next) {
767 len -= instruction->eops->next->offset;
768 if (instruction->eops->next->next &&
769 len > (size_t)instruction->eops->next->next->offset) {
770 len = (size_t)instruction->eops->next->next->offset;
771 }
772 }
773 val = instruction->times * len;
774 }
775 if (fp)
776 fclose(fp);
777 return val;
778 }
779
780 /* Check to see if we need an address-size prefix */
781 add_asp(instruction, bits);
782
783 m = find_match(&temp, instruction, segment, offset, bits);
784 if (m == MOK_GOOD) {
785 /* we've matched an instruction. */
786 int64_t isize;
787 int j;
788
789 isize = calcsize(segment, offset, bits, instruction, temp);
790 if (isize < 0)
791 return -1;
792 for (j = 0; j < MAXPREFIX; j++) {
793 switch (instruction->prefixes[j]) {
794 case P_A16:
795 if (bits != 16)
796 isize++;
797 break;
798 case P_A32:
799 if (bits != 32)
800 isize++;
801 break;
802 case P_O16:
803 if (bits != 16)
804 isize++;
805 break;
806 case P_O32:
807 if (bits == 16)
808 isize++;
809 break;
810 case P_A64:
811 case P_O64:
812 case P_EVEX:
813 case P_none:
814 break;
815 default:
816 isize++;
817 break;
818 }
819 }
820 return isize * instruction->times;
821 } else {
822 return -1; /* didn't match any instruction */
823 }
824 }
825
826 static void bad_hle_warn(const insn * ins, uint8_t hleok)
827 {
828 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
829 enum whatwarn { w_none, w_lock, w_inval } ww;
830 static const enum whatwarn warn[2][4] =
831 {
832 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
833 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
834 };
835 unsigned int n;
836
837 n = (unsigned int)rep_pfx - P_XACQUIRE;
838 if (n > 1)
839 return; /* Not XACQUIRE/XRELEASE */
840
841 ww = warn[n][hleok];
842 if (!is_class(MEMORY, ins->oprs[0].type))
843 ww = w_inval; /* HLE requires operand 0 to be memory */
844
845 switch (ww) {
846 case w_none:
847 break;
848
849 case w_lock:
850 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
851 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
852 "%s with this instruction requires lock",
853 prefix_name(rep_pfx));
854 }
855 break;
856
857 case w_inval:
858 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
859 "%s invalid with this instruction",
860 prefix_name(rep_pfx));
861 break;
862 }
863 }
864
865 /* Common construct */
866 #define case3(x) case (x): case (x)+1: case (x)+2
867 #define case4(x) case3(x): case (x)+3
868
869 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
870 insn * ins, const struct itemplate *temp)
871 {
872 const uint8_t *codes = temp->code;
873 int64_t length = 0;
874 uint8_t c;
875 int rex_mask = ~0;
876 int op1, op2;
877 struct operand *opx;
878 uint8_t opex = 0;
879 enum ea_type eat;
880 uint8_t hleok = 0;
881 bool lockcheck = true;
882 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
883
884 ins->rex = 0; /* Ensure REX is reset */
885 eat = EA_SCALAR; /* Expect a scalar EA */
886 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
887
888 if (ins->prefixes[PPS_OSIZE] == P_O64)
889 ins->rex |= REX_W;
890
891 (void)segment; /* Don't warn that this parameter is unused */
892 (void)offset; /* Don't warn that this parameter is unused */
893
894 while (*codes) {
895 c = *codes++;
896 op1 = (c & 3) + ((opex & 1) << 2);
897 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
898 opx = &ins->oprs[op1];
899 opex = 0; /* For the next iteration */
900
901 switch (c) {
902 case4(01):
903 codes += c, length += c;
904 break;
905
906 case3(05):
907 opex = c;
908 break;
909
910 case4(010):
911 ins->rex |=
912 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
913 codes++, length++;
914 break;
915
916 case4(014):
917 /* this is an index reg of MIB operand */
918 mib_index = opx->basereg;
919 break;
920
921 case4(020):
922 case4(024):
923 length++;
924 break;
925
926 case4(030):
927 length += 2;
928 break;
929
930 case4(034):
931 if (opx->type & (BITS16 | BITS32 | BITS64))
932 length += (opx->type & BITS16) ? 2 : 4;
933 else
934 length += (bits == 16) ? 2 : 4;
935 break;
936
937 case4(040):
938 length += 4;
939 break;
940
941 case4(044):
942 length += ins->addr_size >> 3;
943 break;
944
945 case4(050):
946 length++;
947 break;
948
949 case4(054):
950 length += 8; /* MOV reg64/imm */
951 break;
952
953 case4(060):
954 length += 2;
955 break;
956
957 case4(064):
958 if (opx->type & (BITS16 | BITS32 | BITS64))
959 length += (opx->type & BITS16) ? 2 : 4;
960 else
961 length += (bits == 16) ? 2 : 4;
962 break;
963
964 case4(070):
965 length += 4;
966 break;
967
968 case4(074):
969 length += 2;
970 break;
971
972 case 0172:
973 case 0173:
974 codes++;
975 length++;
976 break;
977
978 case4(0174):
979 length++;
980 break;
981
982 case4(0240):
983 ins->rex |= REX_EV;
984 ins->vexreg = regval(opx);
985 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
986 ins->vex_cm = *codes++;
987 ins->vex_wlp = *codes++;
988 ins->evex_tuple = (*codes++ - 0300);
989 break;
990
991 case 0250:
992 ins->rex |= REX_EV;
993 ins->vexreg = 0;
994 ins->vex_cm = *codes++;
995 ins->vex_wlp = *codes++;
996 ins->evex_tuple = (*codes++ - 0300);
997 break;
998
999 case4(0254):
1000 length += 4;
1001 break;
1002
1003 case4(0260):
1004 ins->rex |= REX_V;
1005 ins->vexreg = regval(opx);
1006 ins->vex_cm = *codes++;
1007 ins->vex_wlp = *codes++;
1008 break;
1009
1010 case 0270:
1011 ins->rex |= REX_V;
1012 ins->vexreg = 0;
1013 ins->vex_cm = *codes++;
1014 ins->vex_wlp = *codes++;
1015 break;
1016
1017 case3(0271):
1018 hleok = c & 3;
1019 break;
1020
1021 case4(0274):
1022 length++;
1023 break;
1024
1025 case4(0300):
1026 break;
1027
1028 case 0310:
1029 if (bits == 64)
1030 return -1;
1031 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1032 break;
1033
1034 case 0311:
1035 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1036 break;
1037
1038 case 0312:
1039 break;
1040
1041 case 0313:
1042 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1043 has_prefix(ins, PPS_ASIZE, P_A32))
1044 return -1;
1045 break;
1046
1047 case4(0314):
1048 break;
1049
1050 case 0320:
1051 {
1052 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1053 if (pfx == P_O16)
1054 break;
1055 if (pfx != P_none)
1056 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1057 else
1058 ins->prefixes[PPS_OSIZE] = P_O16;
1059 break;
1060 }
1061
1062 case 0321:
1063 {
1064 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1065 if (pfx == P_O32)
1066 break;
1067 if (pfx != P_none)
1068 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1069 else
1070 ins->prefixes[PPS_OSIZE] = P_O32;
1071 break;
1072 }
1073
1074 case 0322:
1075 break;
1076
1077 case 0323:
1078 rex_mask &= ~REX_W;
1079 break;
1080
1081 case 0324:
1082 ins->rex |= REX_W;
1083 break;
1084
1085 case 0325:
1086 ins->rex |= REX_NH;
1087 break;
1088
1089 case 0326:
1090 break;
1091
1092 case 0330:
1093 codes++, length++;
1094 break;
1095
1096 case 0331:
1097 break;
1098
1099 case 0332:
1100 case 0333:
1101 length++;
1102 break;
1103
1104 case 0334:
1105 ins->rex |= REX_L;
1106 break;
1107
1108 case 0335:
1109 break;
1110
1111 case 0336:
1112 if (!ins->prefixes[PPS_REP])
1113 ins->prefixes[PPS_REP] = P_REP;
1114 break;
1115
1116 case 0337:
1117 if (!ins->prefixes[PPS_REP])
1118 ins->prefixes[PPS_REP] = P_REPNE;
1119 break;
1120
1121 case 0340:
1122 if (ins->oprs[0].segment != NO_SEG)
1123 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1124 " quantity of BSS space");
1125 else
1126 length += ins->oprs[0].offset;
1127 break;
1128
1129 case 0341:
1130 if (!ins->prefixes[PPS_WAIT])
1131 ins->prefixes[PPS_WAIT] = P_WAIT;
1132 break;
1133
1134 case 0360:
1135 break;
1136
1137 case 0361:
1138 length++;
1139 break;
1140
1141 case 0364:
1142 case 0365:
1143 break;
1144
1145 case 0366:
1146 case 0367:
1147 length++;
1148 break;
1149
1150 case 0370:
1151 case 0371:
1152 break;
1153
1154 case 0373:
1155 length++;
1156 break;
1157
1158 case 0374:
1159 eat = EA_XMMVSIB;
1160 break;
1161
1162 case 0375:
1163 eat = EA_YMMVSIB;
1164 break;
1165
1166 case 0376:
1167 eat = EA_ZMMVSIB;
1168 break;
1169
1170 case4(0100):
1171 case4(0110):
1172 case4(0120):
1173 case4(0130):
1174 case4(0200):
1175 case4(0204):
1176 case4(0210):
1177 case4(0214):
1178 case4(0220):
1179 case4(0224):
1180 case4(0230):
1181 case4(0234):
1182 {
1183 ea ea_data;
1184 int rfield;
1185 opflags_t rflags;
1186 struct operand *opy = &ins->oprs[op2];
1187 struct operand *op_er_sae;
1188
1189 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1190
1191 if (c <= 0177) {
1192 /* pick rfield from operand b (opx) */
1193 rflags = regflag(opx);
1194 rfield = nasm_regvals[opx->basereg];
1195 } else {
1196 rflags = 0;
1197 rfield = c & 7;
1198 }
1199
1200 /* EVEX.b1 : evex_brerop contains the operand position */
1201 op_er_sae = (ins->evex_brerop >= 0 ?
1202 &ins->oprs[ins->evex_brerop] : NULL);
1203
1204 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1205 /* set EVEX.b */
1206 ins->evex_p[2] |= EVEX_P2B;
1207 if (op_er_sae->decoflags & ER) {
1208 /* set EVEX.RC (rounding control) */
1209 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1210 & EVEX_P2RC;
1211 }
1212 } else {
1213 /* set EVEX.L'L (vector length) */
1214 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1215 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1216 if (opy->decoflags & BRDCAST_MASK) {
1217 /* set EVEX.b */
1218 ins->evex_p[2] |= EVEX_P2B;
1219 }
1220 }
1221
1222 /*
1223 * if a separate form of MIB (ICC style) is used,
1224 * the index reg info is merged into mem operand
1225 */
1226 if (mib_index != R_none) {
1227 opy->indexreg = mib_index;
1228 opy->scale = 1;
1229 opy->hintbase = mib_index;
1230 opy->hinttype = EAH_NOTBASE;
1231 }
1232
1233 /*
1234 * only for mib operands, make a single reg index [reg*1].
1235 * gas uses this form to explicitly denote index register.
1236 */
1237 if (itemp_has(temp, IF_MIB) &&
1238 (opy->indexreg == -1 && opy->hintbase == opy->basereg &&
1239 opy->hinttype == EAH_NOTBASE)) {
1240 opy->indexreg = opy->basereg;
1241 opy->basereg = -1;
1242 opy->scale = 1;
1243 }
1244
1245 if (process_ea(opy, &ea_data, bits,
1246 rfield, rflags, ins) != eat) {
1247 errfunc(ERR_NONFATAL, "invalid effective address");
1248 return -1;
1249 } else {
1250 ins->rex |= ea_data.rex;
1251 length += ea_data.size;
1252 }
1253 }
1254 break;
1255
1256 default:
1257 errfunc(ERR_PANIC, "internal instruction table corrupt"
1258 ": instruction code \\%o (0x%02X) given", c, c);
1259 break;
1260 }
1261 }
1262
1263 ins->rex &= rex_mask;
1264
1265 if (ins->rex & REX_NH) {
1266 if (ins->rex & REX_H) {
1267 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1268 return -1;
1269 }
1270 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1271 }
1272
1273 if (ins->rex & (REX_V | REX_EV)) {
1274 int bad32 = REX_R|REX_W|REX_X|REX_B;
1275
1276 if (ins->rex & REX_H) {
1277 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1278 return -1;
1279 }
1280 switch (ins->vex_wlp & 060) {
1281 case 000:
1282 case 040:
1283 ins->rex &= ~REX_W;
1284 break;
1285 case 020:
1286 ins->rex |= REX_W;
1287 bad32 &= ~REX_W;
1288 break;
1289 case 060:
1290 /* Follow REX_W */
1291 break;
1292 }
1293
1294 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1295 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1296 return -1;
1297 } else if (!(ins->rex & REX_EV) &&
1298 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1299 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1300 return -1;
1301 }
1302 if (ins->rex & REX_EV)
1303 length += 4;
1304 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1305 length += 3;
1306 else
1307 length += 2;
1308 } else if (ins->rex & REX_REAL) {
1309 if (ins->rex & REX_H) {
1310 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1311 return -1;
1312 } else if (bits == 64) {
1313 length++;
1314 } else if ((ins->rex & REX_L) &&
1315 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1316 iflag_ffs(&cpu) >= IF_X86_64) {
1317 /* LOCK-as-REX.R */
1318 assert_no_prefix(ins, PPS_LOCK);
1319 lockcheck = false; /* Already errored, no need for warning */
1320 length++;
1321 } else {
1322 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1323 return -1;
1324 }
1325 }
1326
1327 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1328 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1329 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1330 "instruction is not lockable");
1331 }
1332
1333 bad_hle_warn(ins, hleok);
1334
1335 return length;
1336 }
1337
1338 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1339 {
1340 if (bits == 64) {
1341 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1342 ins->rex = (ins->rex & REX_REAL) | REX_P;
1343 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1344 ins->rex = 0;
1345 return 1;
1346 }
1347 }
1348
1349 return 0;
1350 }
1351
1352 static void gencode(int32_t segment, int64_t offset, int bits,
1353 insn * ins, const struct itemplate *temp,
1354 int64_t insn_end)
1355 {
1356 uint8_t c;
1357 uint8_t bytes[4];
1358 int64_t size;
1359 int64_t data;
1360 int op1, op2;
1361 struct operand *opx;
1362 const uint8_t *codes = temp->code;
1363 uint8_t opex = 0;
1364 enum ea_type eat = EA_SCALAR;
1365
1366 while (*codes) {
1367 c = *codes++;
1368 op1 = (c & 3) + ((opex & 1) << 2);
1369 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1370 opx = &ins->oprs[op1];
1371 opex = 0; /* For the next iteration */
1372
1373 switch (c) {
1374 case 01:
1375 case 02:
1376 case 03:
1377 case 04:
1378 offset += emit_rex(ins, segment, offset, bits);
1379 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1380 codes += c;
1381 offset += c;
1382 break;
1383
1384 case 05:
1385 case 06:
1386 case 07:
1387 opex = c;
1388 break;
1389
1390 case4(010):
1391 offset += emit_rex(ins, segment, offset, bits);
1392 bytes[0] = *codes++ + (regval(opx) & 7);
1393 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1394 offset += 1;
1395 break;
1396
1397 case4(014):
1398 break;
1399
1400 case4(020):
1401 if (opx->offset < -256 || opx->offset > 255) {
1402 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1403 "byte value exceeds bounds");
1404 }
1405 out_imm8(offset, segment, opx, -1);
1406 offset += 1;
1407 break;
1408
1409 case4(024):
1410 if (opx->offset < 0 || opx->offset > 255)
1411 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1412 "unsigned byte value exceeds bounds");
1413 out_imm8(offset, segment, opx, 1);
1414 offset += 1;
1415 break;
1416
1417 case4(030):
1418 warn_overflow_opd(opx, 2);
1419 data = opx->offset;
1420 out(offset, segment, &data, OUT_ADDRESS, 2,
1421 opx->segment, opx->wrt);
1422 offset += 2;
1423 break;
1424
1425 case4(034):
1426 if (opx->type & (BITS16 | BITS32))
1427 size = (opx->type & BITS16) ? 2 : 4;
1428 else
1429 size = (bits == 16) ? 2 : 4;
1430 warn_overflow_opd(opx, size);
1431 data = opx->offset;
1432 out(offset, segment, &data, OUT_ADDRESS, size,
1433 opx->segment, opx->wrt);
1434 offset += size;
1435 break;
1436
1437 case4(040):
1438 warn_overflow_opd(opx, 4);
1439 data = opx->offset;
1440 out(offset, segment, &data, OUT_ADDRESS, 4,
1441 opx->segment, opx->wrt);
1442 offset += 4;
1443 break;
1444
1445 case4(044):
1446 data = opx->offset;
1447 size = ins->addr_size >> 3;
1448 warn_overflow_opd(opx, size);
1449 out(offset, segment, &data, OUT_ADDRESS, size,
1450 opx->segment, opx->wrt);
1451 offset += size;
1452 break;
1453
1454 case4(050):
1455 if (opx->segment != segment) {
1456 data = opx->offset;
1457 out(offset, segment, &data,
1458 OUT_REL1ADR, insn_end - offset,
1459 opx->segment, opx->wrt);
1460 } else {
1461 data = opx->offset - insn_end;
1462 if (data > 127 || data < -128)
1463 errfunc(ERR_NONFATAL, "short jump is out of range");
1464 out(offset, segment, &data,
1465 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1466 }
1467 offset += 1;
1468 break;
1469
1470 case4(054):
1471 data = (int64_t)opx->offset;
1472 out(offset, segment, &data, OUT_ADDRESS, 8,
1473 opx->segment, opx->wrt);
1474 offset += 8;
1475 break;
1476
1477 case4(060):
1478 if (opx->segment != segment) {
1479 data = opx->offset;
1480 out(offset, segment, &data,
1481 OUT_REL2ADR, insn_end - offset,
1482 opx->segment, opx->wrt);
1483 } else {
1484 data = opx->offset - insn_end;
1485 out(offset, segment, &data,
1486 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1487 }
1488 offset += 2;
1489 break;
1490
1491 case4(064):
1492 if (opx->type & (BITS16 | BITS32 | BITS64))
1493 size = (opx->type & BITS16) ? 2 : 4;
1494 else
1495 size = (bits == 16) ? 2 : 4;
1496 if (opx->segment != segment) {
1497 data = opx->offset;
1498 out(offset, segment, &data,
1499 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1500 insn_end - offset, opx->segment, opx->wrt);
1501 } else {
1502 data = opx->offset - insn_end;
1503 out(offset, segment, &data,
1504 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1505 }
1506 offset += size;
1507 break;
1508
1509 case4(070):
1510 if (opx->segment != segment) {
1511 data = opx->offset;
1512 out(offset, segment, &data,
1513 OUT_REL4ADR, insn_end - offset,
1514 opx->segment, opx->wrt);
1515 } else {
1516 data = opx->offset - insn_end;
1517 out(offset, segment, &data,
1518 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1519 }
1520 offset += 4;
1521 break;
1522
1523 case4(074):
1524 if (opx->segment == NO_SEG)
1525 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1526 " relocatable");
1527 data = 0;
1528 out(offset, segment, &data, OUT_ADDRESS, 2,
1529 outfmt->segbase(1 + opx->segment),
1530 opx->wrt);
1531 offset += 2;
1532 break;
1533
1534 case 0172:
1535 c = *codes++;
1536 opx = &ins->oprs[c >> 3];
1537 bytes[0] = nasm_regvals[opx->basereg] << 4;
1538 opx = &ins->oprs[c & 7];
1539 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1540 errfunc(ERR_NONFATAL,
1541 "non-absolute expression not permitted as argument %d",
1542 c & 7);
1543 } else {
1544 if (opx->offset & ~15) {
1545 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1546 "four-bit argument exceeds bounds");
1547 }
1548 bytes[0] |= opx->offset & 15;
1549 }
1550 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1551 offset++;
1552 break;
1553
1554 case 0173:
1555 c = *codes++;
1556 opx = &ins->oprs[c >> 4];
1557 bytes[0] = nasm_regvals[opx->basereg] << 4;
1558 bytes[0] |= c & 15;
1559 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1560 offset++;
1561 break;
1562
1563 case4(0174):
1564 bytes[0] = nasm_regvals[opx->basereg] << 4;
1565 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1566 offset++;
1567 break;
1568
1569 case4(0254):
1570 data = opx->offset;
1571 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1572 (int32_t)data != (int64_t)data) {
1573 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1574 "signed dword immediate exceeds bounds");
1575 }
1576 out(offset, segment, &data, OUT_ADDRESS, -4,
1577 opx->segment, opx->wrt);
1578 offset += 4;
1579 break;
1580
1581 case4(0240):
1582 case 0250:
1583 codes += 3;
1584 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1585 EVEX_P2Z | EVEX_P2AAA, 2);
1586 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1587 bytes[0] = 0x62;
1588 /* EVEX.X can be set by either REX or EVEX for different reasons */
1589 bytes[1] = ((((ins->rex & 7) << 5) |
1590 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1591 (ins->vex_cm & 3);
1592 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1593 ((~ins->vexreg & 15) << 3) |
1594 (1 << 2) | (ins->vex_wlp & 3);
1595 bytes[3] = ins->evex_p[2];
1596 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1597 offset += 4;
1598 break;
1599
1600 case4(0260):
1601 case 0270:
1602 codes += 2;
1603 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1604 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1605 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1606 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1607 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1608 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1609 offset += 3;
1610 } else {
1611 bytes[0] = 0xc5;
1612 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1613 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1614 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1615 offset += 2;
1616 }
1617 break;
1618
1619 case 0271:
1620 case 0272:
1621 case 0273:
1622 break;
1623
1624 case4(0274):
1625 {
1626 uint64_t uv, um;
1627 int s;
1628
1629 if (ins->rex & REX_W)
1630 s = 64;
1631 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1632 s = 16;
1633 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1634 s = 32;
1635 else
1636 s = bits;
1637
1638 um = (uint64_t)2 << (s-1);
1639 uv = opx->offset;
1640
1641 if (uv > 127 && uv < (uint64_t)-128 &&
1642 (uv < um-128 || uv > um-1)) {
1643 /* If this wasn't explicitly byte-sized, warn as though we
1644 * had fallen through to the imm16/32/64 case.
1645 */
1646 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1647 "%s value exceeds bounds",
1648 (opx->type & BITS8) ? "signed byte" :
1649 s == 16 ? "word" :
1650 s == 32 ? "dword" :
1651 "signed dword");
1652 }
1653 if (opx->segment != NO_SEG) {
1654 data = uv;
1655 out(offset, segment, &data, OUT_ADDRESS, 1,
1656 opx->segment, opx->wrt);
1657 } else {
1658 bytes[0] = uv;
1659 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1660 NO_SEG);
1661 }
1662 offset += 1;
1663 break;
1664 }
1665
1666 case4(0300):
1667 break;
1668
1669 case 0310:
1670 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1671 *bytes = 0x67;
1672 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1673 offset += 1;
1674 } else
1675 offset += 0;
1676 break;
1677
1678 case 0311:
1679 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1680 *bytes = 0x67;
1681 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1682 offset += 1;
1683 } else
1684 offset += 0;
1685 break;
1686
1687 case 0312:
1688 break;
1689
1690 case 0313:
1691 ins->rex = 0;
1692 break;
1693
1694 case4(0314):
1695 break;
1696
1697 case 0320:
1698 case 0321:
1699 break;
1700
1701 case 0322:
1702 case 0323:
1703 break;
1704
1705 case 0324:
1706 ins->rex |= REX_W;
1707 break;
1708
1709 case 0325:
1710 break;
1711
1712 case 0326:
1713 break;
1714
1715 case 0330:
1716 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1717 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1718 offset += 1;
1719 break;
1720
1721 case 0331:
1722 break;
1723
1724 case 0332:
1725 case 0333:
1726 *bytes = c - 0332 + 0xF2;
1727 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1728 offset += 1;
1729 break;
1730
1731 case 0334:
1732 if (ins->rex & REX_R) {
1733 *bytes = 0xF0;
1734 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1735 offset += 1;
1736 }
1737 ins->rex &= ~(REX_L|REX_R);
1738 break;
1739
1740 case 0335:
1741 break;
1742
1743 case 0336:
1744 case 0337:
1745 break;
1746
1747 case 0340:
1748 if (ins->oprs[0].segment != NO_SEG)
1749 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1750 else {
1751 int64_t size = ins->oprs[0].offset;
1752 if (size > 0)
1753 out(offset, segment, NULL,
1754 OUT_RESERVE, size, NO_SEG, NO_SEG);
1755 offset += size;
1756 }
1757 break;
1758
1759 case 0341:
1760 break;
1761
1762 case 0360:
1763 break;
1764
1765 case 0361:
1766 bytes[0] = 0x66;
1767 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1768 offset += 1;
1769 break;
1770
1771 case 0364:
1772 case 0365:
1773 break;
1774
1775 case 0366:
1776 case 0367:
1777 *bytes = c - 0366 + 0x66;
1778 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1779 offset += 1;
1780 break;
1781
1782 case3(0370):
1783 break;
1784
1785 case 0373:
1786 *bytes = bits == 16 ? 3 : 5;
1787 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1788 offset += 1;
1789 break;
1790
1791 case 0374:
1792 eat = EA_XMMVSIB;
1793 break;
1794
1795 case 0375:
1796 eat = EA_YMMVSIB;
1797 break;
1798
1799 case 0376:
1800 eat = EA_ZMMVSIB;
1801 break;
1802
1803 case4(0100):
1804 case4(0110):
1805 case4(0120):
1806 case4(0130):
1807 case4(0200):
1808 case4(0204):
1809 case4(0210):
1810 case4(0214):
1811 case4(0220):
1812 case4(0224):
1813 case4(0230):
1814 case4(0234):
1815 {
1816 ea ea_data;
1817 int rfield;
1818 opflags_t rflags;
1819 uint8_t *p;
1820 int32_t s;
1821 struct operand *opy = &ins->oprs[op2];
1822
1823 if (c <= 0177) {
1824 /* pick rfield from operand b (opx) */
1825 rflags = regflag(opx);
1826 rfield = nasm_regvals[opx->basereg];
1827 } else {
1828 /* rfield is constant */
1829 rflags = 0;
1830 rfield = c & 7;
1831 }
1832
1833 if (process_ea(opy, &ea_data, bits,
1834 rfield, rflags, ins) != eat)
1835 errfunc(ERR_NONFATAL, "invalid effective address");
1836
1837 p = bytes;
1838 *p++ = ea_data.modrm;
1839 if (ea_data.sib_present)
1840 *p++ = ea_data.sib;
1841
1842 s = p - bytes;
1843 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1844
1845 /*
1846 * Make sure the address gets the right offset in case
1847 * the line breaks in the .lst file (BR 1197827)
1848 */
1849 offset += s;
1850 s = 0;
1851
1852 switch (ea_data.bytes) {
1853 case 0:
1854 break;
1855 case 1:
1856 case 2:
1857 case 4:
1858 case 8:
1859 /* use compressed displacement, if available */
1860 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1861 s += ea_data.bytes;
1862 if (ea_data.rip) {
1863 if (opy->segment == segment) {
1864 data -= insn_end;
1865 if (overflow_signed(data, ea_data.bytes))
1866 warn_overflow(ERR_PASS2, ea_data.bytes);
1867 out(offset, segment, &data, OUT_ADDRESS,
1868 ea_data.bytes, NO_SEG, NO_SEG);
1869 } else {
1870 /* overflow check in output/linker? */
1871 out(offset, segment, &data, OUT_REL4ADR,
1872 insn_end - offset, opy->segment, opy->wrt);
1873 }
1874 } else {
1875 if (overflow_general(data, ins->addr_size >> 3) ||
1876 signed_bits(data, ins->addr_size) !=
1877 signed_bits(data, ea_data.bytes * 8))
1878 warn_overflow(ERR_PASS2, ea_data.bytes);
1879
1880 out(offset, segment, &data, OUT_ADDRESS,
1881 -ea_data.bytes, opy->segment, opy->wrt);
1882 }
1883 break;
1884 default:
1885 /* Impossible! */
1886 errfunc(ERR_PANIC,
1887 "Invalid amount of bytes (%d) for offset?!",
1888 ea_data.bytes);
1889 break;
1890 }
1891 offset += s;
1892 }
1893 break;
1894
1895 default:
1896 errfunc(ERR_PANIC, "internal instruction table corrupt"
1897 ": instruction code \\%o (0x%02X) given", c, c);
1898 break;
1899 }
1900 }
1901 }
1902
1903 static opflags_t regflag(const operand * o)
1904 {
1905 if (!is_register(o->basereg))
1906 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1907 return nasm_reg_flags[o->basereg];
1908 }
1909
1910 static int32_t regval(const operand * o)
1911 {
1912 if (!is_register(o->basereg))
1913 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1914 return nasm_regvals[o->basereg];
1915 }
1916
1917 static int op_rexflags(const operand * o, int mask)
1918 {
1919 opflags_t flags;
1920 int val;
1921
1922 if (!is_register(o->basereg))
1923 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1924
1925 flags = nasm_reg_flags[o->basereg];
1926 val = nasm_regvals[o->basereg];
1927
1928 return rexflags(val, flags, mask);
1929 }
1930
1931 static int rexflags(int val, opflags_t flags, int mask)
1932 {
1933 int rex = 0;
1934
1935 if (val >= 0 && (val & 8))
1936 rex |= REX_B|REX_X|REX_R;
1937 if (flags & BITS64)
1938 rex |= REX_W;
1939 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1940 rex |= REX_H;
1941 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1942 rex |= REX_P;
1943
1944 return rex & mask;
1945 }
1946
1947 static int evexflags(int val, decoflags_t deco,
1948 int mask, uint8_t byte)
1949 {
1950 int evex = 0;
1951
1952 switch (byte) {
1953 case 0:
1954 if (val >= 0 && (val & 16))
1955 evex |= (EVEX_P0RP | EVEX_P0X);
1956 break;
1957 case 2:
1958 if (val >= 0 && (val & 16))
1959 evex |= EVEX_P2VP;
1960 if (deco & Z)
1961 evex |= EVEX_P2Z;
1962 if (deco & OPMASK_MASK)
1963 evex |= deco & EVEX_P2AAA;
1964 break;
1965 }
1966 return evex & mask;
1967 }
1968
1969 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1970 {
1971 int val;
1972
1973 if (!is_register(o->basereg))
1974 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1975
1976 val = nasm_regvals[o->basereg];
1977
1978 return evexflags(val, o->decoflags, mask, byte);
1979 }
1980
1981 static enum match_result find_match(const struct itemplate **tempp,
1982 insn *instruction,
1983 int32_t segment, int64_t offset, int bits)
1984 {
1985 const struct itemplate *temp;
1986 enum match_result m, merr;
1987 opflags_t xsizeflags[MAX_OPERANDS];
1988 bool opsizemissing = false;
1989 int8_t broadcast = instruction->evex_brerop;
1990 int i;
1991
1992 /* broadcasting uses a different data element size */
1993 for (i = 0; i < instruction->operands; i++)
1994 if (i == broadcast)
1995 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
1996 else
1997 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1998
1999 merr = MERR_INVALOP;
2000
2001 for (temp = nasm_instructions[instruction->opcode];
2002 temp->opcode != I_none; temp++) {
2003 m = matches(temp, instruction, bits);
2004 if (m == MOK_JUMP) {
2005 if (jmp_match(segment, offset, bits, instruction, temp))
2006 m = MOK_GOOD;
2007 else
2008 m = MERR_INVALOP;
2009 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2010 /*
2011 * Missing operand size and a candidate for fuzzy matching...
2012 */
2013 for (i = 0; i < temp->operands; i++)
2014 if (i == broadcast)
2015 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2016 else
2017 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2018 opsizemissing = true;
2019 }
2020 if (m > merr)
2021 merr = m;
2022 if (merr == MOK_GOOD)
2023 goto done;
2024 }
2025
2026 /* No match, but see if we can get a fuzzy operand size match... */
2027 if (!opsizemissing)
2028 goto done;
2029
2030 for (i = 0; i < instruction->operands; i++) {
2031 /*
2032 * We ignore extrinsic operand sizes on registers, so we should
2033 * never try to fuzzy-match on them. This also resolves the case
2034 * when we have e.g. "xmmrm128" in two different positions.
2035 */
2036 if (is_class(REGISTER, instruction->oprs[i].type))
2037 continue;
2038
2039 /* This tests if xsizeflags[i] has more than one bit set */
2040 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2041 goto done; /* No luck */
2042
2043 if (i == broadcast) {
2044 instruction->oprs[i].decoflags |= xsizeflags[i];
2045 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2046 BITS32 : BITS64);
2047 } else {
2048 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2049 }
2050 }
2051
2052 /* Try matching again... */
2053 for (temp = nasm_instructions[instruction->opcode];
2054 temp->opcode != I_none; temp++) {
2055 m = matches(temp, instruction, bits);
2056 if (m == MOK_JUMP) {
2057 if (jmp_match(segment, offset, bits, instruction, temp))
2058 m = MOK_GOOD;
2059 else
2060 m = MERR_INVALOP;
2061 }
2062 if (m > merr)
2063 merr = m;
2064 if (merr == MOK_GOOD)
2065 goto done;
2066 }
2067
2068 done:
2069 *tempp = temp;
2070 return merr;
2071 }
2072
2073 static enum match_result matches(const struct itemplate *itemp,
2074 insn *instruction, int bits)
2075 {
2076 opflags_t size[MAX_OPERANDS], asize;
2077 bool opsizemissing = false;
2078 int i, oprs;
2079
2080 /*
2081 * Check the opcode
2082 */
2083 if (itemp->opcode != instruction->opcode)
2084 return MERR_INVALOP;
2085
2086 /*
2087 * Count the operands
2088 */
2089 if (itemp->operands != instruction->operands)
2090 return MERR_INVALOP;
2091
2092 /*
2093 * Is it legal?
2094 */
2095 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2096 return MERR_INVALOP;
2097
2098 /*
2099 * Check that no spurious colons or TOs are present
2100 */
2101 for (i = 0; i < itemp->operands; i++)
2102 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2103 return MERR_INVALOP;
2104
2105 /*
2106 * Process size flags
2107 */
2108 switch (itemp_smask(itemp)) {
2109 case IF_GENBIT(IF_SB):
2110 asize = BITS8;
2111 break;
2112 case IF_GENBIT(IF_SW):
2113 asize = BITS16;
2114 break;
2115 case IF_GENBIT(IF_SD):
2116 asize = BITS32;
2117 break;
2118 case IF_GENBIT(IF_SQ):
2119 asize = BITS64;
2120 break;
2121 case IF_GENBIT(IF_SO):
2122 asize = BITS128;
2123 break;
2124 case IF_GENBIT(IF_SY):
2125 asize = BITS256;
2126 break;
2127 case IF_GENBIT(IF_SZ):
2128 asize = BITS512;
2129 break;
2130 case IF_GENBIT(IF_SIZE):
2131 switch (bits) {
2132 case 16:
2133 asize = BITS16;
2134 break;
2135 case 32:
2136 asize = BITS32;
2137 break;
2138 case 64:
2139 asize = BITS64;
2140 break;
2141 default:
2142 asize = 0;
2143 break;
2144 }
2145 break;
2146 default:
2147 asize = 0;
2148 break;
2149 }
2150
2151 if (itemp_armask(itemp)) {
2152 /* S- flags only apply to a specific operand */
2153 i = itemp_arg(itemp);
2154 memset(size, 0, sizeof size);
2155 size[i] = asize;
2156 } else {
2157 /* S- flags apply to all operands */
2158 for (i = 0; i < MAX_OPERANDS; i++)
2159 size[i] = asize;
2160 }
2161
2162 /*
2163 * Check that the operand flags all match up,
2164 * it's a bit tricky so lets be verbose:
2165 *
2166 * 1) Find out the size of operand. If instruction
2167 * doesn't have one specified -- we're trying to
2168 * guess it either from template (IF_S* flag) or
2169 * from code bits.
2170 *
2171 * 2) If template operand do not match the instruction OR
2172 * template has an operand size specified AND this size differ
2173 * from which instruction has (perhaps we got it from code bits)
2174 * we are:
2175 * a) Check that only size of instruction and operand is differ
2176 * other characteristics do match
2177 * b) Perhaps it's a register specified in instruction so
2178 * for such a case we just mark that operand as "size
2179 * missing" and this will turn on fuzzy operand size
2180 * logic facility (handled by a caller)
2181 */
2182 for (i = 0; i < itemp->operands; i++) {
2183 opflags_t type = instruction->oprs[i].type;
2184 decoflags_t deco = instruction->oprs[i].decoflags;
2185 bool is_broadcast = deco & BRDCAST_MASK;
2186 uint8_t brcast_num = 0;
2187 opflags_t template_opsize, insn_opsize;
2188
2189 if (!(type & SIZE_MASK))
2190 type |= size[i];
2191
2192 insn_opsize = type & SIZE_MASK;
2193 if (!is_broadcast) {
2194 template_opsize = itemp->opd[i] & SIZE_MASK;
2195 } else {
2196 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2197 /*
2198 * when broadcasting, the element size depends on
2199 * the instruction type. decorator flag should match.
2200 */
2201
2202 if (deco_brsize) {
2203 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2204 /* calculate the proper number : {1to<brcast_num>} */
2205 brcast_num = (itemp->opd[i] & SIZE_MASK) / BITS128 *
2206 BITS64 / template_opsize * 2;
2207 } else {
2208 template_opsize = 0;
2209 }
2210 }
2211
2212 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2213 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2214 return MERR_INVALOP;
2215 } else if (template_opsize) {
2216 if (template_opsize != insn_opsize) {
2217 if (insn_opsize) {
2218 return MERR_INVALOP;
2219 } else if (!is_class(REGISTER, type)) {
2220 /*
2221 * Note: we don't honor extrinsic operand sizes for registers,
2222 * so "missing operand size" for a register should be
2223 * considered a wildcard match rather than an error.
2224 */
2225 opsizemissing = true;
2226 }
2227 } else if (is_broadcast &&
2228 (brcast_num !=
2229 (8U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2230 /*
2231 * broadcasting opsize matches but the number of repeated memory
2232 * element does not match.
2233 * if 64b double precision float is broadcasted to zmm (512b),
2234 * broadcasting decorator must be {1to8}.
2235 */
2236 return MERR_BRNUMMISMATCH;
2237 }
2238 } else if (is_register(instruction->oprs[i].basereg) &&
2239 nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
2240 !itemp_has(itemp, IF_AVX512)) {
2241 return MERR_ENCMISMATCH;
2242 } else if (instruction->prefixes[PPS_EVEX] &&
2243 !itemp_has(itemp, IF_AVX512)) {
2244 return MERR_ENCMISMATCH;
2245 }
2246 }
2247
2248 if (opsizemissing)
2249 return MERR_OPSIZEMISSING;
2250
2251 /*
2252 * Check operand sizes
2253 */
2254 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2255 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2256 for (i = 0; i < oprs; i++) {
2257 asize = itemp->opd[i] & SIZE_MASK;
2258 if (asize) {
2259 for (i = 0; i < oprs; i++)
2260 size[i] = asize;
2261 break;
2262 }
2263 }
2264 } else {
2265 oprs = itemp->operands;
2266 }
2267
2268 for (i = 0; i < itemp->operands; i++) {
2269 if (!(itemp->opd[i] & SIZE_MASK) &&
2270 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2271 return MERR_OPSIZEMISMATCH;
2272 }
2273
2274 /*
2275 * Check template is okay at the set cpu level
2276 */
2277 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2278 return MERR_BADCPU;
2279
2280 /*
2281 * Verify the appropriate long mode flag.
2282 */
2283 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2284 return MERR_BADMODE;
2285
2286 /*
2287 * If we have a HLE prefix, look for the NOHLE flag
2288 */
2289 if (itemp_has(itemp, IF_NOHLE) &&
2290 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2291 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2292 return MERR_BADHLE;
2293
2294 /*
2295 * Check if special handling needed for Jumps
2296 */
2297 if ((itemp->code[0] & ~1) == 0370)
2298 return MOK_JUMP;
2299
2300 /*
2301 * Check if BND prefix is allowed
2302 */
2303 if (!itemp_has(itemp, IF_BND) &&
2304 has_prefix(instruction, PPS_REP, P_BND))
2305 return MERR_BADBND;
2306
2307 return MOK_GOOD;
2308 }
2309
2310 /*
2311 * Check if ModR/M.mod should/can be 01.
2312 * - EAF_BYTEOFFS is set
2313 * - offset can fit in a byte when EVEX is not used
2314 * - offset can be compressed when EVEX is used
2315 */
2316 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2317 (o >= -128 && o <= 127 && \
2318 seg == NO_SEG && !forw_ref && \
2319 !(input->eaflags & EAF_WORDOFFS) && \
2320 !(ins->rex & REX_EV)) || \
2321 (ins->rex & REX_EV && \
2322 is_disp8n(input, ins, &output->disp8)))
2323
2324 static enum ea_type process_ea(operand *input, ea *output, int bits,
2325 int rfield, opflags_t rflags, insn *ins)
2326 {
2327 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2328 int addrbits = ins->addr_size;
2329
2330 output->type = EA_SCALAR;
2331 output->rip = false;
2332 output->disp8 = 0;
2333
2334 /* REX flags for the rfield operand */
2335 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2336 /* EVEX.R' flag for the REG operand */
2337 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2338
2339 if (is_class(REGISTER, input->type)) {
2340 /*
2341 * It's a direct register.
2342 */
2343 if (!is_register(input->basereg))
2344 goto err;
2345
2346 if (!is_reg_class(REG_EA, input->basereg))
2347 goto err;
2348
2349 /* broadcasting is not available with a direct register operand. */
2350 if (input->decoflags & BRDCAST_MASK) {
2351 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2352 goto err;
2353 }
2354
2355 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2356 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2357 output->sib_present = false; /* no SIB necessary */
2358 output->bytes = 0; /* no offset necessary either */
2359 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2360 } else {
2361 /*
2362 * It's a memory reference.
2363 */
2364
2365 /* Embedded rounding or SAE is not available with a mem ref operand. */
2366 if (input->decoflags & (ER | SAE)) {
2367 nasm_error(ERR_NONFATAL,
2368 "Embedded rounding is available only with reg-reg op.");
2369 return -1;
2370 }
2371
2372 if (input->basereg == -1 &&
2373 (input->indexreg == -1 || input->scale == 0)) {
2374 /*
2375 * It's a pure offset.
2376 */
2377 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2378 input->segment == NO_SEG) {
2379 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2380 input->type &= ~IP_REL;
2381 input->type |= MEMORY;
2382 }
2383
2384 if (input->eaflags & EAF_BYTEOFFS ||
2385 (input->eaflags & EAF_WORDOFFS &&
2386 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2387 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2388 }
2389
2390 if (bits == 64 && (~input->type & IP_REL)) {
2391 output->sib_present = true;
2392 output->sib = GEN_SIB(0, 4, 5);
2393 output->bytes = 4;
2394 output->modrm = GEN_MODRM(0, rfield, 4);
2395 output->rip = false;
2396 } else {
2397 output->sib_present = false;
2398 output->bytes = (addrbits != 16 ? 4 : 2);
2399 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2400 output->rip = bits == 64;
2401 }
2402 } else {
2403 /*
2404 * It's an indirection.
2405 */
2406 int i = input->indexreg, b = input->basereg, s = input->scale;
2407 int32_t seg = input->segment;
2408 int hb = input->hintbase, ht = input->hinttype;
2409 int t, it, bt; /* register numbers */
2410 opflags_t x, ix, bx; /* register flags */
2411
2412 if (s == 0)
2413 i = -1; /* make this easy, at least */
2414
2415 if (is_register(i)) {
2416 it = nasm_regvals[i];
2417 ix = nasm_reg_flags[i];
2418 } else {
2419 it = -1;
2420 ix = 0;
2421 }
2422
2423 if (is_register(b)) {
2424 bt = nasm_regvals[b];
2425 bx = nasm_reg_flags[b];
2426 } else {
2427 bt = -1;
2428 bx = 0;
2429 }
2430
2431 /* if either one are a vector register... */
2432 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2433 opflags_t sok = BITS32 | BITS64;
2434 int32_t o = input->offset;
2435 int mod, scale, index, base;
2436
2437 /*
2438 * For a vector SIB, one has to be a vector and the other,
2439 * if present, a GPR. The vector must be the index operand.
2440 */
2441 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2442 if (s == 0)
2443 s = 1;
2444 else if (s != 1)
2445 goto err;
2446
2447 t = bt, bt = it, it = t;
2448 x = bx, bx = ix, ix = x;
2449 }
2450
2451 if (bt != -1) {
2452 if (REG_GPR & ~bx)
2453 goto err;
2454 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2455 sok &= bx;
2456 else
2457 goto err;
2458 }
2459
2460 /*
2461 * While we're here, ensure the user didn't specify
2462 * WORD or QWORD
2463 */
2464 if (input->disp_size == 16 || input->disp_size == 64)
2465 goto err;
2466
2467 if (addrbits == 16 ||
2468 (addrbits == 32 && !(sok & BITS32)) ||
2469 (addrbits == 64 && !(sok & BITS64)))
2470 goto err;
2471
2472 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2473 : ((ix & YMMREG & ~REG_EA)
2474 ? EA_YMMVSIB : EA_XMMVSIB));
2475
2476 output->rex |= rexflags(it, ix, REX_X);
2477 output->rex |= rexflags(bt, bx, REX_B);
2478 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2479
2480 index = it & 7; /* it is known to be != -1 */
2481
2482 switch (s) {
2483 case 1:
2484 scale = 0;
2485 break;
2486 case 2:
2487 scale = 1;
2488 break;
2489 case 4:
2490 scale = 2;
2491 break;
2492 case 8:
2493 scale = 3;
2494 break;
2495 default: /* then what the smeg is it? */
2496 goto err; /* panic */
2497 }
2498
2499 if (bt == -1) {
2500 base = 5;
2501 mod = 0;
2502 } else {
2503 base = (bt & 7);
2504 if (base != REG_NUM_EBP && o == 0 &&
2505 seg == NO_SEG && !forw_ref &&
2506 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2507 mod = 0;
2508 else if (IS_MOD_01())
2509 mod = 1;
2510 else
2511 mod = 2;
2512 }
2513
2514 output->sib_present = true;
2515 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2516 output->modrm = GEN_MODRM(mod, rfield, 4);
2517 output->sib = GEN_SIB(scale, index, base);
2518 } else if ((ix|bx) & (BITS32|BITS64)) {
2519 /*
2520 * it must be a 32/64-bit memory reference. Firstly we have
2521 * to check that all registers involved are type E/Rxx.
2522 */
2523 opflags_t sok = BITS32 | BITS64;
2524 int32_t o = input->offset;
2525
2526 if (it != -1) {
2527 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2528 sok &= ix;
2529 else
2530 goto err;
2531 }
2532
2533 if (bt != -1) {
2534 if (REG_GPR & ~bx)
2535 goto err; /* Invalid register */
2536 if (~sok & bx & SIZE_MASK)
2537 goto err; /* Invalid size */
2538 sok &= bx;
2539 }
2540
2541 /*
2542 * While we're here, ensure the user didn't specify
2543 * WORD or QWORD
2544 */
2545 if (input->disp_size == 16 || input->disp_size == 64)
2546 goto err;
2547
2548 if (addrbits == 16 ||
2549 (addrbits == 32 && !(sok & BITS32)) ||
2550 (addrbits == 64 && !(sok & BITS64)))
2551 goto err;
2552
2553 /* now reorganize base/index */
2554 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2555 ((hb == b && ht == EAH_NOTBASE) ||
2556 (hb == i && ht == EAH_MAKEBASE))) {
2557 /* swap if hints say so */
2558 t = bt, bt = it, it = t;
2559 x = bx, bx = ix, ix = x;
2560 }
2561 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2562 bt = -1, bx = 0, s++;
2563 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2564 /* make single reg base, unless hint */
2565 bt = it, bx = ix, it = -1, ix = 0;
2566 }
2567 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2568 s == 3 || s == 5 || s == 9) && bt == -1)
2569 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2570 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2571 (input->eaflags & EAF_TIMESTWO))
2572 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2573 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2574 if (s == 1 && it == REG_NUM_ESP) {
2575 /* swap ESP into base if scale is 1 */
2576 t = it, it = bt, bt = t;
2577 x = ix, ix = bx, bx = x;
2578 }
2579 if (it == REG_NUM_ESP ||
2580 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2581 goto err; /* wrong, for various reasons */
2582
2583 output->rex |= rexflags(it, ix, REX_X);
2584 output->rex |= rexflags(bt, bx, REX_B);
2585
2586 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2587 /* no SIB needed */
2588 int mod, rm;
2589
2590 if (bt == -1) {
2591 rm = 5;
2592 mod = 0;
2593 } else {
2594 rm = (bt & 7);
2595 if (rm != REG_NUM_EBP && o == 0 &&
2596 seg == NO_SEG && !forw_ref &&
2597 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2598 mod = 0;
2599 else if (IS_MOD_01())
2600 mod = 1;
2601 else
2602 mod = 2;
2603 }
2604
2605 output->sib_present = false;
2606 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2607 output->modrm = GEN_MODRM(mod, rfield, rm);
2608 } else {
2609 /* we need a SIB */
2610 int mod, scale, index, base;
2611
2612 if (it == -1)
2613 index = 4, s = 1;
2614 else
2615 index = (it & 7);
2616
2617 switch (s) {
2618 case 1:
2619 scale = 0;
2620 break;
2621 case 2:
2622 scale = 1;
2623 break;
2624 case 4:
2625 scale = 2;
2626 break;
2627 case 8:
2628 scale = 3;
2629 break;
2630 default: /* then what the smeg is it? */
2631 goto err; /* panic */
2632 }
2633
2634 if (bt == -1) {
2635 base = 5;
2636 mod = 0;
2637 } else {
2638 base = (bt & 7);
2639 if (base != REG_NUM_EBP && o == 0 &&
2640 seg == NO_SEG && !forw_ref &&
2641 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2642 mod = 0;
2643 else if (IS_MOD_01())
2644 mod = 1;
2645 else
2646 mod = 2;
2647 }
2648
2649 output->sib_present = true;
2650 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2651 output->modrm = GEN_MODRM(mod, rfield, 4);
2652 output->sib = GEN_SIB(scale, index, base);
2653 }
2654 } else { /* it's 16-bit */
2655 int mod, rm;
2656 int16_t o = input->offset;
2657
2658 /* check for 64-bit long mode */
2659 if (addrbits == 64)
2660 goto err;
2661
2662 /* check all registers are BX, BP, SI or DI */
2663 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2664 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2665 goto err;
2666
2667 /* ensure the user didn't specify DWORD/QWORD */
2668 if (input->disp_size == 32 || input->disp_size == 64)
2669 goto err;
2670
2671 if (s != 1 && i != -1)
2672 goto err; /* no can do, in 16-bit EA */
2673 if (b == -1 && i != -1) {
2674 int tmp = b;
2675 b = i;
2676 i = tmp;
2677 } /* swap */
2678 if ((b == R_SI || b == R_DI) && i != -1) {
2679 int tmp = b;
2680 b = i;
2681 i = tmp;
2682 }
2683 /* have BX/BP as base, SI/DI index */
2684 if (b == i)
2685 goto err; /* shouldn't ever happen, in theory */
2686 if (i != -1 && b != -1 &&
2687 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2688 goto err; /* invalid combinations */
2689 if (b == -1) /* pure offset: handled above */
2690 goto err; /* so if it gets to here, panic! */
2691
2692 rm = -1;
2693 if (i != -1)
2694 switch (i * 256 + b) {
2695 case R_SI * 256 + R_BX:
2696 rm = 0;
2697 break;
2698 case R_DI * 256 + R_BX:
2699 rm = 1;
2700 break;
2701 case R_SI * 256 + R_BP:
2702 rm = 2;
2703 break;
2704 case R_DI * 256 + R_BP:
2705 rm = 3;
2706 break;
2707 } else
2708 switch (b) {
2709 case R_SI:
2710 rm = 4;
2711 break;
2712 case R_DI:
2713 rm = 5;
2714 break;
2715 case R_BP:
2716 rm = 6;
2717 break;
2718 case R_BX:
2719 rm = 7;
2720 break;
2721 }
2722 if (rm == -1) /* can't happen, in theory */
2723 goto err; /* so panic if it does */
2724
2725 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2726 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2727 mod = 0;
2728 else if (IS_MOD_01())
2729 mod = 1;
2730 else
2731 mod = 2;
2732
2733 output->sib_present = false; /* no SIB - it's 16-bit */
2734 output->bytes = mod; /* bytes of offset needed */
2735 output->modrm = GEN_MODRM(mod, rfield, rm);
2736 }
2737 }
2738 }
2739
2740 output->size = 1 + output->sib_present + output->bytes;
2741 return output->type;
2742
2743 err:
2744 return output->type = EA_INVALID;
2745 }
2746
2747 static void add_asp(insn *ins, int addrbits)
2748 {
2749 int j, valid;
2750 int defdisp;
2751
2752 valid = (addrbits == 64) ? 64|32 : 32|16;
2753
2754 switch (ins->prefixes[PPS_ASIZE]) {
2755 case P_A16:
2756 valid &= 16;
2757 break;
2758 case P_A32:
2759 valid &= 32;
2760 break;
2761 case P_A64:
2762 valid &= 64;
2763 break;
2764 case P_ASP:
2765 valid &= (addrbits == 32) ? 16 : 32;
2766 break;
2767 default:
2768 break;
2769 }
2770
2771 for (j = 0; j < ins->operands; j++) {
2772 if (is_class(MEMORY, ins->oprs[j].type)) {
2773 opflags_t i, b;
2774
2775 /* Verify as Register */
2776 if (!is_register(ins->oprs[j].indexreg))
2777 i = 0;
2778 else
2779 i = nasm_reg_flags[ins->oprs[j].indexreg];
2780
2781 /* Verify as Register */
2782 if (!is_register(ins->oprs[j].basereg))
2783 b = 0;
2784 else
2785 b = nasm_reg_flags[ins->oprs[j].basereg];
2786
2787 if (ins->oprs[j].scale == 0)
2788 i = 0;
2789
2790 if (!i && !b) {
2791 int ds = ins->oprs[j].disp_size;
2792 if ((addrbits != 64 && ds > 8) ||
2793 (addrbits == 64 && ds == 16))
2794 valid &= ds;
2795 } else {
2796 if (!(REG16 & ~b))
2797 valid &= 16;
2798 if (!(REG32 & ~b))
2799 valid &= 32;
2800 if (!(REG64 & ~b))
2801 valid &= 64;
2802
2803 if (!(REG16 & ~i))
2804 valid &= 16;
2805 if (!(REG32 & ~i))
2806 valid &= 32;
2807 if (!(REG64 & ~i))
2808 valid &= 64;
2809 }
2810 }
2811 }
2812
2813 if (valid & addrbits) {
2814 ins->addr_size = addrbits;
2815 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2816 /* Add an address size prefix */
2817 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2818 ins->addr_size = (addrbits == 32) ? 16 : 32;
2819 } else {
2820 /* Impossible... */
2821 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2822 ins->addr_size = addrbits; /* Error recovery */
2823 }
2824
2825 defdisp = ins->addr_size == 16 ? 16 : 32;
2826
2827 for (j = 0; j < ins->operands; j++) {
2828 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2829 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2830 /*
2831 * mem_offs sizes must match the address size; if not,
2832 * strip the MEM_OFFS bit and match only EA instructions
2833 */
2834 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2835 }
2836 }
2837 }
The Netwide Assembler