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Add copyright notice to insns.dat
[nasm.git] / assemble.c
blob535c49c0203b91c3f4c05218d18f7d07f26bf975
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1..\4 - that many literal bytes follow in the code stream
11 * \5 - add 4 to the primary operand number (b, low octdigit)
12 * \6 - add 4 to the secondary operand number (a, middle octdigit)
13 * \7 - add 4 to both the primary and the secondary operand number
14 * \10..\13 - a literal byte follows in the code stream, to be added
15 * to the register value of operand 0..3
16 * \14..\17 - a signed byte immediate operand, from operand 0..3
17 * \20..\23 - a byte immediate operand, from operand 0..3
18 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
19 * \30..\33 - a word immediate operand, from operand 0..3
20 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
21 * assembly mode or the operand-size override on the operand
22 * \40..\43 - a long immediate operand, from operand 0..3
23 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
24 * depending on the address size of the instruction.
25 * \50..\53 - a byte relative operand, from operand 0..3
26 * \54..\57 - a qword immediate operand, from operand 0..3
27 * \60..\63 - a word relative operand, from operand 0..3
28 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
29 * assembly mode or the operand-size override on the operand
30 * \70..\73 - a long relative operand, from operand 0..3
31 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
32 * \1ab - a ModRM, calculated on EA in operand a, with the spare
33 * field the register value of operand b.
34 * \140..\143 - an immediate word or signed byte for operand 0..3
35 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
36 * is a signed byte rather than a word. Opcode byte follows.
37 * \150..\153 - an immediate dword or signed byte for operand 0..3
38 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
39 * is a signed byte rather than a dword. Opcode byte follows.
40 * \160..\163 - this instruction uses DREX rather than REX, with the
41 * OC0 field set to 0, and the dest field taken from
42 * operand 0..3.
43 * \164..\167 - this instruction uses DREX rather than REX, with the
44 * OC0 field set to 1, and the dest field taken from
45 * operand 0..3.
46 * \171 - placement of DREX suffix in the absence of an EA
47 * \172\ab - the register number from operand a in bits 7..4, with
48 * the 4-bit immediate from operand b in bits 3..0.
49 * \173\xab - the register number from operand a in bits 7..4, with
50 * the value b in bits 3..0.
51 * \174\a - the register number from operand a in bits 7..4, and
52 * an arbitrary value in bits 3..0 (assembled as zero.)
53 * \2ab - a ModRM, calculated on EA in operand a, with the spare
54 * field equal to digit b.
55 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
56 * is not equal to the truncated and sign-extended 32-bit
57 * operand; used for 32-bit immediates in 64-bit mode.
58 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
59 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
60 * V field taken from operand 0..3.
61 * \270 - this instruction uses VEX/XOP rather than REX, with the
62 * V field set to 1111b.
63 *
64 * VEX/XOP prefixes are followed by the sequence:
65 * \tmm\wlp where mm is the M field; and wlp is:
66 * 00 0ww lpp
67 * [w0] ww = 0 for W = 0
68 * [w1] ww = 1 for W = 1
69 * [wx] ww = 2 for W don't care (always assembled as 0)
70 * [ww] ww = 3 for W used as REX.W
71 *
72 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
73 *
74 * \274..\277 - a signed byte immediate operand, from operand 0..3,
75 * which is to be extended to the operand size.
76 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
77 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
78 * \312 - (disassembler only) invalid with non-default address size.
79 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
80 * \314 - (disassembler only) invalid with REX.B
81 * \315 - (disassembler only) invalid with REX.X
82 * \316 - (disassembler only) invalid with REX.R
83 * \317 - (disassembler only) invalid with REX.W
84 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
85 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
86 * \322 - indicates that this instruction is only valid when the
87 * operand size is the default (instruction to disassembler,
88 * generates no code in the assembler)
89 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
90 * \324 - indicates 64-bit operand size requiring REX prefix.
91 * \325 - instruction which always uses spl/bpl/sil/dil
92 * \330 - a literal byte follows in the code stream, to be added
93 * to the condition code value of the instruction.
94 * \331 - instruction not valid with REP prefix. Hint for
95 * disassembler only; for SSE instructions.
96 * \332 - REP prefix (0xF2 byte) used as opcode extension.
97 * \333 - REP prefix (0xF3 byte) used as opcode extension.
98 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
99 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
100 * \336 - force a REP(E) prefix (0xF2) even if not specified.
101 * \337 - force a REPNE prefix (0xF3) even if not specified.
102 * \336-\337 are still listed as prefixes in the disassembler.
103 * \340 - reserve <operand 0> bytes of uninitialized storage.
104 * Operand 0 had better be a segmentless constant.
105 * \341 - this instruction needs a WAIT "prefix"
106 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
107 * (POP is never used for CS) depending on operand 0
108 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
109 * on operand 0
110 * \360 - no SSE prefix (== \364\331)
111 * \361 - 66 SSE prefix (== \366\331)
112 * \362 - F2 SSE prefix (== \364\332)
113 * \363 - F3 SSE prefix (== \364\333)
114 * \364 - operand-size prefix (0x66) not permitted
115 * \365 - address-size prefix (0x67) not permitted
116 * \366 - operand-size prefix (0x66) used as opcode extension
117 * \367 - address-size prefix (0x67) used as opcode extension
118 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
119 * 370 is used for Jcc, 371 is used for JMP.
120 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
121 * used for conditional jump over longer jump
122 */
123
124 #include "compiler.h"
125
126 #include <stdio.h>
127 #include <string.h>
128 #include <inttypes.h>
129
130 #include "nasm.h"
131 #include "nasmlib.h"
132 #include "assemble.h"
133 #include "insns.h"
134 #include "tables.h"
135
136 typedef struct {
137 int sib_present; /* is a SIB byte necessary? */
138 int bytes; /* # of bytes of offset needed */
139 int size; /* lazy - this is sib+bytes+1 */
140 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
141 } ea;
142
143 static uint32_t cpu; /* cpu level received from nasm.c */
144 static efunc errfunc;
145 static struct ofmt *outfmt;
146 static ListGen *list;
147
148 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
149 static void gencode(int32_t segment, int64_t offset, int bits,
150 insn * ins, const struct itemplate *temp,
151 int64_t insn_end);
152 static int matches(const struct itemplate *, insn *, int bits);
153 static int32_t regflag(const operand *);
154 static int32_t regval(const operand *);
155 static int rexflags(int, int32_t, int);
156 static int op_rexflags(const operand *, int);
157 static ea *process_ea(operand *, ea *, int, int, int, int32_t);
158 static void add_asp(insn *, int);
159
160 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
161 {
162 return ins->prefixes[pos] == prefix;
163 }
164
165 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
166 {
167 if (ins->prefixes[pos])
168 errfunc(ERR_NONFATAL, "invalid %s prefix",
169 prefix_name(ins->prefixes[pos]));
170 }
171
172 static const char *size_name(int size)
173 {
174 switch (size) {
175 case 1:
176 return "byte";
177 case 2:
178 return "word";
179 case 4:
180 return "dword";
181 case 8:
182 return "qword";
183 case 10:
184 return "tword";
185 case 16:
186 return "oword";
187 case 32:
188 return "yword";
189 default:
190 return "???";
191 }
192 }
193
194 static void warn_overflow(int size, const struct operand *o)
195 {
196 if (size < 8 && o->wrt == NO_SEG && o->segment == NO_SEG) {
197 int64_t lim = ((int64_t)1 << (size*8))-1;
198 int64_t data = o->offset;
199
200 if (data < ~lim || data > lim)
201 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
202 "%s data exceeds bounds", size_name(size));
203 }
204 }
205 /*
206 * This routine wrappers the real output format's output routine,
207 * in order to pass a copy of the data off to the listing file
208 * generator at the same time.
209 */
210 static void out(int64_t offset, int32_t segto, const void *data,
211 enum out_type type, uint64_t size,
212 int32_t segment, int32_t wrt)
213 {
214 static int32_t lineno = 0; /* static!!! */
215 static char *lnfname = NULL;
216 uint8_t p[8];
217
218 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
219 /*
220 * This is a non-relocated address, and we're going to
221 * convert it into RAWDATA format.
222 */
223 uint8_t *q = p;
224
225 if (size > 8) {
226 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
227 return;
228 }
229
230 WRITEADDR(q, *(int64_t *)data, size);
231 data = p;
232 type = OUT_RAWDATA;
233 }
234
235 list->output(offset, data, type, size);
236
237 /*
238 * this call to src_get determines when we call the
239 * debug-format-specific "linenum" function
240 * it updates lineno and lnfname to the current values
241 * returning 0 if "same as last time", -2 if lnfname
242 * changed, and the amount by which lineno changed,
243 * if it did. thus, these variables must be static
244 */
245
246 if (src_get(&lineno, &lnfname)) {
247 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
248 }
249
250 outfmt->output(segto, data, type, size, segment, wrt);
251 }
252
253 static bool jmp_match(int32_t segment, int64_t offset, int bits,
254 insn * ins, const uint8_t *code)
255 {
256 int64_t isize;
257 uint8_t c = code[0];
258
259 if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT))
260 return false;
261 if (!optimizing)
262 return false;
263 if (optimizing < 0 && c == 0371)
264 return false;
265
266 isize = calcsize(segment, offset, bits, ins, code);
267
268 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
269 /* Be optimistic in pass 1 */
270 return true;
271
272 if (ins->oprs[0].segment != segment)
273 return false;
274
275 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
276 return (isize >= -128 && isize <= 127); /* is it byte size? */
277 }
278
279 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
280 insn * instruction, struct ofmt *output, efunc error,
281 ListGen * listgen)
282 {
283 const struct itemplate *temp;
284 int j;
285 int size_prob;
286 int64_t insn_end;
287 int32_t itimes;
288 int64_t start = offset;
289 int64_t wsize = 0; /* size for DB etc. */
290
291 errfunc = error; /* to pass to other functions */
292 cpu = cp;
293 outfmt = output; /* likewise */
294 list = listgen; /* and again */
295
296 switch (instruction->opcode) {
297 case -1:
298 return 0;
299 case I_DB:
300 wsize = 1;
301 break;
302 case I_DW:
303 wsize = 2;
304 break;
305 case I_DD:
306 wsize = 4;
307 break;
308 case I_DQ:
309 wsize = 8;
310 break;
311 case I_DT:
312 wsize = 10;
313 break;
314 case I_DO:
315 wsize = 16;
316 break;
317 case I_DY:
318 wsize = 32;
319 break;
320 default:
321 break;
322 }
323
324 if (wsize) {
325 extop *e;
326 int32_t t = instruction->times;
327 if (t < 0)
328 errfunc(ERR_PANIC,
329 "instruction->times < 0 (%ld) in assemble()", t);
330
331 while (t--) { /* repeat TIMES times */
332 for (e = instruction->eops; e; e = e->next) {
333 if (e->type == EOT_DB_NUMBER) {
334 if (wsize == 1) {
335 if (e->segment != NO_SEG)
336 errfunc(ERR_NONFATAL,
337 "one-byte relocation attempted");
338 else {
339 uint8_t out_byte = e->offset;
340 out(offset, segment, &out_byte,
341 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
342 }
343 } else if (wsize > 8) {
344 errfunc(ERR_NONFATAL,
345 "integer supplied to a DT, DO or DY"
346 " instruction");
347 } else
348 out(offset, segment, &e->offset,
349 OUT_ADDRESS, wsize, e->segment, e->wrt);
350 offset += wsize;
351 } else if (e->type == EOT_DB_STRING ||
352 e->type == EOT_DB_STRING_FREE) {
353 int align;
354
355 out(offset, segment, e->stringval,
356 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
357 align = e->stringlen % wsize;
358
359 if (align) {
360 align = wsize - align;
361 out(offset, segment, zero_buffer,
362 OUT_RAWDATA, align, NO_SEG, NO_SEG);
363 }
364 offset += e->stringlen + align;
365 }
366 }
367 if (t > 0 && t == instruction->times - 1) {
368 /*
369 * Dummy call to list->output to give the offset to the
370 * listing module.
371 */
372 list->output(offset, NULL, OUT_RAWDATA, 0);
373 list->uplevel(LIST_TIMES);
374 }
375 }
376 if (instruction->times > 1)
377 list->downlevel(LIST_TIMES);
378 return offset - start;
379 }
380
381 if (instruction->opcode == I_INCBIN) {
382 const char *fname = instruction->eops->stringval;
383 FILE *fp;
384
385 fp = fopen(fname, "rb");
386 if (!fp) {
387 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
388 fname);
389 } else if (fseek(fp, 0L, SEEK_END) < 0) {
390 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
391 fname);
392 } else {
393 static char buf[4096];
394 size_t t = instruction->times;
395 size_t base = 0;
396 size_t len;
397
398 len = ftell(fp);
399 if (instruction->eops->next) {
400 base = instruction->eops->next->offset;
401 len -= base;
402 if (instruction->eops->next->next &&
403 len > (size_t)instruction->eops->next->next->offset)
404 len = (size_t)instruction->eops->next->next->offset;
405 }
406 /*
407 * Dummy call to list->output to give the offset to the
408 * listing module.
409 */
410 list->output(offset, NULL, OUT_RAWDATA, 0);
411 list->uplevel(LIST_INCBIN);
412 while (t--) {
413 size_t l;
414
415 fseek(fp, base, SEEK_SET);
416 l = len;
417 while (l > 0) {
418 int32_t m;
419 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
420 if (!m) {
421 /*
422 * This shouldn't happen unless the file
423 * actually changes while we are reading
424 * it.
425 */
426 error(ERR_NONFATAL,
427 "`incbin': unexpected EOF while"
428 " reading file `%s'", fname);
429 t = 0; /* Try to exit cleanly */
430 break;
431 }
432 out(offset, segment, buf, OUT_RAWDATA, m,
433 NO_SEG, NO_SEG);
434 l -= m;
435 }
436 }
437 list->downlevel(LIST_INCBIN);
438 if (instruction->times > 1) {
439 /*
440 * Dummy call to list->output to give the offset to the
441 * listing module.
442 */
443 list->output(offset, NULL, OUT_RAWDATA, 0);
444 list->uplevel(LIST_TIMES);
445 list->downlevel(LIST_TIMES);
446 }
447 fclose(fp);
448 return instruction->times * len;
449 }
450 return 0; /* if we're here, there's an error */
451 }
452
453 /* Check to see if we need an address-size prefix */
454 add_asp(instruction, bits);
455
456 size_prob = 0;
457
458 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
459 int m = matches(temp, instruction, bits);
460 if (m == 100 ||
461 (m == 99 && jmp_match(segment, offset, bits,
462 instruction, temp->code))) {
463 /* Matches! */
464 int64_t insn_size = calcsize(segment, offset, bits,
465 instruction, temp->code);
466 itimes = instruction->times;
467 if (insn_size < 0) /* shouldn't be, on pass two */
468 error(ERR_PANIC, "errors made it through from pass one");
469 else
470 while (itimes--) {
471 for (j = 0; j < MAXPREFIX; j++) {
472 uint8_t c = 0;
473 switch (instruction->prefixes[j]) {
474 case P_WAIT:
475 c = 0x9B;
476 break;
477 case P_LOCK:
478 c = 0xF0;
479 break;
480 case P_REPNE:
481 case P_REPNZ:
482 c = 0xF2;
483 break;
484 case P_REPE:
485 case P_REPZ:
486 case P_REP:
487 c = 0xF3;
488 break;
489 case R_CS:
490 if (bits == 64) {
491 error(ERR_WARNING | ERR_PASS2,
492 "cs segment base generated, but will be ignored in 64-bit mode");
493 }
494 c = 0x2E;
495 break;
496 case R_DS:
497 if (bits == 64) {
498 error(ERR_WARNING | ERR_PASS2,
499 "ds segment base generated, but will be ignored in 64-bit mode");
500 }
501 c = 0x3E;
502 break;
503 case R_ES:
504 if (bits == 64) {
505 error(ERR_WARNING | ERR_PASS2,
506 "es segment base generated, but will be ignored in 64-bit mode");
507 }
508 c = 0x26;
509 break;
510 case R_FS:
511 c = 0x64;
512 break;
513 case R_GS:
514 c = 0x65;
515 break;
516 case R_SS:
517 if (bits == 64) {
518 error(ERR_WARNING | ERR_PASS2,
519 "ss segment base generated, but will be ignored in 64-bit mode");
520 }
521 c = 0x36;
522 break;
523 case R_SEGR6:
524 case R_SEGR7:
525 error(ERR_NONFATAL,
526 "segr6 and segr7 cannot be used as prefixes");
527 break;
528 case P_A16:
529 if (bits == 64) {
530 error(ERR_NONFATAL,
531 "16-bit addressing is not supported "
532 "in 64-bit mode");
533 } else if (bits != 16)
534 c = 0x67;
535 break;
536 case P_A32:
537 if (bits != 32)
538 c = 0x67;
539 break;
540 case P_A64:
541 if (bits != 64) {
542 error(ERR_NONFATAL,
543 "64-bit addressing is only supported "
544 "in 64-bit mode");
545 }
546 break;
547 case P_ASP:
548 c = 0x67;
549 break;
550 case P_O16:
551 if (bits != 16)
552 c = 0x66;
553 break;
554 case P_O32:
555 if (bits == 16)
556 c = 0x66;
557 break;
558 case P_O64:
559 /* REX.W */
560 break;
561 case P_OSP:
562 c = 0x66;
563 break;
564 case P_none:
565 break;
566 default:
567 error(ERR_PANIC, "invalid instruction prefix");
568 }
569 if (c != 0) {
570 out(offset, segment, &c, OUT_RAWDATA, 1,
571 NO_SEG, NO_SEG);
572 offset++;
573 }
574 }
575 insn_end = offset + insn_size;
576 gencode(segment, offset, bits, instruction,
577 temp, insn_end);
578 offset += insn_size;
579 if (itimes > 0 && itimes == instruction->times - 1) {
580 /*
581 * Dummy call to list->output to give the offset to the
582 * listing module.
583 */
584 list->output(offset, NULL, OUT_RAWDATA, 0);
585 list->uplevel(LIST_TIMES);
586 }
587 }
588 if (instruction->times > 1)
589 list->downlevel(LIST_TIMES);
590 return offset - start;
591 } else if (m > 0 && m > size_prob) {
592 size_prob = m;
593 }
594 }
595
596 if (temp->opcode == -1) { /* didn't match any instruction */
597 switch (size_prob) {
598 case 1:
599 error(ERR_NONFATAL, "operation size not specified");
600 break;
601 case 2:
602 error(ERR_NONFATAL, "mismatch in operand sizes");
603 break;
604 case 3:
605 error(ERR_NONFATAL, "no instruction for this cpu level");
606 break;
607 case 4:
608 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
609 bits);
610 break;
611 default:
612 error(ERR_NONFATAL,
613 "invalid combination of opcode and operands");
614 break;
615 }
616 }
617 return 0;
618 }
619
620 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
621 insn * instruction, efunc error)
622 {
623 const struct itemplate *temp;
624
625 errfunc = error; /* to pass to other functions */
626 cpu = cp;
627
628 if (instruction->opcode == -1)
629 return 0;
630
631 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
632 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
633 instruction->opcode == I_DT || instruction->opcode == I_DO ||
634 instruction->opcode == I_DY) {
635 extop *e;
636 int32_t isize, osize, wsize = 0; /* placate gcc */
637
638 isize = 0;
639 switch (instruction->opcode) {
640 case I_DB:
641 wsize = 1;
642 break;
643 case I_DW:
644 wsize = 2;
645 break;
646 case I_DD:
647 wsize = 4;
648 break;
649 case I_DQ:
650 wsize = 8;
651 break;
652 case I_DT:
653 wsize = 10;
654 break;
655 case I_DO:
656 wsize = 16;
657 break;
658 case I_DY:
659 wsize = 32;
660 break;
661 default:
662 break;
663 }
664
665 for (e = instruction->eops; e; e = e->next) {
666 int32_t align;
667
668 osize = 0;
669 if (e->type == EOT_DB_NUMBER)
670 osize = 1;
671 else if (e->type == EOT_DB_STRING ||
672 e->type == EOT_DB_STRING_FREE)
673 osize = e->stringlen;
674
675 align = (-osize) % wsize;
676 if (align < 0)
677 align += wsize;
678 isize += osize + align;
679 }
680 return isize * instruction->times;
681 }
682
683 if (instruction->opcode == I_INCBIN) {
684 const char *fname = instruction->eops->stringval;
685 FILE *fp;
686 size_t len;
687
688 fp = fopen(fname, "rb");
689 if (!fp)
690 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
691 fname);
692 else if (fseek(fp, 0L, SEEK_END) < 0)
693 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
694 fname);
695 else {
696 len = ftell(fp);
697 fclose(fp);
698 if (instruction->eops->next) {
699 len -= instruction->eops->next->offset;
700 if (instruction->eops->next->next &&
701 len > (size_t)instruction->eops->next->next->offset) {
702 len = (size_t)instruction->eops->next->next->offset;
703 }
704 }
705 return instruction->times * len;
706 }
707 return 0; /* if we're here, there's an error */
708 }
709
710 /* Check to see if we need an address-size prefix */
711 add_asp(instruction, bits);
712
713 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
714 int m = matches(temp, instruction, bits);
715 if (m == 100 ||
716 (m == 99 && jmp_match(segment, offset, bits,
717 instruction, temp->code))) {
718 /* we've matched an instruction. */
719 int64_t isize;
720 const uint8_t *codes = temp->code;
721 int j;
722
723 isize = calcsize(segment, offset, bits, instruction, codes);
724 if (isize < 0)
725 return -1;
726 for (j = 0; j < MAXPREFIX; j++) {
727 switch (instruction->prefixes[j]) {
728 case P_A16:
729 if (bits != 16)
730 isize++;
731 break;
732 case P_A32:
733 if (bits != 32)
734 isize++;
735 break;
736 case P_O16:
737 if (bits != 16)
738 isize++;
739 break;
740 case P_O32:
741 if (bits == 16)
742 isize++;
743 break;
744 case P_A64:
745 case P_O64:
746 case P_none:
747 break;
748 default:
749 isize++;
750 break;
751 }
752 }
753 return isize * instruction->times;
754 }
755 }
756 return -1; /* didn't match any instruction */
757 }
758
759 static bool possible_sbyte(operand *o)
760 {
761 return o->wrt == NO_SEG && o->segment == NO_SEG &&
762 !(o->opflags & OPFLAG_UNKNOWN) &&
763 optimizing >= 0 && !(o->type & STRICT);
764 }
765
766 /* check that opn[op] is a signed byte of size 16 or 32 */
767 static bool is_sbyte16(operand *o)
768 {
769 int16_t v;
770
771 if (!possible_sbyte(o))
772 return false;
773
774 v = o->offset;
775 return v >= -128 && v <= 127;
776 }
777
778 static bool is_sbyte32(operand *o)
779 {
780 int32_t v;
781
782 if (!possible_sbyte(o))
783 return false;
784
785 v = o->offset;
786 return v >= -128 && v <= 127;
787 }
788
789 /* Common construct */
790 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
791
792 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
793 insn * ins, const uint8_t *codes)
794 {
795 int64_t length = 0;
796 uint8_t c;
797 int rex_mask = ~0;
798 int op1, op2;
799 struct operand *opx;
800 uint8_t opex = 0;
801
802 ins->rex = 0; /* Ensure REX is reset */
803
804 if (ins->prefixes[PPS_OSIZE] == P_O64)
805 ins->rex |= REX_W;
806
807 (void)segment; /* Don't warn that this parameter is unused */
808 (void)offset; /* Don't warn that this parameter is unused */
809
810 while (*codes) {
811 c = *codes++;
812 op1 = (c & 3) + ((opex & 1) << 2);
813 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
814 opx = &ins->oprs[op1];
815 opex = 0; /* For the next iteration */
816
817 switch (c) {
818 case 01:
819 case 02:
820 case 03:
821 case 04:
822 codes += c, length += c;
823 break;
824
825 case 05:
826 case 06:
827 case 07:
828 opex = c;
829 break;
830
831 case4(010):
832 ins->rex |=
833 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
834 codes++, length++;
835 break;
836
837 case4(014):
838 case4(020):
839 case4(024):
840 length++;
841 break;
842
843 case4(030):
844 length += 2;
845 break;
846
847 case4(034):
848 if (opx->type & (BITS16 | BITS32 | BITS64))
849 length += (opx->type & BITS16) ? 2 : 4;
850 else
851 length += (bits == 16) ? 2 : 4;
852 break;
853
854 case4(040):
855 length += 4;
856 break;
857
858 case4(044):
859 length += ins->addr_size >> 3;
860 break;
861
862 case4(050):
863 length++;
864 break;
865
866 case4(054):
867 length += 8; /* MOV reg64/imm */
868 break;
869
870 case4(060):
871 length += 2;
872 break;
873
874 case4(064):
875 if (opx->type & (BITS16 | BITS32 | BITS64))
876 length += (opx->type & BITS16) ? 2 : 4;
877 else
878 length += (bits == 16) ? 2 : 4;
879 break;
880
881 case4(070):
882 length += 4;
883 break;
884
885 case4(074):
886 length += 2;
887 break;
888
889 case4(0140):
890 length += is_sbyte16(opx) ? 1 : 2;
891 break;
892
893 case4(0144):
894 codes++;
895 length++;
896 break;
897
898 case4(0150):
899 length += is_sbyte32(opx) ? 1 : 4;
900 break;
901
902 case4(0154):
903 codes++;
904 length++;
905 break;
906
907 case4(0160):
908 length++;
909 ins->rex |= REX_D;
910 ins->drexdst = regval(opx);
911 break;
912
913 case4(0164):
914 length++;
915 ins->rex |= REX_D|REX_OC;
916 ins->drexdst = regval(opx);
917 break;
918
919 case 0171:
920 break;
921
922 case 0172:
923 case 0173:
924 case 0174:
925 codes++;
926 length++;
927 break;
928
929 case4(0250):
930 length += is_sbyte32(opx) ? 1 : 4;
931 break;
932
933 case4(0254):
934 length += 4;
935 break;
936
937 case4(0260):
938 ins->rex |= REX_V;
939 ins->drexdst = regval(opx);
940 ins->vex_cm = *codes++;
941 ins->vex_wlp = *codes++;
942 break;
943
944 case 0270:
945 ins->rex |= REX_V;
946 ins->drexdst = 0;
947 ins->vex_cm = *codes++;
948 ins->vex_wlp = *codes++;
949 break;
950
951 case4(0274):
952 length++;
953 break;
954
955 case4(0300):
956 break;
957
958 case 0310:
959 if (bits == 64)
960 return -1;
961 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
962 break;
963
964 case 0311:
965 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
966 break;
967
968 case 0312:
969 break;
970
971 case 0313:
972 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
973 has_prefix(ins, PPS_ASIZE, P_A32))
974 return -1;
975 break;
976
977 case4(0314):
978 break;
979
980 case 0320:
981 length += (bits != 16);
982 break;
983
984 case 0321:
985 length += (bits == 16);
986 break;
987
988 case 0322:
989 break;
990
991 case 0323:
992 rex_mask &= ~REX_W;
993 break;
994
995 case 0324:
996 ins->rex |= REX_W;
997 break;
998
999 case 0325:
1000 ins->rex |= REX_NH;
1001 break;
1002
1003 case 0330:
1004 codes++, length++;
1005 break;
1006
1007 case 0331:
1008 break;
1009
1010 case 0332:
1011 case 0333:
1012 length++;
1013 break;
1014
1015 case 0334:
1016 ins->rex |= REX_L;
1017 break;
1018
1019 case 0335:
1020 break;
1021
1022 case 0336:
1023 if (!ins->prefixes[PPS_LREP])
1024 ins->prefixes[PPS_LREP] = P_REP;
1025 break;
1026
1027 case 0337:
1028 if (!ins->prefixes[PPS_LREP])
1029 ins->prefixes[PPS_LREP] = P_REPNE;
1030 break;
1031
1032 case 0340:
1033 if (ins->oprs[0].segment != NO_SEG)
1034 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1035 " quantity of BSS space");
1036 else
1037 length += ins->oprs[0].offset;
1038 break;
1039
1040 case 0341:
1041 if (!ins->prefixes[PPS_WAIT])
1042 ins->prefixes[PPS_WAIT] = P_WAIT;
1043 break;
1044
1045 case4(0344):
1046 length++;
1047 break;
1048
1049 case 0360:
1050 break;
1051
1052 case 0361:
1053 case 0362:
1054 case 0363:
1055 length++;
1056 break;
1057
1058 case 0364:
1059 case 0365:
1060 break;
1061
1062 case 0366:
1063 case 0367:
1064 length++;
1065 break;
1066
1067 case 0370:
1068 case 0371:
1069 case 0372:
1070 break;
1071
1072 case 0373:
1073 length++;
1074 break;
1075
1076 case4(0100):
1077 case4(0110):
1078 case4(0120):
1079 case4(0130):
1080 case4(0200):
1081 case4(0204):
1082 case4(0210):
1083 case4(0214):
1084 case4(0220):
1085 case4(0224):
1086 case4(0230):
1087 case4(0234):
1088 {
1089 ea ea_data;
1090 int rfield;
1091 int32_t rflags;
1092 struct operand *opy = &ins->oprs[op2];
1093
1094 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1095
1096 if (c <= 0177) {
1097 /* pick rfield from operand b (opx) */
1098 rflags = regflag(opx);
1099 rfield = nasm_regvals[opx->basereg];
1100 } else {
1101 rflags = 0;
1102 rfield = c & 7;
1103 }
1104 if (!process_ea(opy, &ea_data, bits,
1105 ins->addr_size, rfield, rflags)) {
1106 errfunc(ERR_NONFATAL, "invalid effective address");
1107 return -1;
1108 } else {
1109 ins->rex |= ea_data.rex;
1110 length += ea_data.size;
1111 }
1112 }
1113 break;
1114
1115 default:
1116 errfunc(ERR_PANIC, "internal instruction table corrupt"
1117 ": instruction code \\%o (0x%02X) given", c, c);
1118 break;
1119 }
1120 }
1121
1122 ins->rex &= rex_mask;
1123
1124 if (ins->rex & REX_NH) {
1125 if (ins->rex & REX_H) {
1126 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1127 return -1;
1128 }
1129 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1130 }
1131
1132 if (ins->rex & REX_V) {
1133 int bad32 = REX_R|REX_W|REX_X|REX_B;
1134
1135 if (ins->rex & REX_H) {
1136 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1137 return -1;
1138 }
1139 switch (ins->vex_wlp & 030) {
1140 case 000:
1141 case 020:
1142 ins->rex &= ~REX_W;
1143 break;
1144 case 010:
1145 ins->rex |= REX_W;
1146 bad32 &= ~REX_W;
1147 break;
1148 case 030:
1149 /* Follow REX_W */
1150 break;
1151 }
1152
1153 if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
1154 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1155 return -1;
1156 }
1157 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_R|REX_B)))
1158 length += 3;
1159 else
1160 length += 2;
1161 } else if (ins->rex & REX_D) {
1162 if (ins->rex & REX_H) {
1163 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1164 return -1;
1165 }
1166 if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
1167 ins->drexdst > 7)) {
1168 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1169 return -1;
1170 }
1171 length++;
1172 } else if (ins->rex & REX_REAL) {
1173 if (ins->rex & REX_H) {
1174 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1175 return -1;
1176 } else if (bits == 64) {
1177 length++;
1178 } else if ((ins->rex & REX_L) &&
1179 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1180 cpu >= IF_X86_64) {
1181 /* LOCK-as-REX.R */
1182 assert_no_prefix(ins, PPS_LREP);
1183 length++;
1184 } else {
1185 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1186 return -1;
1187 }
1188 }
1189
1190 return length;
1191 }
1192
1193 #define EMIT_REX() \
1194 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1195 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1196 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1197 ins->rex = 0; \
1198 offset += 1; \
1199 }
1200
1201 static void gencode(int32_t segment, int64_t offset, int bits,
1202 insn * ins, const struct itemplate *temp,
1203 int64_t insn_end)
1204 {
1205 static char condval[] = { /* conditional opcodes */
1206 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1207 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1208 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1209 };
1210 uint8_t c;
1211 uint8_t bytes[4];
1212 int64_t size;
1213 int64_t data;
1214 int op1, op2;
1215 struct operand *opx;
1216 const uint8_t *codes = temp->code;
1217 uint8_t opex = 0;
1218
1219 while (*codes) {
1220 c = *codes++;
1221 op1 = (c & 3) + ((opex & 1) << 2);
1222 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1223 opx = &ins->oprs[op1];
1224 opex = 0; /* For the next iteration */
1225
1226 switch (c) {
1227 case 01:
1228 case 02:
1229 case 03:
1230 case 04:
1231 EMIT_REX();
1232 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1233 codes += c;
1234 offset += c;
1235 break;
1236
1237 case 05:
1238 case 06:
1239 case 07:
1240 opex = c;
1241 break;
1242
1243 case4(010):
1244 EMIT_REX();
1245 bytes[0] = *codes++ + (regval(opx) & 7);
1246 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1247 offset += 1;
1248 break;
1249
1250 case4(014):
1251 /* The test for BITS8 and SBYTE here is intended to avoid
1252 warning on optimizer actions due to SBYTE, while still
1253 warn on explicit BYTE directives. Also warn, obviously,
1254 if the optimizer isn't enabled. */
1255 if (((opx->type & BITS8) ||
1256 !(opx->type & temp->opd[op1] & BYTENESS)) &&
1257 (opx->offset < -128 || opx->offset > 127)) {
1258 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1259 "signed byte value exceeds bounds");
1260 }
1261 if (opx->segment != NO_SEG) {
1262 data = opx->offset;
1263 out(offset, segment, &data, OUT_ADDRESS, 1,
1264 opx->segment, opx->wrt);
1265 } else {
1266 bytes[0] = opx->offset;
1267 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1268 NO_SEG);
1269 }
1270 offset += 1;
1271 break;
1272
1273 case4(020):
1274 if (opx->offset < -256 || opx->offset > 255) {
1275 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1276 "byte value exceeds bounds");
1277 }
1278 if (opx->segment != NO_SEG) {
1279 data = opx->offset;
1280 out(offset, segment, &data, OUT_ADDRESS, 1,
1281 opx->segment, opx->wrt);
1282 } else {
1283 bytes[0] = opx->offset;
1284 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1285 NO_SEG);
1286 }
1287 offset += 1;
1288 break;
1289
1290 case4(024):
1291 if (opx->offset < 0 || opx->offset > 255)
1292 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1293 "unsigned byte value exceeds bounds");
1294 if (opx->segment != NO_SEG) {
1295 data = opx->offset;
1296 out(offset, segment, &data, OUT_ADDRESS, 1,
1297 opx->segment, opx->wrt);
1298 } else {
1299 bytes[0] = opx->offset;
1300 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1301 NO_SEG);
1302 }
1303 offset += 1;
1304 break;
1305
1306 case4(030):
1307 warn_overflow(2, opx);
1308 data = opx->offset;
1309 out(offset, segment, &data, OUT_ADDRESS, 2,
1310 opx->segment, opx->wrt);
1311 offset += 2;
1312 break;
1313
1314 case4(034):
1315 if (opx->type & (BITS16 | BITS32))
1316 size = (opx->type & BITS16) ? 2 : 4;
1317 else
1318 size = (bits == 16) ? 2 : 4;
1319 warn_overflow(size, opx);
1320 data = opx->offset;
1321 out(offset, segment, &data, OUT_ADDRESS, size,
1322 opx->segment, opx->wrt);
1323 offset += size;
1324 break;
1325
1326 case4(040):
1327 warn_overflow(4, opx);
1328 data = opx->offset;
1329 out(offset, segment, &data, OUT_ADDRESS, 4,
1330 opx->segment, opx->wrt);
1331 offset += 4;
1332 break;
1333
1334 case4(044):
1335 data = opx->offset;
1336 size = ins->addr_size >> 3;
1337 warn_overflow(size, opx);
1338 out(offset, segment, &data, OUT_ADDRESS, size,
1339 opx->segment, opx->wrt);
1340 offset += size;
1341 break;
1342
1343 case4(050):
1344 if (opx->segment != segment)
1345 errfunc(ERR_NONFATAL,
1346 "short relative jump outside segment");
1347 data = opx->offset - insn_end;
1348 if (data > 127 || data < -128)
1349 errfunc(ERR_NONFATAL, "short jump is out of range");
1350 bytes[0] = data;
1351 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1352 offset += 1;
1353 break;
1354
1355 case4(054):
1356 data = (int64_t)opx->offset;
1357 out(offset, segment, &data, OUT_ADDRESS, 8,
1358 opx->segment, opx->wrt);
1359 offset += 8;
1360 break;
1361
1362 case4(060):
1363 if (opx->segment != segment) {
1364 data = opx->offset;
1365 out(offset, segment, &data,
1366 OUT_REL2ADR, insn_end - offset,
1367 opx->segment, opx->wrt);
1368 } else {
1369 data = opx->offset - insn_end;
1370 out(offset, segment, &data,
1371 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1372 }
1373 offset += 2;
1374 break;
1375
1376 case4(064):
1377 if (opx->type & (BITS16 | BITS32 | BITS64))
1378 size = (opx->type & BITS16) ? 2 : 4;
1379 else
1380 size = (bits == 16) ? 2 : 4;
1381 if (opx->segment != segment) {
1382 data = opx->offset;
1383 out(offset, segment, &data,
1384 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1385 insn_end - offset, opx->segment, opx->wrt);
1386 } else {
1387 data = opx->offset - insn_end;
1388 out(offset, segment, &data,
1389 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1390 }
1391 offset += size;
1392 break;
1393
1394 case4(070):
1395 if (opx->segment != segment) {
1396 data = opx->offset;
1397 out(offset, segment, &data,
1398 OUT_REL4ADR, insn_end - offset,
1399 opx->segment, opx->wrt);
1400 } else {
1401 data = opx->offset - insn_end;
1402 out(offset, segment, &data,
1403 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1404 }
1405 offset += 4;
1406 break;
1407
1408 case4(074):
1409 if (opx->segment == NO_SEG)
1410 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1411 " relocatable");
1412 data = 0;
1413 out(offset, segment, &data, OUT_ADDRESS, 2,
1414 outfmt->segbase(1 + opx->segment),
1415 opx->wrt);
1416 offset += 2;
1417 break;
1418
1419 case4(0140):
1420 data = opx->offset;
1421 warn_overflow(2, opx);
1422 if (is_sbyte16(opx)) {
1423 bytes[0] = data;
1424 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1425 NO_SEG);
1426 offset++;
1427 } else {
1428 out(offset, segment, &data, OUT_ADDRESS, 2,
1429 opx->segment, opx->wrt);
1430 offset += 2;
1431 }
1432 break;
1433
1434 case4(0144):
1435 EMIT_REX();
1436 bytes[0] = *codes++;
1437 if (is_sbyte16(opx))
1438 bytes[0] |= 2; /* s-bit */
1439 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1440 offset++;
1441 break;
1442
1443 case4(0150):
1444 data = opx->offset;
1445 warn_overflow(4, opx);
1446 if (is_sbyte32(opx)) {
1447 bytes[0] = data;
1448 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1449 NO_SEG);
1450 offset++;
1451 } else {
1452 out(offset, segment, &data, OUT_ADDRESS, 4,
1453 opx->segment, opx->wrt);
1454 offset += 4;
1455 }
1456 break;
1457
1458 case4(0154):
1459 EMIT_REX();
1460 bytes[0] = *codes++;
1461 if (is_sbyte32(opx))
1462 bytes[0] |= 2; /* s-bit */
1463 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1464 offset++;
1465 break;
1466
1467 case4(0160):
1468 case4(0164):
1469 break;
1470
1471 case 0171:
1472 bytes[0] =
1473 (ins->drexdst << 4) |
1474 (ins->rex & REX_OC ? 0x08 : 0) |
1475 (ins->rex & (REX_R|REX_X|REX_B));
1476 ins->rex = 0;
1477 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1478 offset++;
1479 break;
1480
1481 case 0172:
1482 c = *codes++;
1483 opx = &ins->oprs[c >> 3];
1484 bytes[0] = nasm_regvals[opx->basereg] << 4;
1485 opx = &ins->oprs[c & 7];
1486 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1487 errfunc(ERR_NONFATAL,
1488 "non-absolute expression not permitted as argument %d",
1489 c & 7);
1490 } else {
1491 if (opx->offset & ~15) {
1492 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1493 "four-bit argument exceeds bounds");
1494 }
1495 bytes[0] |= opx->offset & 15;
1496 }
1497 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1498 offset++;
1499 break;
1500
1501 case 0173:
1502 c = *codes++;
1503 opx = &ins->oprs[c >> 4];
1504 bytes[0] = nasm_regvals[opx->basereg] << 4;
1505 bytes[0] |= c & 15;
1506 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1507 offset++;
1508 break;
1509
1510 case 0174:
1511 c = *codes++;
1512 opx = &ins->oprs[c];
1513 bytes[0] = nasm_regvals[opx->basereg] << 4;
1514 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1515 offset++;
1516 break;
1517
1518 case4(0250):
1519 data = opx->offset;
1520 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1521 (int32_t)data != (int64_t)data) {
1522 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1523 "signed dword immediate exceeds bounds");
1524 }
1525 if (is_sbyte32(opx)) {
1526 bytes[0] = data;
1527 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1528 NO_SEG);
1529 offset++;
1530 } else {
1531 out(offset, segment, &data, OUT_ADDRESS, 4,
1532 opx->segment, opx->wrt);
1533 offset += 4;
1534 }
1535 break;
1536
1537 case4(0254):
1538 data = opx->offset;
1539 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1540 (int32_t)data != (int64_t)data) {
1541 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1542 "signed dword immediate exceeds bounds");
1543 }
1544 out(offset, segment, &data, OUT_ADDRESS, 4,
1545 opx->segment, opx->wrt);
1546 offset += 4;
1547 break;
1548
1549 case4(0260):
1550 case 0270:
1551 codes += 2;
1552 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1553 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1554 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1555 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1556 ((~ins->drexdst & 15)<< 3) | (ins->vex_wlp & 07);
1557 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1558 offset += 3;
1559 } else {
1560 bytes[0] = 0xc5;
1561 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1562 ((~ins->drexdst & 15) << 3) | (ins->vex_wlp & 07);
1563 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1564 offset += 2;
1565 }
1566 break;
1567
1568 case4(0274):
1569 {
1570 uint64_t uv, um;
1571 int s;
1572
1573 if (ins->rex & REX_W)
1574 s = 64;
1575 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1576 s = 16;
1577 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1578 s = 32;
1579 else
1580 s = bits;
1581
1582 um = (uint64_t)2 << (s-1);
1583 uv = opx->offset;
1584
1585 if (uv > 127 && uv < (uint64_t)-128 &&
1586 (uv < um-128 || uv > um-1)) {
1587 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1588 "signed byte value exceeds bounds");
1589 }
1590 if (opx->segment != NO_SEG) {
1591 data = uv;
1592 out(offset, segment, &data, OUT_ADDRESS, 1,
1593 opx->segment, opx->wrt);
1594 } else {
1595 bytes[0] = uv;
1596 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1597 NO_SEG);
1598 }
1599 offset += 1;
1600 break;
1601 }
1602
1603 case4(0300):
1604 break;
1605
1606 case 0310:
1607 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1608 *bytes = 0x67;
1609 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1610 offset += 1;
1611 } else
1612 offset += 0;
1613 break;
1614
1615 case 0311:
1616 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1617 *bytes = 0x67;
1618 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1619 offset += 1;
1620 } else
1621 offset += 0;
1622 break;
1623
1624 case 0312:
1625 break;
1626
1627 case 0313:
1628 ins->rex = 0;
1629 break;
1630
1631 case4(0314):
1632 break;
1633
1634 case 0320:
1635 if (bits != 16) {
1636 *bytes = 0x66;
1637 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1638 offset += 1;
1639 } else
1640 offset += 0;
1641 break;
1642
1643 case 0321:
1644 if (bits == 16) {
1645 *bytes = 0x66;
1646 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1647 offset += 1;
1648 } else
1649 offset += 0;
1650 break;
1651
1652 case 0322:
1653 case 0323:
1654 break;
1655
1656 case 0324:
1657 ins->rex |= REX_W;
1658 break;
1659
1660 case 0325:
1661 break;
1662
1663 case 0330:
1664 *bytes = *codes++ ^ condval[ins->condition];
1665 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1666 offset += 1;
1667 break;
1668
1669 case 0331:
1670 break;
1671
1672 case 0332:
1673 case 0333:
1674 *bytes = c - 0332 + 0xF2;
1675 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1676 offset += 1;
1677 break;
1678
1679 case 0334:
1680 if (ins->rex & REX_R) {
1681 *bytes = 0xF0;
1682 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1683 offset += 1;
1684 }
1685 ins->rex &= ~(REX_L|REX_R);
1686 break;
1687
1688 case 0335:
1689 break;
1690
1691 case 0336:
1692 case 0337:
1693 break;
1694
1695 case 0340:
1696 if (ins->oprs[0].segment != NO_SEG)
1697 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1698 else {
1699 int64_t size = ins->oprs[0].offset;
1700 if (size > 0)
1701 out(offset, segment, NULL,
1702 OUT_RESERVE, size, NO_SEG, NO_SEG);
1703 offset += size;
1704 }
1705 break;
1706
1707 case 0341:
1708 break;
1709
1710 case 0344:
1711 case 0345:
1712 bytes[0] = c & 1;
1713 switch (ins->oprs[0].basereg) {
1714 case R_CS:
1715 bytes[0] += 0x0E;
1716 break;
1717 case R_DS:
1718 bytes[0] += 0x1E;
1719 break;
1720 case R_ES:
1721 bytes[0] += 0x06;
1722 break;
1723 case R_SS:
1724 bytes[0] += 0x16;
1725 break;
1726 default:
1727 errfunc(ERR_PANIC,
1728 "bizarre 8086 segment register received");
1729 }
1730 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1731 offset++;
1732 break;
1733
1734 case 0346:
1735 case 0347:
1736 bytes[0] = c & 1;
1737 switch (ins->oprs[0].basereg) {
1738 case R_FS:
1739 bytes[0] += 0xA0;
1740 break;
1741 case R_GS:
1742 bytes[0] += 0xA8;
1743 break;
1744 default:
1745 errfunc(ERR_PANIC,
1746 "bizarre 386 segment register received");
1747 }
1748 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1749 offset++;
1750 break;
1751
1752 case 0360:
1753 break;
1754
1755 case 0361:
1756 bytes[0] = 0x66;
1757 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1758 offset += 1;
1759 break;
1760
1761 case 0362:
1762 case 0363:
1763 bytes[0] = c - 0362 + 0xf2;
1764 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1765 offset += 1;
1766 break;
1767
1768 case 0364:
1769 case 0365:
1770 break;
1771
1772 case 0366:
1773 case 0367:
1774 *bytes = c - 0366 + 0x66;
1775 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1776 offset += 1;
1777 break;
1778
1779 case 0370:
1780 case 0371:
1781 case 0372:
1782 break;
1783
1784 case 0373:
1785 *bytes = bits == 16 ? 3 : 5;
1786 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1787 offset += 1;
1788 break;
1789
1790 case4(0100):
1791 case4(0110):
1792 case4(0120):
1793 case4(0130):
1794 case4(0200):
1795 case4(0204):
1796 case4(0210):
1797 case4(0214):
1798 case4(0220):
1799 case4(0224):
1800 case4(0230):
1801 case4(0234):
1802 {
1803 ea ea_data;
1804 int rfield;
1805 int32_t rflags;
1806 uint8_t *p;
1807 int32_t s;
1808 enum out_type type;
1809 struct operand *opy = &ins->oprs[op2];
1810
1811 if (c <= 0177) {
1812 /* pick rfield from operand b (opx) */
1813 rflags = regflag(opx);
1814 rfield = nasm_regvals[opx->basereg];
1815 } else {
1816 /* rfield is constant */
1817 rflags = 0;
1818 rfield = c & 7;
1819 }
1820
1821 if (!process_ea(opy, &ea_data, bits, ins->addr_size,
1822 rfield, rflags)) {
1823 errfunc(ERR_NONFATAL, "invalid effective address");
1824 }
1825
1826
1827 p = bytes;
1828 *p++ = ea_data.modrm;
1829 if (ea_data.sib_present)
1830 *p++ = ea_data.sib;
1831
1832 /* DREX suffixes come between the SIB and the displacement */
1833 if (ins->rex & REX_D) {
1834 *p++ = (ins->drexdst << 4) |
1835 (ins->rex & REX_OC ? 0x08 : 0) |
1836 (ins->rex & (REX_R|REX_X|REX_B));
1837 ins->rex = 0;
1838 }
1839
1840 s = p - bytes;
1841 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1842
1843 /*
1844 * Make sure the address gets the right offset in case
1845 * the line breaks in the .lst file (BR 1197827)
1846 */
1847 offset += s;
1848 s = 0;
1849
1850 switch (ea_data.bytes) {
1851 case 0:
1852 break;
1853 case 1:
1854 case 2:
1855 case 4:
1856 case 8:
1857 data = opy->offset;
1858 warn_overflow(ea_data.bytes, opy);
1859 s += ea_data.bytes;
1860 if (ea_data.rip) {
1861 if (opy->segment == segment) {
1862 data -= insn_end;
1863 out(offset, segment, &data, OUT_ADDRESS,
1864 ea_data.bytes, NO_SEG, NO_SEG);
1865 } else {
1866 out(offset, segment, &data, OUT_REL4ADR,
1867 insn_end - offset, opy->segment, opy->wrt);
1868 }
1869 } else {
1870 type = OUT_ADDRESS;
1871 out(offset, segment, &data, OUT_ADDRESS,
1872 ea_data.bytes, opy->segment, opy->wrt);
1873 }
1874 break;
1875 default:
1876 /* Impossible! */
1877 errfunc(ERR_PANIC,
1878 "Invalid amount of bytes (%d) for offset?!",
1879 ea_data.bytes);
1880 break;
1881 }
1882 offset += s;
1883 }
1884 break;
1885
1886 default:
1887 errfunc(ERR_PANIC, "internal instruction table corrupt"
1888 ": instruction code \\%o (0x%02X) given", c, c);
1889 break;
1890 }
1891 }
1892 }
1893
1894 static int32_t regflag(const operand * o)
1895 {
1896 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1897 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1898 }
1899 return nasm_reg_flags[o->basereg];
1900 }
1901
1902 static int32_t regval(const operand * o)
1903 {
1904 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1905 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1906 }
1907 return nasm_regvals[o->basereg];
1908 }
1909
1910 static int op_rexflags(const operand * o, int mask)
1911 {
1912 int32_t flags;
1913 int val;
1914
1915 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1916 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1917 }
1918
1919 flags = nasm_reg_flags[o->basereg];
1920 val = nasm_regvals[o->basereg];
1921
1922 return rexflags(val, flags, mask);
1923 }
1924
1925 static int rexflags(int val, int32_t flags, int mask)
1926 {
1927 int rex = 0;
1928
1929 if (val >= 8)
1930 rex |= REX_B|REX_X|REX_R;
1931 if (flags & BITS64)
1932 rex |= REX_W;
1933 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1934 rex |= REX_H;
1935 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1936 rex |= REX_P;
1937
1938 return rex & mask;
1939 }
1940
1941 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1942 {
1943 int i, size[MAX_OPERANDS], asize, oprs, ret;
1944
1945 ret = 100;
1946
1947 /*
1948 * Check the opcode
1949 */
1950 if (itemp->opcode != instruction->opcode)
1951 return 0;
1952
1953 /*
1954 * Count the operands
1955 */
1956 if (itemp->operands != instruction->operands)
1957 return 0;
1958
1959 /*
1960 * Check that no spurious colons or TOs are present
1961 */
1962 for (i = 0; i < itemp->operands; i++)
1963 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1964 return 0;
1965
1966 /*
1967 * Process size flags
1968 */
1969 if (itemp->flags & IF_ARMASK) {
1970 memset(size, 0, sizeof size);
1971
1972 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1973
1974 switch (itemp->flags & IF_SMASK) {
1975 case IF_SB:
1976 size[i] = BITS8;
1977 break;
1978 case IF_SW:
1979 size[i] = BITS16;
1980 break;
1981 case IF_SD:
1982 size[i] = BITS32;
1983 break;
1984 case IF_SQ:
1985 size[i] = BITS64;
1986 break;
1987 case IF_SO:
1988 size[i] = BITS128;
1989 break;
1990 case IF_SY:
1991 size[i] = BITS256;
1992 break;
1993 case IF_SZ:
1994 switch (bits) {
1995 case 16:
1996 size[i] = BITS16;
1997 break;
1998 case 32:
1999 size[i] = BITS32;
2000 break;
2001 case 64:
2002 size[i] = BITS64;
2003 break;
2004 }
2005 break;
2006 default:
2007 break;
2008 }
2009 } else {
2010 asize = 0;
2011 switch (itemp->flags & IF_SMASK) {
2012 case IF_SB:
2013 asize = BITS8;
2014 break;
2015 case IF_SW:
2016 asize = BITS16;
2017 break;
2018 case IF_SD:
2019 asize = BITS32;
2020 break;
2021 case IF_SQ:
2022 asize = BITS64;
2023 break;
2024 case IF_SO:
2025 asize = BITS128;
2026 break;
2027 case IF_SY:
2028 asize = BITS256;
2029 break;
2030 case IF_SZ:
2031 switch (bits) {
2032 case 16:
2033 asize = BITS16;
2034 break;
2035 case 32:
2036 asize = BITS32;
2037 break;
2038 case 64:
2039 asize = BITS64;
2040 break;
2041 }
2042 break;
2043 default:
2044 break;
2045 }
2046 for (i = 0; i < MAX_OPERANDS; i++)
2047 size[i] = asize;
2048 }
2049
2050 /*
2051 * Check that the operand flags all match up
2052 */
2053 for (i = 0; i < itemp->operands; i++) {
2054 int32_t type = instruction->oprs[i].type;
2055 if (!(type & SIZE_MASK))
2056 type |= size[i];
2057
2058 if (itemp->opd[i] & SAME_AS) {
2059 int j = itemp->opd[i] & ~SAME_AS;
2060 if (type != instruction->oprs[j].type ||
2061 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2062 return 0;
2063 } else if (itemp->opd[i] & ~type ||
2064 ((itemp->opd[i] & SIZE_MASK) &&
2065 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2066 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2067 (type & SIZE_MASK))
2068 return 0;
2069 else
2070 return 1;
2071 }
2072 }
2073
2074 /*
2075 * Check operand sizes
2076 */
2077 if (itemp->flags & (IF_SM | IF_SM2)) {
2078 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2079 asize = 0;
2080 for (i = 0; i < oprs; i++) {
2081 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
2082 int j;
2083 for (j = 0; j < oprs; j++)
2084 size[j] = asize;
2085 break;
2086 }
2087 }
2088 } else {
2089 oprs = itemp->operands;
2090 }
2091
2092 for (i = 0; i < itemp->operands; i++) {
2093 if (!(itemp->opd[i] & SIZE_MASK) &&
2094 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2095 return 2;
2096 }
2097
2098 /*
2099 * Check template is okay at the set cpu level
2100 */
2101 if (((itemp->flags & IF_PLEVEL) > cpu))
2102 return 3;
2103
2104 /*
2105 * Verify the appropriate long mode flag.
2106 */
2107 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2108 return 4;
2109
2110 /*
2111 * Check if special handling needed for Jumps
2112 */
2113 if ((uint8_t)(itemp->code[0]) >= 0370)
2114 return 99;
2115
2116 return ret;
2117 }
2118
2119 static ea *process_ea(operand * input, ea * output, int bits,
2120 int addrbits, int rfield, int32_t rflags)
2121 {
2122 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2123
2124 output->rip = false;
2125
2126 /* REX flags for the rfield operand */
2127 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
2128
2129 if (!(REGISTER & ~input->type)) { /* register direct */
2130 int i;
2131 int32_t f;
2132
2133 if (input->basereg < EXPR_REG_START /* Verify as Register */
2134 || input->basereg >= REG_ENUM_LIMIT)
2135 return NULL;
2136 f = regflag(input);
2137 i = nasm_regvals[input->basereg];
2138
2139 if (REG_EA & ~f)
2140 return NULL; /* Invalid EA register */
2141
2142 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
2143
2144 output->sib_present = false; /* no SIB necessary */
2145 output->bytes = 0; /* no offset necessary either */
2146 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2147 } else { /* it's a memory reference */
2148 if (input->basereg == -1
2149 && (input->indexreg == -1 || input->scale == 0)) {
2150 /* it's a pure offset */
2151 if (bits == 64 && (~input->type & IP_REL)) {
2152 int scale, index, base;
2153 output->sib_present = true;
2154 scale = 0;
2155 index = 4;
2156 base = 5;
2157 output->sib = (scale << 6) | (index << 3) | base;
2158 output->bytes = 4;
2159 output->modrm = 4 | ((rfield & 7) << 3);
2160 output->rip = false;
2161 } else {
2162 output->sib_present = false;
2163 output->bytes = (addrbits != 16 ? 4 : 2);
2164 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2165 output->rip = bits == 64;
2166 }
2167 } else { /* it's an indirection */
2168 int i = input->indexreg, b = input->basereg, s = input->scale;
2169 int32_t o = input->offset, seg = input->segment;
2170 int hb = input->hintbase, ht = input->hinttype;
2171 int t;
2172 int it, bt;
2173 int32_t ix, bx; /* register flags */
2174
2175 if (s == 0)
2176 i = -1; /* make this easy, at least */
2177
2178 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
2179 it = nasm_regvals[i];
2180 ix = nasm_reg_flags[i];
2181 } else {
2182 it = -1;
2183 ix = 0;
2184 }
2185
2186 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
2187 bt = nasm_regvals[b];
2188 bx = nasm_reg_flags[b];
2189 } else {
2190 bt = -1;
2191 bx = 0;
2192 }
2193
2194 /* check for a 32/64-bit memory reference... */
2195 if ((ix|bx) & (BITS32|BITS64)) {
2196 /* it must be a 32/64-bit memory reference. Firstly we have
2197 * to check that all registers involved are type E/Rxx. */
2198 int32_t sok = BITS32|BITS64;
2199
2200 if (it != -1) {
2201 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2202 sok &= ix;
2203 else
2204 return NULL;
2205 }
2206
2207 if (bt != -1) {
2208 if (REG_GPR & ~bx)
2209 return NULL; /* Invalid register */
2210 if (~sok & bx & SIZE_MASK)
2211 return NULL; /* Invalid size */
2212 sok &= bx;
2213 }
2214
2215 /* While we're here, ensure the user didn't specify
2216 WORD or QWORD. */
2217 if (input->disp_size == 16 || input->disp_size == 64)
2218 return NULL;
2219
2220 if (addrbits == 16 ||
2221 (addrbits == 32 && !(sok & BITS32)) ||
2222 (addrbits == 64 && !(sok & BITS64)))
2223 return NULL;
2224
2225 /* now reorganize base/index */
2226 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2227 ((hb == b && ht == EAH_NOTBASE)
2228 || (hb == i && ht == EAH_MAKEBASE))) {
2229 /* swap if hints say so */
2230 t = bt, bt = it, it = t;
2231 t = bx, bx = ix, ix = t;
2232 }
2233 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2234 bt = -1, bx = 0, s++;
2235 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2236 /* make single reg base, unless hint */
2237 bt = it, bx = ix, it = -1, ix = 0;
2238 }
2239 if (((s == 2 && it != REG_NUM_ESP
2240 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
2241 || s == 5 || s == 9) && bt == -1)
2242 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2243 if (it == -1 && (bt & 7) != REG_NUM_ESP
2244 && (input->eaflags & EAF_TIMESTWO))
2245 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2246 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2247 if (s == 1 && it == REG_NUM_ESP) {
2248 /* swap ESP into base if scale is 1 */
2249 t = it, it = bt, bt = t;
2250 t = ix, ix = bx, bx = t;
2251 }
2252 if (it == REG_NUM_ESP
2253 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2254 return NULL; /* wrong, for various reasons */
2255
2256 output->rex |= rexflags(it, ix, REX_X);
2257 output->rex |= rexflags(bt, bx, REX_B);
2258
2259 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2260 /* no SIB needed */
2261 int mod, rm;
2262
2263 if (bt == -1) {
2264 rm = 5;
2265 mod = 0;
2266 } else {
2267 rm = (bt & 7);
2268 if (rm != REG_NUM_EBP && o == 0 &&
2269 seg == NO_SEG && !forw_ref &&
2270 !(input->eaflags &
2271 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2272 mod = 0;
2273 else if (input->eaflags & EAF_BYTEOFFS ||
2274 (o >= -128 && o <= 127 && seg == NO_SEG
2275 && !forw_ref
2276 && !(input->eaflags & EAF_WORDOFFS)))
2277 mod = 1;
2278 else
2279 mod = 2;
2280 }
2281
2282 output->sib_present = false;
2283 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2284 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2285 } else {
2286 /* we need a SIB */
2287 int mod, scale, index, base;
2288
2289 if (it == -1)
2290 index = 4, s = 1;
2291 else
2292 index = (it & 7);
2293
2294 switch (s) {
2295 case 1:
2296 scale = 0;
2297 break;
2298 case 2:
2299 scale = 1;
2300 break;
2301 case 4:
2302 scale = 2;
2303 break;
2304 case 8:
2305 scale = 3;
2306 break;
2307 default: /* then what the smeg is it? */
2308 return NULL; /* panic */
2309 }
2310
2311 if (bt == -1) {
2312 base = 5;
2313 mod = 0;
2314 } else {
2315 base = (bt & 7);
2316 if (base != REG_NUM_EBP && o == 0 &&
2317 seg == NO_SEG && !forw_ref &&
2318 !(input->eaflags &
2319 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2320 mod = 0;
2321 else if (input->eaflags & EAF_BYTEOFFS ||
2322 (o >= -128 && o <= 127 && seg == NO_SEG
2323 && !forw_ref
2324 && !(input->eaflags & EAF_WORDOFFS)))
2325 mod = 1;
2326 else
2327 mod = 2;
2328 }
2329
2330 output->sib_present = true;
2331 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2332 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2333 output->sib = (scale << 6) | (index << 3) | base;
2334 }
2335 } else { /* it's 16-bit */
2336 int mod, rm;
2337
2338 /* check for 64-bit long mode */
2339 if (addrbits == 64)
2340 return NULL;
2341
2342 /* check all registers are BX, BP, SI or DI */
2343 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2344 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2345 && i != R_SI && i != R_DI))
2346 return NULL;
2347
2348 /* ensure the user didn't specify DWORD/QWORD */
2349 if (input->disp_size == 32 || input->disp_size == 64)
2350 return NULL;
2351
2352 if (s != 1 && i != -1)
2353 return NULL; /* no can do, in 16-bit EA */
2354 if (b == -1 && i != -1) {
2355 int tmp = b;
2356 b = i;
2357 i = tmp;
2358 } /* swap */
2359 if ((b == R_SI || b == R_DI) && i != -1) {
2360 int tmp = b;
2361 b = i;
2362 i = tmp;
2363 }
2364 /* have BX/BP as base, SI/DI index */
2365 if (b == i)
2366 return NULL; /* shouldn't ever happen, in theory */
2367 if (i != -1 && b != -1 &&
2368 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2369 return NULL; /* invalid combinations */
2370 if (b == -1) /* pure offset: handled above */
2371 return NULL; /* so if it gets to here, panic! */
2372
2373 rm = -1;
2374 if (i != -1)
2375 switch (i * 256 + b) {
2376 case R_SI * 256 + R_BX:
2377 rm = 0;
2378 break;
2379 case R_DI * 256 + R_BX:
2380 rm = 1;
2381 break;
2382 case R_SI * 256 + R_BP:
2383 rm = 2;
2384 break;
2385 case R_DI * 256 + R_BP:
2386 rm = 3;
2387 break;
2388 } else
2389 switch (b) {
2390 case R_SI:
2391 rm = 4;
2392 break;
2393 case R_DI:
2394 rm = 5;
2395 break;
2396 case R_BP:
2397 rm = 6;
2398 break;
2399 case R_BX:
2400 rm = 7;
2401 break;
2402 }
2403 if (rm == -1) /* can't happen, in theory */
2404 return NULL; /* so panic if it does */
2405
2406 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2407 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2408 mod = 0;
2409 else if (input->eaflags & EAF_BYTEOFFS ||
2410 (o >= -128 && o <= 127 && seg == NO_SEG
2411 && !forw_ref
2412 && !(input->eaflags & EAF_WORDOFFS)))
2413 mod = 1;
2414 else
2415 mod = 2;
2416
2417 output->sib_present = false; /* no SIB - it's 16-bit */
2418 output->bytes = mod; /* bytes of offset needed */
2419 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2420 }
2421 }
2422 }
2423
2424 output->size = 1 + output->sib_present + output->bytes;
2425 return output;
2426 }
2427
2428 static void add_asp(insn *ins, int addrbits)
2429 {
2430 int j, valid;
2431 int defdisp;
2432
2433 valid = (addrbits == 64) ? 64|32 : 32|16;
2434
2435 switch (ins->prefixes[PPS_ASIZE]) {
2436 case P_A16:
2437 valid &= 16;
2438 break;
2439 case P_A32:
2440 valid &= 32;
2441 break;
2442 case P_A64:
2443 valid &= 64;
2444 break;
2445 case P_ASP:
2446 valid &= (addrbits == 32) ? 16 : 32;
2447 break;
2448 default:
2449 break;
2450 }
2451
2452 for (j = 0; j < ins->operands; j++) {
2453 if (!(MEMORY & ~ins->oprs[j].type)) {
2454 int32_t i, b;
2455
2456 /* Verify as Register */
2457 if (ins->oprs[j].indexreg < EXPR_REG_START
2458 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2459 i = 0;
2460 else
2461 i = nasm_reg_flags[ins->oprs[j].indexreg];
2462
2463 /* Verify as Register */
2464 if (ins->oprs[j].basereg < EXPR_REG_START
2465 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2466 b = 0;
2467 else
2468 b = nasm_reg_flags[ins->oprs[j].basereg];
2469
2470 if (ins->oprs[j].scale == 0)
2471 i = 0;
2472
2473 if (!i && !b) {
2474 int ds = ins->oprs[j].disp_size;
2475 if ((addrbits != 64 && ds > 8) ||
2476 (addrbits == 64 && ds == 16))
2477 valid &= ds;
2478 } else {
2479 if (!(REG16 & ~b))
2480 valid &= 16;
2481 if (!(REG32 & ~b))
2482 valid &= 32;
2483 if (!(REG64 & ~b))
2484 valid &= 64;
2485
2486 if (!(REG16 & ~i))
2487 valid &= 16;
2488 if (!(REG32 & ~i))
2489 valid &= 32;
2490 if (!(REG64 & ~i))
2491 valid &= 64;
2492 }
2493 }
2494 }
2495
2496 if (valid & addrbits) {
2497 ins->addr_size = addrbits;
2498 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2499 /* Add an address size prefix */
2500 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2501 ins->prefixes[PPS_ASIZE] = pref;
2502 ins->addr_size = (addrbits == 32) ? 16 : 32;
2503 } else {
2504 /* Impossible... */
2505 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2506 ins->addr_size = addrbits; /* Error recovery */
2507 }
2508
2509 defdisp = ins->addr_size == 16 ? 16 : 32;
2510
2511 for (j = 0; j < ins->operands; j++) {
2512 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2513 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2514 != ins->addr_size) {
2515 /* mem_offs sizes must match the address size; if not,
2516 strip the MEM_OFFS bit and match only EA instructions */
2517 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2518 }
2519 }
2520 }
The Netwide Assembler