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ndisasm: fix handing of byte codes 250-253, 324
[nasm.git] / disasm.c
blobf2ec76bf25ae0d1d6756c146d55cbccad8fb0262
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2010 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43 #include <inttypes.h>
44
45 #include "nasm.h"
46 #include "disasm.h"
47 #include "sync.h"
48 #include "insns.h"
49 #include "tables.h"
50 #include "regdis.h"
51
52 /*
53 * Flags that go into the `segment' field of `insn' structures
54 * during disassembly.
55 */
56 #define SEG_RELATIVE 1
57 #define SEG_32BIT 2
58 #define SEG_RMREG 4
59 #define SEG_DISP8 8
60 #define SEG_DISP16 16
61 #define SEG_DISP32 32
62 #define SEG_NODISP 64
63 #define SEG_SIGNED 128
64 #define SEG_64BIT 256
65
66 /*
67 * Prefix information
68 */
69 struct prefix_info {
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
81 uint8_t vex_v;
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
84 };
85
86 #define getu8(x) (*(uint8_t *)(x))
87 #if X86_MEMORY
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
92 #else
93 static uint16_t getu16(uint8_t *data)
94 {
95 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
96 }
97 static uint32_t getu32(uint8_t *data)
98 {
99 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
100 }
101 static uint64_t getu64(uint8_t *data)
102 {
103 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
104 }
105 #endif
106
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
111
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
114 {
115 if (!(regflags & (REGISTER|REGMEM)))
116 return 0; /* Registers not permissible?! */
117
118 regflags |= REGISTER;
119
120 if (!(REG_AL & ~regflags))
121 return R_AL;
122 if (!(REG_AX & ~regflags))
123 return R_AX;
124 if (!(REG_EAX & ~regflags))
125 return R_EAX;
126 if (!(REG_RAX & ~regflags))
127 return R_RAX;
128 if (!(REG_DL & ~regflags))
129 return R_DL;
130 if (!(REG_DX & ~regflags))
131 return R_DX;
132 if (!(REG_EDX & ~regflags))
133 return R_EDX;
134 if (!(REG_RDX & ~regflags))
135 return R_RDX;
136 if (!(REG_CL & ~regflags))
137 return R_CL;
138 if (!(REG_CX & ~regflags))
139 return R_CX;
140 if (!(REG_ECX & ~regflags))
141 return R_ECX;
142 if (!(REG_RCX & ~regflags))
143 return R_RCX;
144 if (!(FPU0 & ~regflags))
145 return R_ST0;
146 if (!(XMM0 & ~regflags))
147 return R_XMM0;
148 if (!(YMM0 & ~regflags))
149 return R_YMM0;
150 if (!(REG_CS & ~regflags))
151 return (regval == 1) ? R_CS : 0;
152 if (!(REG_DESS & ~regflags))
153 return (regval == 0 || regval == 2
154 || regval == 3 ? nasm_rd_sreg[regval] : 0);
155 if (!(REG_FSGS & ~regflags))
156 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
157 if (!(REG_SEG67 & ~regflags))
158 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
159
160 /* All the entries below look up regval in an 16-entry array */
161 if (regval < 0 || regval > 15)
162 return 0;
163
164 if (!(REG8 & ~regflags)) {
165 if (rex & (REX_P|REX_NH))
166 return nasm_rd_reg8_rex[regval];
167 else
168 return nasm_rd_reg8[regval];
169 }
170 if (!(REG16 & ~regflags))
171 return nasm_rd_reg16[regval];
172 if (!(REG32 & ~regflags))
173 return nasm_rd_reg32[regval];
174 if (!(REG64 & ~regflags))
175 return nasm_rd_reg64[regval];
176 if (!(REG_SREG & ~regflags))
177 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
178 if (!(REG_CREG & ~regflags))
179 return nasm_rd_creg[regval];
180 if (!(REG_DREG & ~regflags))
181 return nasm_rd_dreg[regval];
182 if (!(REG_TREG & ~regflags)) {
183 if (regval > 7)
184 return 0; /* TR registers are ill-defined with rex */
185 return nasm_rd_treg[regval];
186 }
187 if (!(FPUREG & ~regflags))
188 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
189 if (!(MMXREG & ~regflags))
190 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
191 if (!(XMMREG & ~regflags))
192 return nasm_rd_xmmreg[regval];
193 if (!(YMMREG & ~regflags))
194 return nasm_rd_ymmreg[regval];
195
196 return 0;
197 }
198
199 /*
200 * Process a DREX suffix
201 */
202 static uint8_t *do_drex(uint8_t *data, insn *ins)
203 {
204 uint8_t drex = *data++;
205 operand *dst = &ins->oprs[ins->drexdst];
206
207 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
208 return NULL; /* OC0 mismatch */
209 ins->rex = (ins->rex & ~7) | (drex & 7);
210
211 dst->segment = SEG_RMREG;
212 dst->basereg = drex >> 4;
213 return data;
214 }
215
216
217 /*
218 * Process an effective address (ModRM) specification.
219 */
220 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
221 int segsize, operand * op, insn *ins)
222 {
223 int mod, rm, scale, index, base;
224 int rex;
225 uint8_t sib = 0;
226
227 mod = (modrm >> 6) & 03;
228 rm = modrm & 07;
229
230 if (mod != 3 && rm == 4 && asize != 16)
231 sib = *data++;
232
233 if (ins->rex & REX_D) {
234 data = do_drex(data, ins);
235 if (!data)
236 return NULL;
237 }
238 rex = ins->rex;
239
240 if (mod == 3) { /* pure register version */
241 op->basereg = rm+(rex & REX_B ? 8 : 0);
242 op->segment |= SEG_RMREG;
243 return data;
244 }
245
246 op->disp_size = 0;
247 op->eaflags = 0;
248
249 if (asize == 16) {
250 /*
251 * <mod> specifies the displacement size (none, byte or
252 * word), and <rm> specifies the register combination.
253 * Exception: mod=0,rm=6 does not specify [BP] as one might
254 * expect, but instead specifies [disp16].
255 */
256 op->indexreg = op->basereg = -1;
257 op->scale = 1; /* always, in 16 bits */
258 switch (rm) {
259 case 0:
260 op->basereg = R_BX;
261 op->indexreg = R_SI;
262 break;
263 case 1:
264 op->basereg = R_BX;
265 op->indexreg = R_DI;
266 break;
267 case 2:
268 op->basereg = R_BP;
269 op->indexreg = R_SI;
270 break;
271 case 3:
272 op->basereg = R_BP;
273 op->indexreg = R_DI;
274 break;
275 case 4:
276 op->basereg = R_SI;
277 break;
278 case 5:
279 op->basereg = R_DI;
280 break;
281 case 6:
282 op->basereg = R_BP;
283 break;
284 case 7:
285 op->basereg = R_BX;
286 break;
287 }
288 if (rm == 6 && mod == 0) { /* special case */
289 op->basereg = -1;
290 if (segsize != 16)
291 op->disp_size = 16;
292 mod = 2; /* fake disp16 */
293 }
294 switch (mod) {
295 case 0:
296 op->segment |= SEG_NODISP;
297 break;
298 case 1:
299 op->segment |= SEG_DISP8;
300 op->offset = (int8_t)*data++;
301 break;
302 case 2:
303 op->segment |= SEG_DISP16;
304 op->offset = *data++;
305 op->offset |= ((unsigned)*data++) << 8;
306 break;
307 }
308 return data;
309 } else {
310 /*
311 * Once again, <mod> specifies displacement size (this time
312 * none, byte or *dword*), while <rm> specifies the base
313 * register. Again, [EBP] is missing, replaced by a pure
314 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
315 * and RIP-relative addressing in 64-bit mode.
316 *
317 * However, rm=4
318 * indicates not a single base register, but instead the
319 * presence of a SIB byte...
320 */
321 int a64 = asize == 64;
322
323 op->indexreg = -1;
324
325 if (a64)
326 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
327 else
328 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
329
330 if (rm == 5 && mod == 0) {
331 if (segsize == 64) {
332 op->eaflags |= EAF_REL;
333 op->segment |= SEG_RELATIVE;
334 mod = 2; /* fake disp32 */
335 }
336
337 if (asize != 64)
338 op->disp_size = asize;
339
340 op->basereg = -1;
341 mod = 2; /* fake disp32 */
342 }
343
344 if (rm == 4) { /* process SIB */
345 scale = (sib >> 6) & 03;
346 index = (sib >> 3) & 07;
347 base = sib & 07;
348
349 op->scale = 1 << scale;
350
351 if (index == 4 && !(rex & REX_X))
352 op->indexreg = -1; /* ESP/RSP cannot be an index */
353 else if (a64)
354 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
355 else
356 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
357
358 if (base == 5 && mod == 0) {
359 op->basereg = -1;
360 mod = 2; /* Fake disp32 */
361 } else if (a64)
362 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
363 else
364 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
365
366 if (segsize == 16)
367 op->disp_size = 32;
368 }
369
370 switch (mod) {
371 case 0:
372 op->segment |= SEG_NODISP;
373 break;
374 case 1:
375 op->segment |= SEG_DISP8;
376 op->offset = gets8(data);
377 data++;
378 break;
379 case 2:
380 op->segment |= SEG_DISP32;
381 op->offset = gets32(data);
382 data += 4;
383 break;
384 }
385 return data;
386 }
387 }
388
389 /*
390 * Determine whether the instruction template in t corresponds to the data
391 * stream in data. Return the number of bytes matched if so.
392 */
393 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
394
395 static int matches(const struct itemplate *t, uint8_t *data,
396 const struct prefix_info *prefix, int segsize, insn *ins)
397 {
398 uint8_t *r = (uint8_t *)(t->code);
399 uint8_t *origdata = data;
400 bool a_used = false, o_used = false;
401 enum prefixes drep = 0;
402 enum prefixes dwait = 0;
403 uint8_t lock = prefix->lock;
404 int osize = prefix->osize;
405 int asize = prefix->asize;
406 int i, c;
407 int op1, op2;
408 struct operand *opx, *opy;
409 uint8_t opex = 0;
410 int s_field_for = -1; /* No 144/154 series code encountered */
411 bool vex_ok = false;
412 int regmask = (segsize == 64) ? 15 : 7;
413
414 for (i = 0; i < MAX_OPERANDS; i++) {
415 ins->oprs[i].segment = ins->oprs[i].disp_size =
416 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
417 }
418 ins->condition = -1;
419 ins->rex = prefix->rex;
420 memset(ins->prefixes, 0, sizeof ins->prefixes);
421
422 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
423 return false;
424
425 if (prefix->rep == 0xF2)
426 drep = P_REPNE;
427 else if (prefix->rep == 0xF3)
428 drep = P_REP;
429
430 dwait = prefix->wait ? P_WAIT : 0;
431
432 while ((c = *r++) != 0) {
433 op1 = (c & 3) + ((opex & 1) << 2);
434 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
435 opx = &ins->oprs[op1];
436 opy = &ins->oprs[op2];
437 opex = 0;
438
439 switch (c) {
440 case 01:
441 case 02:
442 case 03:
443 case 04:
444 while (c--)
445 if (*r++ != *data++)
446 return false;
447 break;
448
449 case 05:
450 case 06:
451 case 07:
452 opex = c;
453 break;
454
455 case4(010):
456 {
457 int t = *r++, d = *data++;
458 if (d < t || d > t + 7)
459 return false;
460 else {
461 opx->basereg = (d-t)+
462 (ins->rex & REX_B ? 8 : 0);
463 opx->segment |= SEG_RMREG;
464 }
465 break;
466 }
467
468 case4(014):
469 case4(0274):
470 opx->offset = (int8_t)*data++;
471 opx->segment |= SEG_SIGNED;
472 break;
473
474 case4(020):
475 opx->offset = *data++;
476 break;
477
478 case4(024):
479 opx->offset = *data++;
480 break;
481
482 case4(030):
483 opx->offset = getu16(data);
484 data += 2;
485 break;
486
487 case4(034):
488 if (osize == 32) {
489 opx->offset = getu32(data);
490 data += 4;
491 } else {
492 opx->offset = getu16(data);
493 data += 2;
494 }
495 if (segsize != asize)
496 opx->disp_size = asize;
497 break;
498
499 case4(040):
500 case4(0254):
501 opx->offset = getu32(data);
502 data += 4;
503 break;
504
505 case4(044):
506 switch (asize) {
507 case 16:
508 opx->offset = getu16(data);
509 data += 2;
510 if (segsize != 16)
511 opx->disp_size = 16;
512 break;
513 case 32:
514 opx->offset = getu32(data);
515 data += 4;
516 if (segsize == 16)
517 opx->disp_size = 32;
518 break;
519 case 64:
520 opx->offset = getu64(data);
521 opx->disp_size = 64;
522 data += 8;
523 break;
524 }
525 break;
526
527 case4(050):
528 opx->offset = gets8(data++);
529 opx->segment |= SEG_RELATIVE;
530 break;
531
532 case4(054):
533 opx->offset = getu64(data);
534 data += 8;
535 break;
536
537 case4(060):
538 opx->offset = gets16(data);
539 data += 2;
540 opx->segment |= SEG_RELATIVE;
541 opx->segment &= ~SEG_32BIT;
542 break;
543
544 case4(064):
545 opx->segment |= SEG_RELATIVE;
546 if (osize == 16) {
547 opx->offset = gets16(data);
548 data += 2;
549 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
550 } else if (osize == 32) {
551 opx->offset = gets32(data);
552 data += 4;
553 opx->segment &= ~SEG_64BIT;
554 opx->segment |= SEG_32BIT;
555 }
556 if (segsize != osize) {
557 opx->type =
558 (opx->type & ~SIZE_MASK)
559 | ((osize == 16) ? BITS16 : BITS32);
560 }
561 break;
562
563 case4(070):
564 opx->offset = gets32(data);
565 data += 4;
566 opx->segment |= SEG_32BIT | SEG_RELATIVE;
567 break;
568
569 case4(0100):
570 case4(0110):
571 case4(0120):
572 case4(0130):
573 {
574 int modrm = *data++;
575 opx->segment |= SEG_RMREG;
576 data = do_ea(data, modrm, asize, segsize, opy, ins);
577 if (!data)
578 return false;
579 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
580 break;
581 }
582
583 case4(0140):
584 if (s_field_for == op1) {
585 opx->offset = gets8(data);
586 data++;
587 } else {
588 opx->offset = getu16(data);
589 data += 2;
590 }
591 break;
592
593 case4(0144):
594 case4(0154):
595 s_field_for = (*data & 0x02) ? op1 : -1;
596 if ((*data++ & ~0x02) != *r++)
597 return false;
598 break;
599
600 case4(0150):
601 if (s_field_for == op1) {
602 opx->offset = gets8(data);
603 data++;
604 } else {
605 opx->offset = getu32(data);
606 data += 4;
607 }
608 break;
609
610 case4(0160):
611 ins->rex |= REX_D;
612 ins->drexdst = op1;
613 break;
614
615 case4(0164):
616 ins->rex |= REX_D|REX_OC;
617 ins->drexdst = op1;
618 break;
619
620 case 0171:
621 data = do_drex(data, ins);
622 if (!data)
623 return false;
624 break;
625
626 case 0172:
627 {
628 uint8_t ximm = *data++;
629 c = *r++;
630 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
631 ins->oprs[c >> 3].segment |= SEG_RMREG;
632 ins->oprs[c & 7].offset = ximm & 15;
633 }
634 break;
635
636 case 0173:
637 {
638 uint8_t ximm = *data++;
639 c = *r++;
640
641 if ((c ^ ximm) & 15)
642 return false;
643
644 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
645 ins->oprs[c >> 4].segment |= SEG_RMREG;
646 }
647 break;
648
649 case 0174:
650 {
651 uint8_t ximm = *data++;
652 c = *r++;
653
654 ins->oprs[c].basereg = (ximm >> 4) & regmask;
655 ins->oprs[c].segment |= SEG_RMREG;
656 }
657 break;
658
659 case4(0200):
660 case4(0204):
661 case4(0210):
662 case4(0214):
663 case4(0220):
664 case4(0224):
665 case4(0230):
666 case4(0234):
667 {
668 int modrm = *data++;
669 if (((modrm >> 3) & 07) != (c & 07))
670 return false; /* spare field doesn't match up */
671 data = do_ea(data, modrm, asize, segsize, opy, ins);
672 if (!data)
673 return false;
674 break;
675 }
676
677 case4(0250):
678 if (s_field_for == op1) {
679 opx->offset = gets8(data);
680 data++;
681 } else {
682 opx->offset = gets32(data);
683 data += 4;
684 }
685 break;
686
687 case4(0260):
688 {
689 int vexm = *r++;
690 int vexwlp = *r++;
691
692 ins->rex |= REX_V;
693 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
694 return false;
695
696 if ((vexm & 0x1f) != prefix->vex_m)
697 return false;
698
699 switch (vexwlp & 060) {
700 case 000:
701 if (prefix->rex & REX_W)
702 return false;
703 break;
704 case 020:
705 if (!(prefix->rex & REX_W))
706 return false;
707 ins->rex &= ~REX_W;
708 break;
709 case 040: /* VEX.W is a don't care */
710 ins->rex &= ~REX_W;
711 break;
712 case 060:
713 break;
714 }
715
716 /* The 010 bit of vexwlp is set if VEX.L is ignored */
717 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
718 return false;
719
720 opx->segment |= SEG_RMREG;
721 opx->basereg = prefix->vex_v;
722 vex_ok = true;
723 break;
724 }
725
726 case 0270:
727 {
728 int vexm = *r++;
729 int vexwlp = *r++;
730 ins->rex |= REX_V;
731 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
732 return false;
733
734 if ((vexm & 0x1f) != prefix->vex_m)
735 return false;
736
737 switch (vexwlp & 030) {
738 case 000:
739 if (ins->rex & REX_W)
740 return false;
741 break;
742 case 010:
743 if (!(ins->rex & REX_W))
744 return false;
745 break;
746 default:
747 break; /* Need to do anything special here? */
748 }
749
750 if ((vexwlp & 007) != prefix->vex_lp)
751 return false;
752
753 if (prefix->vex_v != 0)
754 return false;
755
756 vex_ok = true;
757 break;
758 }
759
760 case 0310:
761 if (asize != 16)
762 return false;
763 else
764 a_used = true;
765 break;
766
767 case 0311:
768 if (asize != 32)
769 return false;
770 else
771 a_used = true;
772 break;
773
774 case 0312:
775 if (asize != segsize)
776 return false;
777 else
778 a_used = true;
779 break;
780
781 case 0313:
782 if (asize != 64)
783 return false;
784 else
785 a_used = true;
786 break;
787
788 case 0314:
789 if (prefix->rex & REX_B)
790 return false;
791 break;
792
793 case 0315:
794 if (prefix->rex & REX_X)
795 return false;
796 break;
797
798 case 0316:
799 if (prefix->rex & REX_R)
800 return false;
801 break;
802
803 case 0317:
804 if (prefix->rex & REX_W)
805 return false;
806 break;
807
808 case 0320:
809 if (osize != 16)
810 return false;
811 else
812 o_used = true;
813 break;
814
815 case 0321:
816 if (osize != 32)
817 return false;
818 else
819 o_used = true;
820 break;
821
822 case 0322:
823 if (osize != (segsize == 16) ? 16 : 32)
824 return false;
825 else
826 o_used = true;
827 break;
828
829 case 0323:
830 ins->rex |= REX_W; /* 64-bit only instruction */
831 osize = 64;
832 o_used = true;
833 break;
834
835 case 0324:
836 if (osize != 64)
837 return false;
838 o_used = true;
839 break;
840
841 case 0325:
842 ins->rex |= REX_NH;
843 break;
844
845 case 0330:
846 {
847 int t = *r++, d = *data++;
848 if (d < t || d > t + 15)
849 return false;
850 else
851 ins->condition = d - t;
852 break;
853 }
854
855 case 0331:
856 if (prefix->rep)
857 return false;
858 break;
859
860 case 0332:
861 if (prefix->rep != 0xF2)
862 return false;
863 drep = 0;
864 break;
865
866 case 0333:
867 if (prefix->rep != 0xF3)
868 return false;
869 drep = 0;
870 break;
871
872 case 0334:
873 if (lock) {
874 ins->rex |= REX_R;
875 lock = 0;
876 }
877 break;
878
879 case 0335:
880 if (drep == P_REP)
881 drep = P_REPE;
882 break;
883
884 case 0336:
885 case 0337:
886 break;
887
888 case 0340:
889 return false;
890
891 case 0341:
892 if (prefix->wait != 0x9B)
893 return false;
894 dwait = 0;
895 break;
896
897 case4(0344):
898 ins->oprs[0].basereg = (*data++ >> 3) & 7;
899 break;
900
901 case 0360:
902 if (prefix->osp || prefix->rep)
903 return false;
904 break;
905
906 case 0361:
907 if (!prefix->osp || prefix->rep)
908 return false;
909 o_used = true;
910 break;
911
912 case 0362:
913 if (prefix->osp || prefix->rep != 0xf2)
914 return false;
915 drep = 0;
916 break;
917
918 case 0363:
919 if (prefix->osp || prefix->rep != 0xf3)
920 return false;
921 drep = 0;
922 break;
923
924 case 0364:
925 if (prefix->osp)
926 return false;
927 break;
928
929 case 0365:
930 if (prefix->asp)
931 return false;
932 break;
933
934 case 0366:
935 if (!prefix->osp)
936 return false;
937 o_used = true;
938 break;
939
940 case 0367:
941 if (!prefix->asp)
942 return false;
943 a_used = true;
944 break;
945
946 default:
947 return false; /* Unknown code */
948 }
949 }
950
951 if (!vex_ok && (ins->rex & REX_V))
952 return false;
953
954 /* REX cannot be combined with DREX or VEX */
955 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
956 return false;
957
958 /*
959 * Check for unused rep or a/o prefixes.
960 */
961 for (i = 0; i < t->operands; i++) {
962 if (ins->oprs[i].segment != SEG_RMREG)
963 a_used = true;
964 }
965
966 if (lock) {
967 if (ins->prefixes[PPS_LREP])
968 return false;
969 ins->prefixes[PPS_LREP] = P_LOCK;
970 }
971 if (drep) {
972 if (ins->prefixes[PPS_LREP])
973 return false;
974 ins->prefixes[PPS_LREP] = drep;
975 }
976 ins->prefixes[PPS_WAIT] = dwait;
977 if (!o_used) {
978 if (osize != ((segsize == 16) ? 16 : 32)) {
979 enum prefixes pfx = 0;
980
981 switch (osize) {
982 case 16:
983 pfx = P_O16;
984 break;
985 case 32:
986 pfx = P_O32;
987 break;
988 case 64:
989 pfx = P_O64;
990 break;
991 }
992
993 if (ins->prefixes[PPS_OSIZE])
994 return false;
995 ins->prefixes[PPS_OSIZE] = pfx;
996 }
997 }
998 if (!a_used && asize != segsize) {
999 if (ins->prefixes[PPS_ASIZE])
1000 return false;
1001 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
1002 }
1003
1004 /* Fix: check for redundant REX prefixes */
1005
1006 return data - origdata;
1007 }
1008
1009 /* Condition names for disassembly, sorted by x86 code */
1010 static const char * const condition_name[16] = {
1011 "o", "no", "c", "nc", "z", "nz", "na", "a",
1012 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
1013 };
1014
1015 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
1016 int32_t offset, int autosync, uint32_t prefer)
1017 {
1018 const struct itemplate * const *p, * const *best_p;
1019 const struct disasm_index *ix;
1020 uint8_t *dp;
1021 int length, best_length = 0;
1022 char *segover;
1023 int i, slen, colon, n;
1024 uint8_t *origdata;
1025 int works;
1026 insn tmp_ins, ins;
1027 uint32_t goodness, best;
1028 int best_pref;
1029 struct prefix_info prefix;
1030 bool end_prefix;
1031
1032 memset(&ins, 0, sizeof ins);
1033
1034 /*
1035 * Scan for prefixes.
1036 */
1037 memset(&prefix, 0, sizeof prefix);
1038 prefix.asize = segsize;
1039 prefix.osize = (segsize == 64) ? 32 : segsize;
1040 segover = NULL;
1041 origdata = data;
1042
1043 ix = itable;
1044
1045 end_prefix = false;
1046 while (!end_prefix) {
1047 switch (*data) {
1048 case 0xF2:
1049 case 0xF3:
1050 prefix.rep = *data++;
1051 break;
1052
1053 case 0x9B:
1054 prefix.wait = *data++;
1055 break;
1056
1057 case 0xF0:
1058 prefix.lock = *data++;
1059 break;
1060
1061 case 0x2E:
1062 segover = "cs", prefix.seg = *data++;
1063 break;
1064 case 0x36:
1065 segover = "ss", prefix.seg = *data++;
1066 break;
1067 case 0x3E:
1068 segover = "ds", prefix.seg = *data++;
1069 break;
1070 case 0x26:
1071 segover = "es", prefix.seg = *data++;
1072 break;
1073 case 0x64:
1074 segover = "fs", prefix.seg = *data++;
1075 break;
1076 case 0x65:
1077 segover = "gs", prefix.seg = *data++;
1078 break;
1079
1080 case 0x66:
1081 prefix.osize = (segsize == 16) ? 32 : 16;
1082 prefix.osp = *data++;
1083 break;
1084 case 0x67:
1085 prefix.asize = (segsize == 32) ? 16 : 32;
1086 prefix.asp = *data++;
1087 break;
1088
1089 case 0xC4:
1090 case 0xC5:
1091 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1092 prefix.vex[0] = *data++;
1093 prefix.vex[1] = *data++;
1094
1095 prefix.rex = REX_V;
1096 prefix.vex_c = RV_VEX;
1097
1098 if (prefix.vex[0] == 0xc4) {
1099 prefix.vex[2] = *data++;
1100 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1101 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1102 prefix.vex_m = prefix.vex[1] & 0x1f;
1103 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1104 prefix.vex_lp = prefix.vex[2] & 7;
1105 } else {
1106 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1107 prefix.vex_m = 1;
1108 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1109 prefix.vex_lp = prefix.vex[1] & 7;
1110 }
1111
1112 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp];
1113 }
1114 end_prefix = true;
1115 break;
1116
1117 case 0x8F:
1118 if ((data[1] & 030) != 0 &&
1119 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1120 prefix.vex[0] = *data++;
1121 prefix.vex[1] = *data++;
1122 prefix.vex[2] = *data++;
1123
1124 prefix.rex = REX_V;
1125 prefix.vex_c = RV_XOP;
1126
1127 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1128 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1129 prefix.vex_m = prefix.vex[1] & 0x1f;
1130 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1131 prefix.vex_lp = prefix.vex[2] & 7;
1132
1133 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp];
1134 }
1135 end_prefix = true;
1136 break;
1137
1138 case REX_P + 0x0:
1139 case REX_P + 0x1:
1140 case REX_P + 0x2:
1141 case REX_P + 0x3:
1142 case REX_P + 0x4:
1143 case REX_P + 0x5:
1144 case REX_P + 0x6:
1145 case REX_P + 0x7:
1146 case REX_P + 0x8:
1147 case REX_P + 0x9:
1148 case REX_P + 0xA:
1149 case REX_P + 0xB:
1150 case REX_P + 0xC:
1151 case REX_P + 0xD:
1152 case REX_P + 0xE:
1153 case REX_P + 0xF:
1154 if (segsize == 64) {
1155 prefix.rex = *data++;
1156 if (prefix.rex & REX_W)
1157 prefix.osize = 64;
1158 }
1159 end_prefix = true;
1160 break;
1161
1162 default:
1163 end_prefix = true;
1164 break;
1165 }
1166 }
1167
1168 best = -1; /* Worst possible */
1169 best_p = NULL;
1170 best_pref = INT_MAX;
1171
1172 if (!ix)
1173 return 0; /* No instruction table at all... */
1174
1175 dp = data;
1176 ix += *dp++;
1177 while (ix->n == -1) {
1178 ix = (const struct disasm_index *)ix->p + *dp++;
1179 }
1180
1181 p = (const struct itemplate * const *)ix->p;
1182 for (n = ix->n; n; n--, p++) {
1183 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1184 works = true;
1185 /*
1186 * Final check to make sure the types of r/m match up.
1187 * XXX: Need to make sure this is actually correct.
1188 */
1189 for (i = 0; i < (*p)->operands; i++) {
1190 if (!((*p)->opd[i] & SAME_AS) &&
1191 (
1192 /* If it's a mem-only EA but we have a
1193 register, die. */
1194 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1195 is_class(MEMORY, (*p)->opd[i])) ||
1196 /* If it's a reg-only EA but we have a memory
1197 ref, die. */
1198 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1199 !(REG_EA & ~(*p)->opd[i]) &&
1200 !((*p)->opd[i] & REG_SMASK)) ||
1201 /* Register type mismatch (eg FS vs REG_DESS):
1202 die. */
1203 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1204 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1205 !whichreg((*p)->opd[i],
1206 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1207 )) {
1208 works = false;
1209 break;
1210 }
1211 }
1212
1213 /*
1214 * Note: we always prefer instructions which incorporate
1215 * prefixes in the instructions themselves. This is to allow
1216 * e.g. PAUSE to be preferred to REP NOP, and deal with
1217 * MMX/SSE instructions where prefixes are used to select
1218 * between MMX and SSE register sets or outright opcode
1219 * selection.
1220 */
1221 if (works) {
1222 int i, nprefix;
1223 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1224 nprefix = 0;
1225 for (i = 0; i < MAXPREFIX; i++)
1226 if (tmp_ins.prefixes[i])
1227 nprefix++;
1228 if (nprefix < best_pref ||
1229 (nprefix == best_pref && goodness < best)) {
1230 /* This is the best one found so far */
1231 best = goodness;
1232 best_p = p;
1233 best_pref = nprefix;
1234 best_length = length;
1235 ins = tmp_ins;
1236 }
1237 }
1238 }
1239 }
1240
1241 if (!best_p)
1242 return 0; /* no instruction was matched */
1243
1244 /* Pick the best match */
1245 p = best_p;
1246 length = best_length;
1247
1248 slen = 0;
1249
1250 /* TODO: snprintf returns the value that the string would have if
1251 * the buffer were long enough, and not the actual length of
1252 * the returned string, so each instance of using the return
1253 * value of snprintf should actually be checked to assure that
1254 * the return value is "sane." Maybe a macro wrapper could
1255 * be used for that purpose.
1256 */
1257 for (i = 0; i < MAXPREFIX; i++) {
1258 const char *prefix = prefix_name(ins.prefixes[i]);
1259 if (prefix)
1260 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1261 }
1262
1263 i = (*p)->opcode;
1264 if (i >= FIRST_COND_OPCODE)
1265 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1266 nasm_insn_names[i], condition_name[ins.condition]);
1267 else
1268 slen += snprintf(output + slen, outbufsize - slen, "%s",
1269 nasm_insn_names[i]);
1270
1271 colon = false;
1272 length += data - origdata; /* fix up for prefixes */
1273 for (i = 0; i < (*p)->operands; i++) {
1274 opflags_t t = (*p)->opd[i];
1275 const operand *o = &ins.oprs[i];
1276 int64_t offs;
1277
1278 if (t & SAME_AS) {
1279 o = &ins.oprs[t & ~SAME_AS];
1280 t = (*p)->opd[t & ~SAME_AS];
1281 }
1282
1283 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1284
1285 offs = o->offset;
1286 if (o->segment & SEG_RELATIVE) {
1287 offs += offset + length;
1288 /*
1289 * sort out wraparound
1290 */
1291 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1292 offs &= 0xffff;
1293 else if (segsize != 64)
1294 offs &= 0xffffffff;
1295
1296 /*
1297 * add sync marker, if autosync is on
1298 */
1299 if (autosync)
1300 add_sync(offs, 0L);
1301 }
1302
1303 if (t & COLON)
1304 colon = true;
1305 else
1306 colon = false;
1307
1308 if ((t & (REGISTER | FPUREG)) ||
1309 (o->segment & SEG_RMREG)) {
1310 enum reg_enum reg;
1311 reg = whichreg(t, o->basereg, ins.rex);
1312 if (t & TO)
1313 slen += snprintf(output + slen, outbufsize - slen, "to ");
1314 slen += snprintf(output + slen, outbufsize - slen, "%s",
1315 nasm_reg_names[reg-EXPR_REG_START]);
1316 } else if (!(UNITY & ~t)) {
1317 output[slen++] = '1';
1318 } else if (t & IMMEDIATE) {
1319 if (t & BITS8) {
1320 slen +=
1321 snprintf(output + slen, outbufsize - slen, "byte ");
1322 if (o->segment & SEG_SIGNED) {
1323 if (offs < 0) {
1324 offs *= -1;
1325 output[slen++] = '-';
1326 } else
1327 output[slen++] = '+';
1328 }
1329 } else if (t & BITS16) {
1330 slen +=
1331 snprintf(output + slen, outbufsize - slen, "word ");
1332 } else if (t & BITS32) {
1333 slen +=
1334 snprintf(output + slen, outbufsize - slen, "dword ");
1335 } else if (t & BITS64) {
1336 slen +=
1337 snprintf(output + slen, outbufsize - slen, "qword ");
1338 } else if (t & NEAR) {
1339 slen +=
1340 snprintf(output + slen, outbufsize - slen, "near ");
1341 } else if (t & SHORT) {
1342 slen +=
1343 snprintf(output + slen, outbufsize - slen, "short ");
1344 }
1345 slen +=
1346 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1347 offs);
1348 } else if (!(MEM_OFFS & ~t)) {
1349 slen +=
1350 snprintf(output + slen, outbufsize - slen,
1351 "[%s%s%s0x%"PRIx64"]",
1352 (segover ? segover : ""),
1353 (segover ? ":" : ""),
1354 (o->disp_size == 64 ? "qword " :
1355 o->disp_size == 32 ? "dword " :
1356 o->disp_size == 16 ? "word " : ""), offs);
1357 segover = NULL;
1358 } else if (is_class(REGMEM, t)) {
1359 int started = false;
1360 if (t & BITS8)
1361 slen +=
1362 snprintf(output + slen, outbufsize - slen, "byte ");
1363 if (t & BITS16)
1364 slen +=
1365 snprintf(output + slen, outbufsize - slen, "word ");
1366 if (t & BITS32)
1367 slen +=
1368 snprintf(output + slen, outbufsize - slen, "dword ");
1369 if (t & BITS64)
1370 slen +=
1371 snprintf(output + slen, outbufsize - slen, "qword ");
1372 if (t & BITS80)
1373 slen +=
1374 snprintf(output + slen, outbufsize - slen, "tword ");
1375 if (t & BITS128)
1376 slen +=
1377 snprintf(output + slen, outbufsize - slen, "oword ");
1378 if (t & BITS256)
1379 slen +=
1380 snprintf(output + slen, outbufsize - slen, "yword ");
1381 if (t & FAR)
1382 slen += snprintf(output + slen, outbufsize - slen, "far ");
1383 if (t & NEAR)
1384 slen +=
1385 snprintf(output + slen, outbufsize - slen, "near ");
1386 output[slen++] = '[';
1387 if (o->disp_size)
1388 slen += snprintf(output + slen, outbufsize - slen, "%s",
1389 (o->disp_size == 64 ? "qword " :
1390 o->disp_size == 32 ? "dword " :
1391 o->disp_size == 16 ? "word " :
1392 ""));
1393 if (o->eaflags & EAF_REL)
1394 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1395 if (segover) {
1396 slen +=
1397 snprintf(output + slen, outbufsize - slen, "%s:",
1398 segover);
1399 segover = NULL;
1400 }
1401 if (o->basereg != -1) {
1402 slen += snprintf(output + slen, outbufsize - slen, "%s",
1403 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1404 started = true;
1405 }
1406 if (o->indexreg != -1) {
1407 if (started)
1408 output[slen++] = '+';
1409 slen += snprintf(output + slen, outbufsize - slen, "%s",
1410 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1411 if (o->scale > 1)
1412 slen +=
1413 snprintf(output + slen, outbufsize - slen, "*%d",
1414 o->scale);
1415 started = true;
1416 }
1417
1418
1419 if (o->segment & SEG_DISP8) {
1420 const char *prefix;
1421 uint8_t offset = offs;
1422 if ((int8_t)offset < 0) {
1423 prefix = "-";
1424 offset = -offset;
1425 } else {
1426 prefix = "+";
1427 }
1428 slen +=
1429 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1430 prefix, offset);
1431 } else if (o->segment & SEG_DISP16) {
1432 const char *prefix;
1433 uint16_t offset = offs;
1434 if ((int16_t)offset < 0 && started) {
1435 offset = -offset;
1436 prefix = "-";
1437 } else {
1438 prefix = started ? "+" : "";
1439 }
1440 slen +=
1441 snprintf(output + slen, outbufsize - slen,
1442 "%s0x%"PRIx16"", prefix, offset);
1443 } else if (o->segment & SEG_DISP32) {
1444 if (prefix.asize == 64) {
1445 const char *prefix;
1446 uint64_t offset = (int64_t)(int32_t)offs;
1447 if ((int32_t)offs < 0 && started) {
1448 offset = -offset;
1449 prefix = "-";
1450 } else {
1451 prefix = started ? "+" : "";
1452 }
1453 slen +=
1454 snprintf(output + slen, outbufsize - slen,
1455 "%s0x%"PRIx64"", prefix, offset);
1456 } else {
1457 const char *prefix;
1458 uint32_t offset = offs;
1459 if ((int32_t) offset < 0 && started) {
1460 offset = -offset;
1461 prefix = "-";
1462 } else {
1463 prefix = started ? "+" : "";
1464 }
1465 slen +=
1466 snprintf(output + slen, outbufsize - slen,
1467 "%s0x%"PRIx32"", prefix, offset);
1468 }
1469 }
1470 output[slen++] = ']';
1471 } else {
1472 slen +=
1473 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1474 i);
1475 }
1476 }
1477 output[slen] = '\0';
1478 if (segover) { /* unused segment override */
1479 char *p = output;
1480 int count = slen + 1;
1481 while (count--)
1482 p[count + 3] = p[count];
1483 strncpy(output, segover, 2);
1484 output[2] = ' ';
1485 }
1486 return length;
1487 }
1488
1489 /*
1490 * This is called when we don't have a complete instruction. If it
1491 * is a standalone *single-byte* prefix show it as such, otherwise
1492 * print it as a literal.
1493 */
1494 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1495 {
1496 uint8_t byte = *data;
1497 const char *str = NULL;
1498
1499 switch (byte) {
1500 case 0xF2:
1501 str = "repne";
1502 break;
1503 case 0xF3:
1504 str = "rep";
1505 break;
1506 case 0x9B:
1507 str = "wait";
1508 break;
1509 case 0xF0:
1510 str = "lock";
1511 break;
1512 case 0x2E:
1513 str = "cs";
1514 break;
1515 case 0x36:
1516 str = "ss";
1517 break;
1518 case 0x3E:
1519 str = "ss";
1520 break;
1521 case 0x26:
1522 str = "es";
1523 break;
1524 case 0x64:
1525 str = "fs";
1526 break;
1527 case 0x65:
1528 str = "gs";
1529 break;
1530 case 0x66:
1531 str = (segsize == 16) ? "o32" : "o16";
1532 break;
1533 case 0x67:
1534 str = (segsize == 32) ? "a16" : "a32";
1535 break;
1536 case REX_P + 0x0:
1537 case REX_P + 0x1:
1538 case REX_P + 0x2:
1539 case REX_P + 0x3:
1540 case REX_P + 0x4:
1541 case REX_P + 0x5:
1542 case REX_P + 0x6:
1543 case REX_P + 0x7:
1544 case REX_P + 0x8:
1545 case REX_P + 0x9:
1546 case REX_P + 0xA:
1547 case REX_P + 0xB:
1548 case REX_P + 0xC:
1549 case REX_P + 0xD:
1550 case REX_P + 0xE:
1551 case REX_P + 0xF:
1552 if (segsize == 64) {
1553 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1554 (byte == REX_P) ? "" : ".",
1555 (byte & REX_W) ? "w" : "",
1556 (byte & REX_R) ? "r" : "",
1557 (byte & REX_X) ? "x" : "",
1558 (byte & REX_B) ? "b" : "");
1559 break;
1560 }
1561 /* else fall through */
1562 default:
1563 snprintf(output, outbufsize, "db 0x%02x", byte);
1564 break;
1565 }
1566
1567 if (str)
1568 snprintf(output, outbufsize, "%s", str);
1569
1570 return 1;
1571 }
The Netwide Assembler