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version: call this branch 2.13rc0
[nasm.git] / disasm.c
blob8e759fe482dc200c738351da27afd72bd6f1a1d0
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43
44 #include "nasm.h"
45 #include "disasm.h"
46 #include "sync.h"
47 #include "insns.h"
48 #include "tables.h"
49 #include "regdis.h"
50 #include "disp8.h"
51
52 /*
53 * Flags that go into the `segment' field of `insn' structures
54 * during disassembly.
55 */
56 #define SEG_RELATIVE 1
57 #define SEG_32BIT 2
58 #define SEG_RMREG 4
59 #define SEG_DISP8 8
60 #define SEG_DISP16 16
61 #define SEG_DISP32 32
62 #define SEG_NODISP 64
63 #define SEG_SIGNED 128
64 #define SEG_64BIT 256
65
66 /*
67 * Prefix information
68 */
69 struct prefix_info {
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
81 uint8_t vex_v;
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
84 uint8_t evex[3]; /* EVEX prefix present */
85 };
86
87 #define getu8(x) (*(uint8_t *)(x))
88 #if X86_MEMORY
89 /* Littleendian CPU which can handle unaligned references */
90 #define getu16(x) (*(uint16_t *)(x))
91 #define getu32(x) (*(uint32_t *)(x))
92 #define getu64(x) (*(uint64_t *)(x))
93 #else
94 static uint16_t getu16(uint8_t *data)
95 {
96 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
97 }
98 static uint32_t getu32(uint8_t *data)
99 {
100 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
101 }
102 static uint64_t getu64(uint8_t *data)
103 {
104 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
105 }
106 #endif
107
108 #define gets8(x) ((int8_t)getu8(x))
109 #define gets16(x) ((int16_t)getu16(x))
110 #define gets32(x) ((int32_t)getu32(x))
111 #define gets64(x) ((int64_t)getu64(x))
112
113 /* Important: regval must already have been adjusted for rex extensions */
114 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
115 {
116 size_t i;
117
118 static const struct {
119 opflags_t flags;
120 enum reg_enum reg;
121 } specific_registers[] = {
122 {REG_AL, R_AL},
123 {REG_AX, R_AX},
124 {REG_EAX, R_EAX},
125 {REG_RAX, R_RAX},
126 {REG_DL, R_DL},
127 {REG_DX, R_DX},
128 {REG_EDX, R_EDX},
129 {REG_RDX, R_RDX},
130 {REG_CL, R_CL},
131 {REG_CX, R_CX},
132 {REG_ECX, R_ECX},
133 {REG_RCX, R_RCX},
134 {FPU0, R_ST0},
135 {XMM0, R_XMM0},
136 {YMM0, R_YMM0},
137 {ZMM0, R_ZMM0},
138 {REG_ES, R_ES},
139 {REG_CS, R_CS},
140 {REG_SS, R_SS},
141 {REG_DS, R_DS},
142 {REG_FS, R_FS},
143 {REG_GS, R_GS},
144 {OPMASK0, R_K0},
145 };
146
147 if (!(regflags & (REGISTER|REGMEM)))
148 return 0; /* Registers not permissible?! */
149
150 regflags |= REGISTER;
151
152 for (i = 0; i < ARRAY_SIZE(specific_registers); i++)
153 if (!(specific_registers[i].flags & ~regflags))
154 return specific_registers[i].reg;
155
156 /* All the entries below look up regval in an 16-entry array */
157 if (regval < 0 || regval > (rex & REX_EV ? 31 : 15))
158 return 0;
159
160 #define GET_REGISTER(__array, __index) \
161 ((size_t)(__index) < (size_t)ARRAY_SIZE(__array) ? __array[(__index)] : 0)
162
163 if (!(REG8 & ~regflags)) {
164 if (rex & (REX_P|REX_NH))
165 return GET_REGISTER(nasm_rd_reg8_rex, regval);
166 else
167 return GET_REGISTER(nasm_rd_reg8, regval);
168 }
169 if (!(REG16 & ~regflags))
170 return GET_REGISTER(nasm_rd_reg16, regval);
171 if (!(REG32 & ~regflags))
172 return GET_REGISTER(nasm_rd_reg32, regval);
173 if (!(REG64 & ~regflags))
174 return GET_REGISTER(nasm_rd_reg64, regval);
175 if (!(REG_SREG & ~regflags))
176 return GET_REGISTER(nasm_rd_sreg, regval & 7); /* Ignore REX */
177 if (!(REG_CREG & ~regflags))
178 return GET_REGISTER(nasm_rd_creg, regval);
179 if (!(REG_DREG & ~regflags))
180 return GET_REGISTER(nasm_rd_dreg, regval);
181 if (!(REG_TREG & ~regflags)) {
182 if (regval > 7)
183 return 0; /* TR registers are ill-defined with rex */
184 return GET_REGISTER(nasm_rd_treg, regval);
185 }
186 if (!(FPUREG & ~regflags))
187 return GET_REGISTER(nasm_rd_fpureg, regval & 7); /* Ignore REX */
188 if (!(MMXREG & ~regflags))
189 return GET_REGISTER(nasm_rd_mmxreg, regval & 7); /* Ignore REX */
190 if (!(XMMREG & ~regflags))
191 return GET_REGISTER(nasm_rd_xmmreg, regval);
192 if (!(YMMREG & ~regflags))
193 return GET_REGISTER(nasm_rd_ymmreg, regval);
194 if (!(ZMMREG & ~regflags))
195 return GET_REGISTER(nasm_rd_zmmreg, regval);
196 if (!(OPMASKREG & ~regflags))
197 return GET_REGISTER(nasm_rd_opmaskreg, regval);
198 if (!(BNDREG & ~regflags))
199 return GET_REGISTER(nasm_rd_bndreg, regval);
200
201 #undef GET_REGISTER
202 return 0;
203 }
204
205 static uint32_t append_evex_reg_deco(char *buf, uint32_t num,
206 decoflags_t deco, uint8_t *evex)
207 {
208 const char * const er_names[] = {"rn-sae", "rd-sae", "ru-sae", "rz-sae"};
209 uint32_t num_chars = 0;
210
211 if ((deco & MASK) && (evex[2] & EVEX_P2AAA)) {
212 enum reg_enum opmasknum = nasm_rd_opmaskreg[evex[2] & EVEX_P2AAA];
213 const char * regname = nasm_reg_names[opmasknum - EXPR_REG_START];
214
215 num_chars += snprintf(buf + num_chars, num - num_chars,
216 "{%s}", regname);
217
218 if ((deco & Z) && (evex[2] & EVEX_P2Z)) {
219 num_chars += snprintf(buf + num_chars, num - num_chars,
220 "{z}");
221 }
222 }
223
224 if (evex[2] & EVEX_P2B) {
225 if (deco & ER) {
226 uint8_t er_type = (evex[2] & EVEX_P2LL) >> 5;
227 num_chars += snprintf(buf + num_chars, num - num_chars,
228 ",{%s}", er_names[er_type]);
229 } else if (deco & SAE) {
230 num_chars += snprintf(buf + num_chars, num - num_chars,
231 ",{sae}");
232 }
233 }
234
235 return num_chars;
236 }
237
238 static uint32_t append_evex_mem_deco(char *buf, uint32_t num, opflags_t type,
239 decoflags_t deco, uint8_t *evex)
240 {
241 uint32_t num_chars = 0;
242
243 if ((evex[2] & EVEX_P2B) && (deco & BRDCAST_MASK)) {
244 decoflags_t deco_brsize = deco & BRSIZE_MASK;
245 opflags_t template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
246 uint8_t br_num = (type & SIZE_MASK) / BITS128 *
247 BITS64 / template_opsize * 2;
248
249 num_chars += snprintf(buf + num_chars, num - num_chars,
250 "{1to%d}", br_num);
251 }
252
253 if ((deco & MASK) && (evex[2] & EVEX_P2AAA)) {
254 enum reg_enum opmasknum = nasm_rd_opmaskreg[evex[2] & EVEX_P2AAA];
255 const char * regname = nasm_reg_names[opmasknum - EXPR_REG_START];
256
257 num_chars += snprintf(buf + num_chars, num - num_chars,
258 "{%s}", regname);
259
260 if ((deco & Z) && (evex[2] & EVEX_P2Z)) {
261 num_chars += snprintf(buf + num_chars, num - num_chars,
262 "{z}");
263 }
264 }
265
266
267 return num_chars;
268 }
269
270 /*
271 * Process an effective address (ModRM) specification.
272 */
273 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
274 int segsize, enum ea_type type,
275 operand *op, insn *ins)
276 {
277 int mod, rm, scale, index, base;
278 int rex;
279 uint8_t *evex;
280 uint8_t sib = 0;
281 bool is_evex = !!(ins->rex & REX_EV);
282
283 mod = (modrm >> 6) & 03;
284 rm = modrm & 07;
285
286 if (mod != 3 && asize != 16 && rm == 4)
287 sib = *data++;
288
289 rex = ins->rex;
290 evex = ins->evex_p;
291
292 if (mod == 3) { /* pure register version */
293 op->basereg = rm+(rex & REX_B ? 8 : 0);
294 op->segment |= SEG_RMREG;
295 if (is_evex && segsize == 64) {
296 op->basereg += (evex[0] & EVEX_P0X ? 0 : 16);
297 }
298 return data;
299 }
300
301 op->disp_size = 0;
302 op->eaflags = 0;
303
304 if (asize == 16) {
305 /*
306 * <mod> specifies the displacement size (none, byte or
307 * word), and <rm> specifies the register combination.
308 * Exception: mod=0,rm=6 does not specify [BP] as one might
309 * expect, but instead specifies [disp16].
310 */
311
312 if (type != EA_SCALAR)
313 return NULL;
314
315 op->indexreg = op->basereg = -1;
316 op->scale = 1; /* always, in 16 bits */
317 switch (rm) {
318 case 0:
319 op->basereg = R_BX;
320 op->indexreg = R_SI;
321 break;
322 case 1:
323 op->basereg = R_BX;
324 op->indexreg = R_DI;
325 break;
326 case 2:
327 op->basereg = R_BP;
328 op->indexreg = R_SI;
329 break;
330 case 3:
331 op->basereg = R_BP;
332 op->indexreg = R_DI;
333 break;
334 case 4:
335 op->basereg = R_SI;
336 break;
337 case 5:
338 op->basereg = R_DI;
339 break;
340 case 6:
341 op->basereg = R_BP;
342 break;
343 case 7:
344 op->basereg = R_BX;
345 break;
346 }
347 if (rm == 6 && mod == 0) { /* special case */
348 op->basereg = -1;
349 if (segsize != 16)
350 op->disp_size = 16;
351 mod = 2; /* fake disp16 */
352 }
353 switch (mod) {
354 case 0:
355 op->segment |= SEG_NODISP;
356 break;
357 case 1:
358 op->segment |= SEG_DISP8;
359 if (ins->evex_tuple != 0) {
360 op->offset = gets8(data) * get_disp8N(ins);
361 } else {
362 op->offset = gets8(data);
363 }
364 data++;
365 break;
366 case 2:
367 op->segment |= SEG_DISP16;
368 op->offset = *data++;
369 op->offset |= ((unsigned)*data++) << 8;
370 break;
371 }
372 return data;
373 } else {
374 /*
375 * Once again, <mod> specifies displacement size (this time
376 * none, byte or *dword*), while <rm> specifies the base
377 * register. Again, [EBP] is missing, replaced by a pure
378 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
379 * and RIP-relative addressing in 64-bit mode.
380 *
381 * However, rm=4
382 * indicates not a single base register, but instead the
383 * presence of a SIB byte...
384 */
385 int a64 = asize == 64;
386
387 op->indexreg = -1;
388
389 if (a64)
390 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
391 else
392 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
393
394 if (rm == 5 && mod == 0) {
395 if (segsize == 64) {
396 op->eaflags |= EAF_REL;
397 op->segment |= SEG_RELATIVE;
398 mod = 2; /* fake disp32 */
399 }
400
401 if (asize != 64)
402 op->disp_size = asize;
403
404 op->basereg = -1;
405 mod = 2; /* fake disp32 */
406 }
407
408
409 if (rm == 4) { /* process SIB */
410 uint8_t vsib_hi = 0;
411 scale = (sib >> 6) & 03;
412 index = (sib >> 3) & 07;
413 base = sib & 07;
414
415 op->scale = 1 << scale;
416
417 if (segsize == 64) {
418 vsib_hi = (rex & REX_X ? 8 : 0) |
419 (evex[2] & EVEX_P2VP ? 0 : 16);
420 }
421
422 if (type == EA_XMMVSIB)
423 op->indexreg = nasm_rd_xmmreg[index | vsib_hi];
424 else if (type == EA_YMMVSIB)
425 op->indexreg = nasm_rd_ymmreg[index | vsib_hi];
426 else if (type == EA_ZMMVSIB)
427 op->indexreg = nasm_rd_zmmreg[index | vsib_hi];
428 else if (index == 4 && !(rex & REX_X))
429 op->indexreg = -1; /* ESP/RSP cannot be an index */
430 else if (a64)
431 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
432 else
433 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
434
435 if (base == 5 && mod == 0) {
436 op->basereg = -1;
437 mod = 2; /* Fake disp32 */
438 } else if (a64)
439 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
440 else
441 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
442
443 if (segsize == 16)
444 op->disp_size = 32;
445 } else if (type != EA_SCALAR) {
446 /* Can't have VSIB without SIB */
447 return NULL;
448 }
449
450 switch (mod) {
451 case 0:
452 op->segment |= SEG_NODISP;
453 break;
454 case 1:
455 op->segment |= SEG_DISP8;
456 if (ins->evex_tuple != 0) {
457 op->offset = gets8(data) * get_disp8N(ins);
458 } else {
459 op->offset = gets8(data);
460 }
461 data++;
462 break;
463 case 2:
464 op->segment |= SEG_DISP32;
465 op->offset = gets32(data);
466 data += 4;
467 break;
468 }
469 return data;
470 }
471 }
472
473 /*
474 * Determine whether the instruction template in t corresponds to the data
475 * stream in data. Return the number of bytes matched if so.
476 */
477 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
478
479 static int matches(const struct itemplate *t, uint8_t *data,
480 const struct prefix_info *prefix, int segsize, insn *ins)
481 {
482 uint8_t *r = (uint8_t *)(t->code);
483 uint8_t *origdata = data;
484 bool a_used = false, o_used = false;
485 enum prefixes drep = 0;
486 enum prefixes dwait = 0;
487 uint8_t lock = prefix->lock;
488 int osize = prefix->osize;
489 int asize = prefix->asize;
490 int i, c;
491 int op1, op2;
492 struct operand *opx, *opy;
493 uint8_t opex = 0;
494 bool vex_ok = false;
495 int regmask = (segsize == 64) ? 15 : 7;
496 enum ea_type eat = EA_SCALAR;
497
498 for (i = 0; i < MAX_OPERANDS; i++) {
499 ins->oprs[i].segment = ins->oprs[i].disp_size =
500 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
501 }
502 ins->condition = -1;
503 ins->evex_tuple = 0;
504 ins->rex = prefix->rex;
505 memset(ins->prefixes, 0, sizeof ins->prefixes);
506
507 if (itemp_has(t, (segsize == 64 ? IF_NOLONG : IF_LONG)))
508 return 0;
509
510 if (prefix->rep == 0xF2)
511 drep = (itemp_has(t, IF_BND) ? P_BND : P_REPNE);
512 else if (prefix->rep == 0xF3)
513 drep = P_REP;
514
515 dwait = prefix->wait ? P_WAIT : 0;
516
517 while ((c = *r++) != 0) {
518 op1 = (c & 3) + ((opex & 1) << 2);
519 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
520 opx = &ins->oprs[op1];
521 opy = &ins->oprs[op2];
522 opex = 0;
523
524 switch (c) {
525 case 01:
526 case 02:
527 case 03:
528 case 04:
529 while (c--)
530 if (*r++ != *data++)
531 return 0;
532 break;
533
534 case 05:
535 case 06:
536 case 07:
537 opex = c;
538 break;
539
540 case4(010):
541 {
542 int t = *r++, d = *data++;
543 if (d < t || d > t + 7)
544 return 0;
545 else {
546 opx->basereg = (d-t)+
547 (ins->rex & REX_B ? 8 : 0);
548 opx->segment |= SEG_RMREG;
549 }
550 break;
551 }
552
553 case4(014):
554 /* this is an separate index reg position of MIB operand (ICC) */
555 /* Disassembler uses NASM's split EA form only */
556 break;
557
558 case4(0274):
559 opx->offset = (int8_t)*data++;
560 opx->segment |= SEG_SIGNED;
561 break;
562
563 case4(020):
564 opx->offset = *data++;
565 break;
566
567 case4(024):
568 opx->offset = *data++;
569 break;
570
571 case4(030):
572 opx->offset = getu16(data);
573 data += 2;
574 break;
575
576 case4(034):
577 if (osize == 32) {
578 opx->offset = getu32(data);
579 data += 4;
580 } else {
581 opx->offset = getu16(data);
582 data += 2;
583 }
584 if (segsize != asize)
585 opx->disp_size = asize;
586 break;
587
588 case4(040):
589 opx->offset = getu32(data);
590 data += 4;
591 break;
592
593 case4(0254):
594 opx->offset = gets32(data);
595 data += 4;
596 break;
597
598 case4(044):
599 switch (asize) {
600 case 16:
601 opx->offset = getu16(data);
602 data += 2;
603 if (segsize != 16)
604 opx->disp_size = 16;
605 break;
606 case 32:
607 opx->offset = getu32(data);
608 data += 4;
609 if (segsize == 16)
610 opx->disp_size = 32;
611 break;
612 case 64:
613 opx->offset = getu64(data);
614 opx->disp_size = 64;
615 data += 8;
616 break;
617 }
618 break;
619
620 case4(050):
621 opx->offset = gets8(data++);
622 opx->segment |= SEG_RELATIVE;
623 break;
624
625 case4(054):
626 opx->offset = getu64(data);
627 data += 8;
628 break;
629
630 case4(060):
631 opx->offset = gets16(data);
632 data += 2;
633 opx->segment |= SEG_RELATIVE;
634 opx->segment &= ~SEG_32BIT;
635 break;
636
637 case4(064): /* rel */
638 opx->segment |= SEG_RELATIVE;
639 /* In long mode rel is always 32 bits, sign extended. */
640 if (segsize == 64 || osize == 32) {
641 opx->offset = gets32(data);
642 data += 4;
643 if (segsize != 64)
644 opx->segment |= SEG_32BIT;
645 opx->type = (opx->type & ~SIZE_MASK)
646 | (segsize == 64 ? BITS64 : BITS32);
647 } else {
648 opx->offset = gets16(data);
649 data += 2;
650 opx->segment &= ~SEG_32BIT;
651 opx->type = (opx->type & ~SIZE_MASK) | BITS16;
652 }
653 break;
654
655 case4(070):
656 opx->offset = gets32(data);
657 data += 4;
658 opx->segment |= SEG_32BIT | SEG_RELATIVE;
659 break;
660
661 case4(0100):
662 case4(0110):
663 case4(0120):
664 case4(0130):
665 {
666 int modrm = *data++;
667 opx->segment |= SEG_RMREG;
668 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
669 if (!data)
670 return 0;
671 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
672 if ((ins->rex & REX_EV) && (segsize == 64))
673 opx->basereg += (ins->evex_p[0] & EVEX_P0RP ? 0 : 16);
674 break;
675 }
676
677 case 0172:
678 {
679 uint8_t ximm = *data++;
680 c = *r++;
681 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
682 ins->oprs[c >> 3].segment |= SEG_RMREG;
683 ins->oprs[c & 7].offset = ximm & 15;
684 }
685 break;
686
687 case 0173:
688 {
689 uint8_t ximm = *data++;
690 c = *r++;
691
692 if ((c ^ ximm) & 15)
693 return 0;
694
695 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
696 ins->oprs[c >> 4].segment |= SEG_RMREG;
697 }
698 break;
699
700 case4(0174):
701 {
702 uint8_t ximm = *data++;
703
704 opx->basereg = (ximm >> 4) & regmask;
705 opx->segment |= SEG_RMREG;
706 }
707 break;
708
709 case4(0200):
710 case4(0204):
711 case4(0210):
712 case4(0214):
713 case4(0220):
714 case4(0224):
715 case4(0230):
716 case4(0234):
717 {
718 int modrm = *data++;
719 if (((modrm >> 3) & 07) != (c & 07))
720 return 0; /* spare field doesn't match up */
721 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
722 if (!data)
723 return 0;
724 break;
725 }
726
727 case4(0240):
728 case 0250:
729 {
730 uint8_t evexm = *r++;
731 uint8_t evexwlp = *r++;
732 uint8_t modrm, valid_mask;
733 ins->evex_tuple = *r++ - 0300;
734 modrm = *(origdata + 1);
735
736 ins->rex |= REX_EV;
737 if ((prefix->rex & (REX_EV|REX_V|REX_P)) != REX_EV)
738 return 0;
739
740 if ((evexm & 0x1f) != prefix->vex_m)
741 return 0;
742
743 switch (evexwlp & 060) {
744 case 000:
745 if (prefix->rex & REX_W)
746 return 0;
747 break;
748 case 020:
749 if (!(prefix->rex & REX_W))
750 return 0;
751 ins->rex |= REX_W;
752 break;
753 case 040: /* VEX.W is a don't care */
754 ins->rex &= ~REX_W;
755 break;
756 case 060:
757 break;
758 }
759
760 /* If EVEX.b is set with reg-reg op,
761 * EVEX.L'L contains embedded rounding control info
762 */
763 if ((prefix->evex[2] & EVEX_P2B) && ((modrm >> 6) == 3)) {
764 valid_mask = 0x3; /* prefix only */
765 } else {
766 valid_mask = 0xf; /* vector length and prefix */
767 }
768 if ((evexwlp ^ prefix->vex_lp) & valid_mask)
769 return 0;
770
771 if (c == 0250) {
772 if ((prefix->vex_v != 0) ||
773 (!(prefix->evex[2] & EVEX_P2VP) &&
774 ((eat < EA_XMMVSIB) || (eat > EA_ZMMVSIB))))
775 return 0;
776 } else {
777 opx->segment |= SEG_RMREG;
778 opx->basereg = ((~prefix->evex[2] & EVEX_P2VP) << (4 - 3) ) |
779 prefix->vex_v;
780 }
781 vex_ok = true;
782 memcpy(ins->evex_p, prefix->evex, 3);
783 break;
784 }
785
786 case4(0260):
787 case 0270:
788 {
789 int vexm = *r++;
790 int vexwlp = *r++;
791
792 ins->rex |= REX_V;
793 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
794 return 0;
795
796 if ((vexm & 0x1f) != prefix->vex_m)
797 return 0;
798
799 switch (vexwlp & 060) {
800 case 000:
801 if (prefix->rex & REX_W)
802 return 0;
803 break;
804 case 020:
805 if (!(prefix->rex & REX_W))
806 return 0;
807 ins->rex &= ~REX_W;
808 break;
809 case 040: /* VEX.W is a don't care */
810 ins->rex &= ~REX_W;
811 break;
812 case 060:
813 break;
814 }
815
816 /* The 010 bit of vexwlp is set if VEX.L is ignored */
817 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
818 return 0;
819
820 if (c == 0270) {
821 if (prefix->vex_v != 0)
822 return 0;
823 } else {
824 opx->segment |= SEG_RMREG;
825 opx->basereg = prefix->vex_v;
826 }
827 vex_ok = true;
828 break;
829 }
830
831 case 0271:
832 if (prefix->rep == 0xF3)
833 drep = P_XRELEASE;
834 break;
835
836 case 0272:
837 if (prefix->rep == 0xF2)
838 drep = P_XACQUIRE;
839 else if (prefix->rep == 0xF3)
840 drep = P_XRELEASE;
841 break;
842
843 case 0273:
844 if (prefix->lock == 0xF0) {
845 if (prefix->rep == 0xF2)
846 drep = P_XACQUIRE;
847 else if (prefix->rep == 0xF3)
848 drep = P_XRELEASE;
849 }
850 break;
851
852 case 0310:
853 if (asize != 16)
854 return 0;
855 else
856 a_used = true;
857 break;
858
859 case 0311:
860 if (asize != 32)
861 return 0;
862 else
863 a_used = true;
864 break;
865
866 case 0312:
867 if (asize != segsize)
868 return 0;
869 else
870 a_used = true;
871 break;
872
873 case 0313:
874 if (asize != 64)
875 return 0;
876 else
877 a_used = true;
878 break;
879
880 case 0314:
881 if (prefix->rex & REX_B)
882 return 0;
883 break;
884
885 case 0315:
886 if (prefix->rex & REX_X)
887 return 0;
888 break;
889
890 case 0316:
891 if (prefix->rex & REX_R)
892 return 0;
893 break;
894
895 case 0317:
896 if (prefix->rex & REX_W)
897 return 0;
898 break;
899
900 case 0320:
901 if (osize != 16)
902 return 0;
903 else
904 o_used = true;
905 break;
906
907 case 0321:
908 if (osize != 32)
909 return 0;
910 else
911 o_used = true;
912 break;
913
914 case 0322:
915 if (osize != (segsize == 16) ? 16 : 32)
916 return 0;
917 else
918 o_used = true;
919 break;
920
921 case 0323:
922 ins->rex |= REX_W; /* 64-bit only instruction */
923 osize = 64;
924 o_used = true;
925 break;
926
927 case 0324:
928 if (osize != 64)
929 return 0;
930 o_used = true;
931 break;
932
933 case 0325:
934 ins->rex |= REX_NH;
935 break;
936
937 case 0330:
938 {
939 int t = *r++, d = *data++;
940 if (d < t || d > t + 15)
941 return 0;
942 else
943 ins->condition = d - t;
944 break;
945 }
946
947 case 0326:
948 if (prefix->rep == 0xF3)
949 return 0;
950 break;
951
952 case 0331:
953 if (prefix->rep)
954 return 0;
955 break;
956
957 case 0332:
958 if (prefix->rep != 0xF2)
959 return 0;
960 drep = 0;
961 break;
962
963 case 0333:
964 if (prefix->rep != 0xF3)
965 return 0;
966 drep = 0;
967 break;
968
969 case 0334:
970 if (lock) {
971 ins->rex |= REX_R;
972 lock = 0;
973 }
974 break;
975
976 case 0335:
977 if (drep == P_REP)
978 drep = P_REPE;
979 break;
980
981 case 0336:
982 case 0337:
983 break;
984
985 case 0340:
986 return 0;
987
988 case 0341:
989 if (prefix->wait != 0x9B)
990 return 0;
991 dwait = 0;
992 break;
993
994 case 0360:
995 if (prefix->osp || prefix->rep)
996 return 0;
997 break;
998
999 case 0361:
1000 if (!prefix->osp || prefix->rep)
1001 return 0;
1002 o_used = true;
1003 break;
1004
1005 case 0364:
1006 if (prefix->osp)
1007 return 0;
1008 break;
1009
1010 case 0365:
1011 if (prefix->asp)
1012 return 0;
1013 break;
1014
1015 case 0366:
1016 if (!prefix->osp)
1017 return 0;
1018 o_used = true;
1019 break;
1020
1021 case 0367:
1022 if (!prefix->asp)
1023 return 0;
1024 a_used = true;
1025 break;
1026
1027 case 0370:
1028 case 0371:
1029 break;
1030
1031 case 0374:
1032 eat = EA_XMMVSIB;
1033 break;
1034
1035 case 0375:
1036 eat = EA_YMMVSIB;
1037 break;
1038
1039 case 0376:
1040 eat = EA_ZMMVSIB;
1041 break;
1042
1043 default:
1044 return 0; /* Unknown code */
1045 }
1046 }
1047
1048 if (!vex_ok && (ins->rex & (REX_V | REX_EV)))
1049 return 0;
1050
1051 /* REX cannot be combined with VEX */
1052 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
1053 return 0;
1054
1055 /*
1056 * Check for unused rep or a/o prefixes.
1057 */
1058 for (i = 0; i < t->operands; i++) {
1059 if (ins->oprs[i].segment != SEG_RMREG)
1060 a_used = true;
1061 }
1062
1063 if (lock) {
1064 if (ins->prefixes[PPS_LOCK])
1065 return 0;
1066 ins->prefixes[PPS_LOCK] = P_LOCK;
1067 }
1068 if (drep) {
1069 if (ins->prefixes[PPS_REP])
1070 return 0;
1071 ins->prefixes[PPS_REP] = drep;
1072 }
1073 ins->prefixes[PPS_WAIT] = dwait;
1074 if (!o_used) {
1075 if (osize != ((segsize == 16) ? 16 : 32)) {
1076 enum prefixes pfx = 0;
1077
1078 switch (osize) {
1079 case 16:
1080 pfx = P_O16;
1081 break;
1082 case 32:
1083 pfx = P_O32;
1084 break;
1085 case 64:
1086 pfx = P_O64;
1087 break;
1088 }
1089
1090 if (ins->prefixes[PPS_OSIZE])
1091 return 0;
1092 ins->prefixes[PPS_OSIZE] = pfx;
1093 }
1094 }
1095 if (!a_used && asize != segsize) {
1096 if (ins->prefixes[PPS_ASIZE])
1097 return 0;
1098 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
1099 }
1100
1101 /* Fix: check for redundant REX prefixes */
1102
1103 return data - origdata;
1104 }
1105
1106 /* Condition names for disassembly, sorted by x86 code */
1107 static const char * const condition_name[16] = {
1108 "o", "no", "c", "nc", "z", "nz", "na", "a",
1109 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
1110 };
1111
1112 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
1113 int32_t offset, int autosync, iflag_t *prefer)
1114 {
1115 const struct itemplate * const *p, * const *best_p;
1116 const struct disasm_index *ix;
1117 uint8_t *dp;
1118 int length, best_length = 0;
1119 char *segover;
1120 int i, slen, colon, n;
1121 uint8_t *origdata;
1122 int works;
1123 insn tmp_ins, ins;
1124 iflag_t goodness, best;
1125 int best_pref;
1126 struct prefix_info prefix;
1127 bool end_prefix;
1128 bool is_evex;
1129
1130 memset(&ins, 0, sizeof ins);
1131
1132 /*
1133 * Scan for prefixes.
1134 */
1135 memset(&prefix, 0, sizeof prefix);
1136 prefix.asize = segsize;
1137 prefix.osize = (segsize == 64) ? 32 : segsize;
1138 segover = NULL;
1139 origdata = data;
1140
1141 ix = itable;
1142
1143 end_prefix = false;
1144 while (!end_prefix) {
1145 switch (*data) {
1146 case 0xF2:
1147 case 0xF3:
1148 prefix.rep = *data++;
1149 break;
1150
1151 case 0x9B:
1152 prefix.wait = *data++;
1153 break;
1154
1155 case 0xF0:
1156 prefix.lock = *data++;
1157 break;
1158
1159 case 0x2E:
1160 segover = "cs", prefix.seg = *data++;
1161 break;
1162 case 0x36:
1163 segover = "ss", prefix.seg = *data++;
1164 break;
1165 case 0x3E:
1166 segover = "ds", prefix.seg = *data++;
1167 break;
1168 case 0x26:
1169 segover = "es", prefix.seg = *data++;
1170 break;
1171 case 0x64:
1172 segover = "fs", prefix.seg = *data++;
1173 break;
1174 case 0x65:
1175 segover = "gs", prefix.seg = *data++;
1176 break;
1177
1178 case 0x66:
1179 prefix.osize = (segsize == 16) ? 32 : 16;
1180 prefix.osp = *data++;
1181 break;
1182 case 0x67:
1183 prefix.asize = (segsize == 32) ? 16 : 32;
1184 prefix.asp = *data++;
1185 break;
1186
1187 case 0xC4:
1188 case 0xC5:
1189 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1190 prefix.vex[0] = *data++;
1191 prefix.vex[1] = *data++;
1192
1193 prefix.rex = REX_V;
1194 prefix.vex_c = RV_VEX;
1195
1196 if (prefix.vex[0] == 0xc4) {
1197 prefix.vex[2] = *data++;
1198 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1199 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1200 prefix.vex_m = prefix.vex[1] & 0x1f;
1201 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1202 prefix.vex_lp = prefix.vex[2] & 7;
1203 } else {
1204 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1205 prefix.vex_m = 1;
1206 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1207 prefix.vex_lp = prefix.vex[1] & 7;
1208 }
1209
1210 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1211 }
1212 end_prefix = true;
1213 break;
1214
1215 case 0x62:
1216 {
1217 if (segsize == 64 || ((data[1] & 0xc0) == 0xc0)) {
1218 data++; /* 62h EVEX prefix */
1219 prefix.evex[0] = *data++;
1220 prefix.evex[1] = *data++;
1221 prefix.evex[2] = *data++;
1222
1223 prefix.rex = REX_EV;
1224 prefix.vex_c = RV_EVEX;
1225 prefix.rex |= (~prefix.evex[0] >> 5) & 7; /* REX_RXB */
1226 prefix.rex |= (prefix.evex[1] >> (7-3)) & REX_W;
1227 prefix.vex_m = prefix.evex[0] & EVEX_P0MM;
1228 prefix.vex_v = (~prefix.evex[1] & EVEX_P1VVVV) >> 3;
1229 prefix.vex_lp = ((prefix.evex[2] & EVEX_P2LL) >> (5-2)) |
1230 (prefix.evex[1] & EVEX_P1PP);
1231
1232 ix = itable_vex[prefix.vex_c][prefix.vex_m][prefix.vex_lp & 3];
1233 }
1234 end_prefix = true;
1235 break;
1236 }
1237
1238 case 0x8F:
1239 if ((data[1] & 030) != 0 &&
1240 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1241 prefix.vex[0] = *data++;
1242 prefix.vex[1] = *data++;
1243 prefix.vex[2] = *data++;
1244
1245 prefix.rex = REX_V;
1246 prefix.vex_c = RV_XOP;
1247
1248 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1249 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1250 prefix.vex_m = prefix.vex[1] & 0x1f;
1251 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1252 prefix.vex_lp = prefix.vex[2] & 7;
1253
1254 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1255 }
1256 end_prefix = true;
1257 break;
1258
1259 case REX_P + 0x0:
1260 case REX_P + 0x1:
1261 case REX_P + 0x2:
1262 case REX_P + 0x3:
1263 case REX_P + 0x4:
1264 case REX_P + 0x5:
1265 case REX_P + 0x6:
1266 case REX_P + 0x7:
1267 case REX_P + 0x8:
1268 case REX_P + 0x9:
1269 case REX_P + 0xA:
1270 case REX_P + 0xB:
1271 case REX_P + 0xC:
1272 case REX_P + 0xD:
1273 case REX_P + 0xE:
1274 case REX_P + 0xF:
1275 if (segsize == 64) {
1276 prefix.rex = *data++;
1277 if (prefix.rex & REX_W)
1278 prefix.osize = 64;
1279 }
1280 end_prefix = true;
1281 break;
1282
1283 default:
1284 end_prefix = true;
1285 break;
1286 }
1287 }
1288
1289 iflag_set_all(&best); /* Worst possible */
1290 best_p = NULL;
1291 best_pref = INT_MAX;
1292
1293 if (!ix)
1294 return 0; /* No instruction table at all... */
1295
1296 dp = data;
1297 ix += *dp++;
1298 while (ix->n == -1) {
1299 ix = (const struct disasm_index *)ix->p + *dp++;
1300 }
1301
1302 p = (const struct itemplate * const *)ix->p;
1303 for (n = ix->n; n; n--, p++) {
1304 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1305 works = true;
1306 /*
1307 * Final check to make sure the types of r/m match up.
1308 * XXX: Need to make sure this is actually correct.
1309 */
1310 for (i = 0; i < (*p)->operands; i++) {
1311 if (
1312 /* If it's a mem-only EA but we have a
1313 register, die. */
1314 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1315 is_class(MEMORY, (*p)->opd[i])) ||
1316 /* If it's a reg-only EA but we have a memory
1317 ref, die. */
1318 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1319 !(REG_EA & ~(*p)->opd[i]) &&
1320 !((*p)->opd[i] & REG_SMASK)) ||
1321 /* Register type mismatch (eg FS vs REG_DESS):
1322 die. */
1323 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1324 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1325 !whichreg((*p)->opd[i],
1326 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1327 ) {
1328 works = false;
1329 break;
1330 }
1331 }
1332
1333 /*
1334 * Note: we always prefer instructions which incorporate
1335 * prefixes in the instructions themselves. This is to allow
1336 * e.g. PAUSE to be preferred to REP NOP, and deal with
1337 * MMX/SSE instructions where prefixes are used to select
1338 * between MMX and SSE register sets or outright opcode
1339 * selection.
1340 */
1341 if (works) {
1342 int i, nprefix;
1343 goodness = iflag_pfmask(*p);
1344 goodness = iflag_xor(&goodness, prefer);
1345 nprefix = 0;
1346 for (i = 0; i < MAXPREFIX; i++)
1347 if (tmp_ins.prefixes[i])
1348 nprefix++;
1349 if (nprefix < best_pref ||
1350 (nprefix == best_pref &&
1351 iflag_cmp(&goodness, &best) < 0)) {
1352 /* This is the best one found so far */
1353 best = goodness;
1354 best_p = p;
1355 best_pref = nprefix;
1356 best_length = length;
1357 ins = tmp_ins;
1358 }
1359 }
1360 }
1361 }
1362
1363 if (!best_p)
1364 return 0; /* no instruction was matched */
1365
1366 /* Pick the best match */
1367 p = best_p;
1368 length = best_length;
1369
1370 slen = 0;
1371
1372 /* TODO: snprintf returns the value that the string would have if
1373 * the buffer were long enough, and not the actual length of
1374 * the returned string, so each instance of using the return
1375 * value of snprintf should actually be checked to assure that
1376 * the return value is "sane." Maybe a macro wrapper could
1377 * be used for that purpose.
1378 */
1379 for (i = 0; i < MAXPREFIX; i++) {
1380 const char *prefix = prefix_name(ins.prefixes[i]);
1381 if (prefix)
1382 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1383 }
1384
1385 i = (*p)->opcode;
1386 if (i >= FIRST_COND_OPCODE)
1387 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1388 nasm_insn_names[i], condition_name[ins.condition]);
1389 else
1390 slen += snprintf(output + slen, outbufsize - slen, "%s",
1391 nasm_insn_names[i]);
1392
1393 colon = false;
1394 is_evex = !!(ins.rex & REX_EV);
1395 length += data - origdata; /* fix up for prefixes */
1396 for (i = 0; i < (*p)->operands; i++) {
1397 opflags_t t = (*p)->opd[i];
1398 decoflags_t deco = (*p)->deco[i];
1399 const operand *o = &ins.oprs[i];
1400 int64_t offs;
1401
1402 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1403
1404 offs = o->offset;
1405 if (o->segment & SEG_RELATIVE) {
1406 offs += offset + length;
1407 /*
1408 * sort out wraparound
1409 */
1410 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1411 offs &= 0xffff;
1412 else if (segsize != 64)
1413 offs &= 0xffffffff;
1414
1415 /*
1416 * add sync marker, if autosync is on
1417 */
1418 if (autosync)
1419 add_sync(offs, 0L);
1420 }
1421
1422 if (t & COLON)
1423 colon = true;
1424 else
1425 colon = false;
1426
1427 if ((t & (REGISTER | FPUREG)) ||
1428 (o->segment & SEG_RMREG)) {
1429 enum reg_enum reg;
1430 reg = whichreg(t, o->basereg, ins.rex);
1431 if (t & TO)
1432 slen += snprintf(output + slen, outbufsize - slen, "to ");
1433 slen += snprintf(output + slen, outbufsize - slen, "%s",
1434 nasm_reg_names[reg-EXPR_REG_START]);
1435 if (is_evex && deco)
1436 slen += append_evex_reg_deco(output + slen, outbufsize - slen,
1437 deco, ins.evex_p);
1438 } else if (!(UNITY & ~t)) {
1439 output[slen++] = '1';
1440 } else if (t & IMMEDIATE) {
1441 if (t & BITS8) {
1442 slen +=
1443 snprintf(output + slen, outbufsize - slen, "byte ");
1444 if (o->segment & SEG_SIGNED) {
1445 if (offs < 0) {
1446 offs *= -1;
1447 output[slen++] = '-';
1448 } else
1449 output[slen++] = '+';
1450 }
1451 } else if (t & BITS16) {
1452 slen +=
1453 snprintf(output + slen, outbufsize - slen, "word ");
1454 } else if (t & BITS32) {
1455 slen +=
1456 snprintf(output + slen, outbufsize - slen, "dword ");
1457 } else if (t & BITS64) {
1458 slen +=
1459 snprintf(output + slen, outbufsize - slen, "qword ");
1460 } else if (t & NEAR) {
1461 slen +=
1462 snprintf(output + slen, outbufsize - slen, "near ");
1463 } else if (t & SHORT) {
1464 slen +=
1465 snprintf(output + slen, outbufsize - slen, "short ");
1466 }
1467 slen +=
1468 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1469 offs);
1470 } else if (!(MEM_OFFS & ~t)) {
1471 slen +=
1472 snprintf(output + slen, outbufsize - slen,
1473 "[%s%s%s0x%"PRIx64"]",
1474 (segover ? segover : ""),
1475 (segover ? ":" : ""),
1476 (o->disp_size == 64 ? "qword " :
1477 o->disp_size == 32 ? "dword " :
1478 o->disp_size == 16 ? "word " : ""), offs);
1479 segover = NULL;
1480 } else if (is_class(REGMEM, t)) {
1481 int started = false;
1482 if (t & BITS8)
1483 slen +=
1484 snprintf(output + slen, outbufsize - slen, "byte ");
1485 if (t & BITS16)
1486 slen +=
1487 snprintf(output + slen, outbufsize - slen, "word ");
1488 if (t & BITS32)
1489 slen +=
1490 snprintf(output + slen, outbufsize - slen, "dword ");
1491 if (t & BITS64)
1492 slen +=
1493 snprintf(output + slen, outbufsize - slen, "qword ");
1494 if (t & BITS80)
1495 slen +=
1496 snprintf(output + slen, outbufsize - slen, "tword ");
1497 if ((ins.evex_p[2] & EVEX_P2B) && (deco & BRDCAST_MASK)) {
1498 /* when broadcasting, each element size should be used */
1499 if (deco & BR_BITS32)
1500 slen +=
1501 snprintf(output + slen, outbufsize - slen, "dword ");
1502 else if (deco & BR_BITS64)
1503 slen +=
1504 snprintf(output + slen, outbufsize - slen, "qword ");
1505 } else {
1506 if (t & BITS128)
1507 slen +=
1508 snprintf(output + slen, outbufsize - slen, "oword ");
1509 if (t & BITS256)
1510 slen +=
1511 snprintf(output + slen, outbufsize - slen, "yword ");
1512 if (t & BITS512)
1513 slen +=
1514 snprintf(output + slen, outbufsize - slen, "zword ");
1515 }
1516 if (t & FAR)
1517 slen += snprintf(output + slen, outbufsize - slen, "far ");
1518 if (t & NEAR)
1519 slen +=
1520 snprintf(output + slen, outbufsize - slen, "near ");
1521 output[slen++] = '[';
1522 if (o->disp_size)
1523 slen += snprintf(output + slen, outbufsize - slen, "%s",
1524 (o->disp_size == 64 ? "qword " :
1525 o->disp_size == 32 ? "dword " :
1526 o->disp_size == 16 ? "word " :
1527 ""));
1528 if (o->eaflags & EAF_REL)
1529 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1530 if (segover) {
1531 slen +=
1532 snprintf(output + slen, outbufsize - slen, "%s:",
1533 segover);
1534 segover = NULL;
1535 }
1536 if (o->basereg != -1) {
1537 slen += snprintf(output + slen, outbufsize - slen, "%s",
1538 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1539 started = true;
1540 }
1541 if (o->indexreg != -1 && !itemp_has(*best_p, IF_MIB)) {
1542 if (started)
1543 output[slen++] = '+';
1544 slen += snprintf(output + slen, outbufsize - slen, "%s",
1545 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1546 if (o->scale > 1)
1547 slen +=
1548 snprintf(output + slen, outbufsize - slen, "*%d",
1549 o->scale);
1550 started = true;
1551 }
1552
1553
1554 if (o->segment & SEG_DISP8) {
1555 if (is_evex) {
1556 const char *prefix;
1557 uint32_t offset = offs;
1558 if ((int32_t)offset < 0) {
1559 prefix = "-";
1560 offset = -offset;
1561 } else {
1562 prefix = "+";
1563 }
1564 slen +=
1565 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx32"",
1566 prefix, offset);
1567 } else {
1568 const char *prefix;
1569 uint8_t offset = offs;
1570 if ((int8_t)offset < 0) {
1571 prefix = "-";
1572 offset = -offset;
1573 } else {
1574 prefix = "+";
1575 }
1576 slen +=
1577 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1578 prefix, offset);
1579 }
1580 } else if (o->segment & SEG_DISP16) {
1581 const char *prefix;
1582 uint16_t offset = offs;
1583 if ((int16_t)offset < 0 && started) {
1584 offset = -offset;
1585 prefix = "-";
1586 } else {
1587 prefix = started ? "+" : "";
1588 }
1589 slen +=
1590 snprintf(output + slen, outbufsize - slen,
1591 "%s0x%"PRIx16"", prefix, offset);
1592 } else if (o->segment & SEG_DISP32) {
1593 if (prefix.asize == 64) {
1594 const char *prefix;
1595 uint64_t offset = (int64_t)(int32_t)offs;
1596 if ((int32_t)offs < 0 && started) {
1597 offset = -offset;
1598 prefix = "-";
1599 } else {
1600 prefix = started ? "+" : "";
1601 }
1602 slen +=
1603 snprintf(output + slen, outbufsize - slen,
1604 "%s0x%"PRIx64"", prefix, offset);
1605 } else {
1606 const char *prefix;
1607 uint32_t offset = offs;
1608 if ((int32_t) offset < 0 && started) {
1609 offset = -offset;
1610 prefix = "-";
1611 } else {
1612 prefix = started ? "+" : "";
1613 }
1614 slen +=
1615 snprintf(output + slen, outbufsize - slen,
1616 "%s0x%"PRIx32"", prefix, offset);
1617 }
1618 }
1619
1620 if (o->indexreg != -1 && itemp_has(*best_p, IF_MIB)) {
1621 output[slen++] = ',';
1622 slen += snprintf(output + slen, outbufsize - slen, "%s",
1623 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1624 if (o->scale > 1)
1625 slen +=
1626 snprintf(output + slen, outbufsize - slen, "*%d",
1627 o->scale);
1628 started = true;
1629 }
1630
1631 output[slen++] = ']';
1632
1633 if (is_evex && deco)
1634 slen += append_evex_mem_deco(output + slen, outbufsize - slen,
1635 t, deco, ins.evex_p);
1636 } else {
1637 slen +=
1638 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1639 i);
1640 }
1641 }
1642 output[slen] = '\0';
1643 if (segover) { /* unused segment override */
1644 char *p = output;
1645 int count = slen + 1;
1646 while (count--)
1647 p[count + 3] = p[count];
1648 strncpy(output, segover, 2);
1649 output[2] = ' ';
1650 }
1651 return length;
1652 }
1653
1654 /*
1655 * This is called when we don't have a complete instruction. If it
1656 * is a standalone *single-byte* prefix show it as such, otherwise
1657 * print it as a literal.
1658 */
1659 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1660 {
1661 uint8_t byte = *data;
1662 const char *str = NULL;
1663
1664 switch (byte) {
1665 case 0xF2:
1666 str = "repne";
1667 break;
1668 case 0xF3:
1669 str = "rep";
1670 break;
1671 case 0x9B:
1672 str = "wait";
1673 break;
1674 case 0xF0:
1675 str = "lock";
1676 break;
1677 case 0x2E:
1678 str = "cs";
1679 break;
1680 case 0x36:
1681 str = "ss";
1682 break;
1683 case 0x3E:
1684 str = "ds";
1685 break;
1686 case 0x26:
1687 str = "es";
1688 break;
1689 case 0x64:
1690 str = "fs";
1691 break;
1692 case 0x65:
1693 str = "gs";
1694 break;
1695 case 0x66:
1696 str = (segsize == 16) ? "o32" : "o16";
1697 break;
1698 case 0x67:
1699 str = (segsize == 32) ? "a16" : "a32";
1700 break;
1701 case REX_P + 0x0:
1702 case REX_P + 0x1:
1703 case REX_P + 0x2:
1704 case REX_P + 0x3:
1705 case REX_P + 0x4:
1706 case REX_P + 0x5:
1707 case REX_P + 0x6:
1708 case REX_P + 0x7:
1709 case REX_P + 0x8:
1710 case REX_P + 0x9:
1711 case REX_P + 0xA:
1712 case REX_P + 0xB:
1713 case REX_P + 0xC:
1714 case REX_P + 0xD:
1715 case REX_P + 0xE:
1716 case REX_P + 0xF:
1717 if (segsize == 64) {
1718 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1719 (byte == REX_P) ? "" : ".",
1720 (byte & REX_W) ? "w" : "",
1721 (byte & REX_R) ? "r" : "",
1722 (byte & REX_X) ? "x" : "",
1723 (byte & REX_B) ? "b" : "");
1724 break;
1725 }
1726 /* else fall through */
1727 default:
1728 snprintf(output, outbufsize, "db 0x%02x", byte);
1729 break;
1730 }
1731
1732 if (str)
1733 snprintf(output, outbufsize, "%s", str);
1734
1735 return 1;
1736 }
The Netwide Assembler