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disasm: Add ZMM vsib
[nasm.git] / disasm.c
blob49c3051a63acbfb2596627cbad5f0f288d02a7ce
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43 #include <inttypes.h>
44
45 #include "nasm.h"
46 #include "disasm.h"
47 #include "sync.h"
48 #include "insns.h"
49 #include "tables.h"
50 #include "regdis.h"
51
52 /*
53 * Flags that go into the `segment' field of `insn' structures
54 * during disassembly.
55 */
56 #define SEG_RELATIVE 1
57 #define SEG_32BIT 2
58 #define SEG_RMREG 4
59 #define SEG_DISP8 8
60 #define SEG_DISP16 16
61 #define SEG_DISP32 32
62 #define SEG_NODISP 64
63 #define SEG_SIGNED 128
64 #define SEG_64BIT 256
65
66 /*
67 * Prefix information
68 */
69 struct prefix_info {
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
81 uint8_t vex_v;
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
84 uint8_t evex[3]; /* EVEX prefix present */
85 };
86
87 #define getu8(x) (*(uint8_t *)(x))
88 #if X86_MEMORY
89 /* Littleendian CPU which can handle unaligned references */
90 #define getu16(x) (*(uint16_t *)(x))
91 #define getu32(x) (*(uint32_t *)(x))
92 #define getu64(x) (*(uint64_t *)(x))
93 #else
94 static uint16_t getu16(uint8_t *data)
95 {
96 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
97 }
98 static uint32_t getu32(uint8_t *data)
99 {
100 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
101 }
102 static uint64_t getu64(uint8_t *data)
103 {
104 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
105 }
106 #endif
107
108 #define gets8(x) ((int8_t)getu8(x))
109 #define gets16(x) ((int16_t)getu16(x))
110 #define gets32(x) ((int32_t)getu32(x))
111 #define gets64(x) ((int64_t)getu64(x))
112
113 /* Important: regval must already have been adjusted for rex extensions */
114 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
115 {
116 size_t i;
117
118 static const struct {
119 opflags_t flags;
120 enum reg_enum reg;
121 } specific_registers[] = {
122 {REG_AL, R_AL},
123 {REG_AX, R_AX},
124 {REG_EAX, R_EAX},
125 {REG_RAX, R_RAX},
126 {REG_DL, R_DL},
127 {REG_DX, R_DX},
128 {REG_EDX, R_EDX},
129 {REG_RDX, R_RDX},
130 {REG_CL, R_CL},
131 {REG_CX, R_CX},
132 {REG_ECX, R_ECX},
133 {REG_RCX, R_RCX},
134 {FPU0, R_ST0},
135 {XMM0, R_XMM0},
136 {YMM0, R_YMM0},
137 {ZMM0, R_ZMM0},
138 {REG_ES, R_ES},
139 {REG_CS, R_CS},
140 {REG_SS, R_SS},
141 {REG_DS, R_DS},
142 {REG_FS, R_FS},
143 {REG_GS, R_GS},
144 {OPMASK0, R_K0},
145 };
146
147 if (!(regflags & (REGISTER|REGMEM)))
148 return 0; /* Registers not permissible?! */
149
150 regflags |= REGISTER;
151
152 for (i = 0; i < ARRAY_SIZE(specific_registers); i++)
153 if (!(specific_registers[i].flags & ~regflags))
154 return specific_registers[i].reg;
155
156 /* All the entries below look up regval in an 16-entry array */
157 if (regval < 0 || regval > (rex & REX_EV ? 31 : 15))
158 return 0;
159
160 if (!(REG8 & ~regflags)) {
161 if (rex & (REX_P|REX_NH))
162 return nasm_rd_reg8_rex[regval];
163 else
164 return nasm_rd_reg8[regval];
165 }
166 if (!(REG16 & ~regflags))
167 return nasm_rd_reg16[regval];
168 if (!(REG32 & ~regflags))
169 return nasm_rd_reg32[regval];
170 if (!(REG64 & ~regflags))
171 return nasm_rd_reg64[regval];
172 if (!(REG_SREG & ~regflags))
173 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
174 if (!(REG_CREG & ~regflags))
175 return nasm_rd_creg[regval];
176 if (!(REG_DREG & ~regflags))
177 return nasm_rd_dreg[regval];
178 if (!(REG_TREG & ~regflags)) {
179 if (regval > 7)
180 return 0; /* TR registers are ill-defined with rex */
181 return nasm_rd_treg[regval];
182 }
183 if (!(FPUREG & ~regflags))
184 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
185 if (!(MMXREG & ~regflags))
186 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
187 if (!(XMMREG & ~regflags))
188 return nasm_rd_xmmreg[regval];
189 if (!(YMMREG & ~regflags))
190 return nasm_rd_ymmreg[regval];
191 if (!(ZMMREG & ~regflags))
192 return nasm_rd_zmmreg[regval];
193 if (!(OPMASKREG & ~regflags))
194 return nasm_rd_opmaskreg[regval];
195
196 return 0;
197 }
198
199 /*
200 * Find N value for compressed displacement (disp8 * N)
201 */
202 static uint8_t get_disp8N(insn *ins)
203 {
204 const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}},
205 {{16, 32, 64}, {8, 8, 8}}};
206 const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}};
207 const uint8_t dup_n[VLMAX] = {8, 32, 64};
208
209 bool evex_b = (ins->evex_p[2] & EVEX_P2B) >> 4;
210 enum ttypes tuple = ins->evex_tuple;
211 /* vex_wlp composed as [wwllpp] */
212 enum vectlens vectlen = (ins->evex_p[2] & EVEX_P2LL) >> 5;
213 /* wig(=2) is treated as w0(=0) */
214 bool evex_w = (ins->evex_p[1] & EVEX_P1W) >> 7;
215 uint8_t n = 0;
216
217 switch(tuple) {
218 case FV:
219 n = fv_n[evex_w][evex_b][vectlen];
220 break;
221 case HV:
222 n = hv_n[evex_b][vectlen];
223 break;
224
225 case FVM:
226 /* 16, 32, 64 for VL 128, 256, 512 respectively*/
227 n = 1 << (vectlen + 4);
228 break;
229 case T1S8: /* N = 1 */
230 case T1S16: /* N = 2 */
231 n = tuple - T1S8 + 1;
232 break;
233 case T1S:
234 /* N = 4 for 32bit, 8 for 64bit */
235 n = evex_w ? 8 : 4;
236 break;
237 case T1F32:
238 case T1F64:
239 /* N = 4 for 32bit, 8 for 64bit */
240 n = (tuple == T1F32 ? 4 : 8);
241 break;
242 case T2:
243 case T4:
244 case T8:
245 if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1))
246 n = 0;
247 else
248 n = 1 << (tuple - T2 + evex_w + 3);
249 break;
250 case HVM:
251 case QVM:
252 case OVM:
253 n = 1 << (OVM - tuple + vectlen + 1);
254 break;
255 case M128:
256 n = 16;
257 break;
258 case DUP:
259 n = dup_n[vectlen];
260 break;
261
262 default:
263 break;
264 }
265
266 return n;
267 }
268
269 /*
270 * Process an effective address (ModRM) specification.
271 */
272 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
273 int segsize, enum ea_type type,
274 operand *op, insn *ins)
275 {
276 int mod, rm, scale, index, base;
277 int rex;
278 uint8_t *evex;
279 uint8_t sib = 0;
280 bool is_evex = !!(ins->rex & REX_EV);
281
282 mod = (modrm >> 6) & 03;
283 rm = modrm & 07;
284
285 if (mod != 3 && asize != 16 && rm == 4)
286 sib = *data++;
287
288 rex = ins->rex;
289 evex = ins->evex_p;
290
291 if (mod == 3) { /* pure register version */
292 op->basereg = rm+(rex & REX_B ? 8 : 0);
293 op->segment |= SEG_RMREG;
294 if (is_evex && segsize == 64) {
295 op->basereg += (evex[0] & EVEX_P0X ? 0 : 16);
296 }
297 return data;
298 }
299
300 op->disp_size = 0;
301 op->eaflags = 0;
302
303 if (asize == 16) {
304 /*
305 * <mod> specifies the displacement size (none, byte or
306 * word), and <rm> specifies the register combination.
307 * Exception: mod=0,rm=6 does not specify [BP] as one might
308 * expect, but instead specifies [disp16].
309 */
310
311 if (type != EA_SCALAR)
312 return NULL;
313
314 op->indexreg = op->basereg = -1;
315 op->scale = 1; /* always, in 16 bits */
316 switch (rm) {
317 case 0:
318 op->basereg = R_BX;
319 op->indexreg = R_SI;
320 break;
321 case 1:
322 op->basereg = R_BX;
323 op->indexreg = R_DI;
324 break;
325 case 2:
326 op->basereg = R_BP;
327 op->indexreg = R_SI;
328 break;
329 case 3:
330 op->basereg = R_BP;
331 op->indexreg = R_DI;
332 break;
333 case 4:
334 op->basereg = R_SI;
335 break;
336 case 5:
337 op->basereg = R_DI;
338 break;
339 case 6:
340 op->basereg = R_BP;
341 break;
342 case 7:
343 op->basereg = R_BX;
344 break;
345 }
346 if (rm == 6 && mod == 0) { /* special case */
347 op->basereg = -1;
348 if (segsize != 16)
349 op->disp_size = 16;
350 mod = 2; /* fake disp16 */
351 }
352 switch (mod) {
353 case 0:
354 op->segment |= SEG_NODISP;
355 break;
356 case 1:
357 op->segment |= SEG_DISP8;
358 if (ins->evex_tuple != 0) {
359 op->offset = gets8(data) * get_disp8N(ins);
360 } else {
361 op->offset = gets8(data);
362 }
363 data++;
364 break;
365 case 2:
366 op->segment |= SEG_DISP16;
367 op->offset = *data++;
368 op->offset |= ((unsigned)*data++) << 8;
369 break;
370 }
371 return data;
372 } else {
373 /*
374 * Once again, <mod> specifies displacement size (this time
375 * none, byte or *dword*), while <rm> specifies the base
376 * register. Again, [EBP] is missing, replaced by a pure
377 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
378 * and RIP-relative addressing in 64-bit mode.
379 *
380 * However, rm=4
381 * indicates not a single base register, but instead the
382 * presence of a SIB byte...
383 */
384 int a64 = asize == 64;
385
386 op->indexreg = -1;
387
388 if (a64)
389 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
390 else
391 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
392
393 if (rm == 5 && mod == 0) {
394 if (segsize == 64) {
395 op->eaflags |= EAF_REL;
396 op->segment |= SEG_RELATIVE;
397 mod = 2; /* fake disp32 */
398 }
399
400 if (asize != 64)
401 op->disp_size = asize;
402
403 op->basereg = -1;
404 mod = 2; /* fake disp32 */
405 }
406
407
408 if (rm == 4) { /* process SIB */
409 uint8_t vsib_hi = 0;
410 scale = (sib >> 6) & 03;
411 index = (sib >> 3) & 07;
412 base = sib & 07;
413
414 op->scale = 1 << scale;
415
416 if (segsize == 64) {
417 vsib_hi = (rex & REX_X ? 8 : 0) |
418 (evex[2] & EVEX_P2VP ? 0 : 16);
419 }
420
421 if (type == EA_XMMVSIB)
422 op->indexreg = nasm_rd_xmmreg[index | vsib_hi];
423 else if (type == EA_YMMVSIB)
424 op->indexreg = nasm_rd_ymmreg[index | vsib_hi];
425 else if (type == EA_ZMMVSIB)
426 op->indexreg = nasm_rd_zmmreg[index | vsib_hi];
427 else if (index == 4 && !(rex & REX_X))
428 op->indexreg = -1; /* ESP/RSP cannot be an index */
429 else if (a64)
430 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
431 else
432 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
433
434 if (base == 5 && mod == 0) {
435 op->basereg = -1;
436 mod = 2; /* Fake disp32 */
437 } else if (a64)
438 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
439 else
440 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
441
442 if (segsize == 16)
443 op->disp_size = 32;
444 } else if (type != EA_SCALAR) {
445 /* Can't have VSIB without SIB */
446 return NULL;
447 }
448
449 switch (mod) {
450 case 0:
451 op->segment |= SEG_NODISP;
452 break;
453 case 1:
454 op->segment |= SEG_DISP8;
455 if (ins->evex_tuple != 0) {
456 op->offset = gets8(data) * get_disp8N(ins);
457 } else {
458 op->offset = gets8(data);
459 }
460 data++;
461 break;
462 case 2:
463 op->segment |= SEG_DISP32;
464 op->offset = gets32(data);
465 data += 4;
466 break;
467 }
468 return data;
469 }
470 }
471
472 /*
473 * Determine whether the instruction template in t corresponds to the data
474 * stream in data. Return the number of bytes matched if so.
475 */
476 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
477
478 static int matches(const struct itemplate *t, uint8_t *data,
479 const struct prefix_info *prefix, int segsize, insn *ins)
480 {
481 uint8_t *r = (uint8_t *)(t->code);
482 uint8_t *origdata = data;
483 bool a_used = false, o_used = false;
484 enum prefixes drep = 0;
485 enum prefixes dwait = 0;
486 uint8_t lock = prefix->lock;
487 int osize = prefix->osize;
488 int asize = prefix->asize;
489 int i, c;
490 int op1, op2;
491 struct operand *opx, *opy;
492 uint8_t opex = 0;
493 bool vex_ok = false;
494 int regmask = (segsize == 64) ? 15 : 7;
495 enum ea_type eat = EA_SCALAR;
496
497 for (i = 0; i < MAX_OPERANDS; i++) {
498 ins->oprs[i].segment = ins->oprs[i].disp_size =
499 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
500 }
501 ins->condition = -1;
502 ins->evex_tuple = 0;
503 ins->rex = prefix->rex;
504 memset(ins->prefixes, 0, sizeof ins->prefixes);
505
506 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
507 return false;
508
509 if (prefix->rep == 0xF2)
510 drep = (t->flags & IF_BND ? P_BND : P_REPNE);
511 else if (prefix->rep == 0xF3)
512 drep = P_REP;
513
514 dwait = prefix->wait ? P_WAIT : 0;
515
516 while ((c = *r++) != 0) {
517 op1 = (c & 3) + ((opex & 1) << 2);
518 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
519 opx = &ins->oprs[op1];
520 opy = &ins->oprs[op2];
521 opex = 0;
522
523 switch (c) {
524 case 01:
525 case 02:
526 case 03:
527 case 04:
528 while (c--)
529 if (*r++ != *data++)
530 return false;
531 break;
532
533 case 05:
534 case 06:
535 case 07:
536 opex = c;
537 break;
538
539 case4(010):
540 {
541 int t = *r++, d = *data++;
542 if (d < t || d > t + 7)
543 return false;
544 else {
545 opx->basereg = (d-t)+
546 (ins->rex & REX_B ? 8 : 0);
547 opx->segment |= SEG_RMREG;
548 }
549 break;
550 }
551
552 case4(0274):
553 opx->offset = (int8_t)*data++;
554 opx->segment |= SEG_SIGNED;
555 break;
556
557 case4(020):
558 opx->offset = *data++;
559 break;
560
561 case4(024):
562 opx->offset = *data++;
563 break;
564
565 case4(030):
566 opx->offset = getu16(data);
567 data += 2;
568 break;
569
570 case4(034):
571 if (osize == 32) {
572 opx->offset = getu32(data);
573 data += 4;
574 } else {
575 opx->offset = getu16(data);
576 data += 2;
577 }
578 if (segsize != asize)
579 opx->disp_size = asize;
580 break;
581
582 case4(040):
583 opx->offset = getu32(data);
584 data += 4;
585 break;
586
587 case4(0254):
588 opx->offset = gets32(data);
589 data += 4;
590 break;
591
592 case4(044):
593 switch (asize) {
594 case 16:
595 opx->offset = getu16(data);
596 data += 2;
597 if (segsize != 16)
598 opx->disp_size = 16;
599 break;
600 case 32:
601 opx->offset = getu32(data);
602 data += 4;
603 if (segsize == 16)
604 opx->disp_size = 32;
605 break;
606 case 64:
607 opx->offset = getu64(data);
608 opx->disp_size = 64;
609 data += 8;
610 break;
611 }
612 break;
613
614 case4(050):
615 opx->offset = gets8(data++);
616 opx->segment |= SEG_RELATIVE;
617 break;
618
619 case4(054):
620 opx->offset = getu64(data);
621 data += 8;
622 break;
623
624 case4(060):
625 opx->offset = gets16(data);
626 data += 2;
627 opx->segment |= SEG_RELATIVE;
628 opx->segment &= ~SEG_32BIT;
629 break;
630
631 case4(064): /* rel */
632 opx->segment |= SEG_RELATIVE;
633 /* In long mode rel is always 32 bits, sign extended. */
634 if (segsize == 64 || osize == 32) {
635 opx->offset = gets32(data);
636 data += 4;
637 if (segsize != 64)
638 opx->segment |= SEG_32BIT;
639 opx->type = (opx->type & ~SIZE_MASK)
640 | (segsize == 64 ? BITS64 : BITS32);
641 } else {
642 opx->offset = gets16(data);
643 data += 2;
644 opx->segment &= ~SEG_32BIT;
645 opx->type = (opx->type & ~SIZE_MASK) | BITS16;
646 }
647 break;
648
649 case4(070):
650 opx->offset = gets32(data);
651 data += 4;
652 opx->segment |= SEG_32BIT | SEG_RELATIVE;
653 break;
654
655 case4(0100):
656 case4(0110):
657 case4(0120):
658 case4(0130):
659 {
660 int modrm = *data++;
661 opx->segment |= SEG_RMREG;
662 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
663 if (!data)
664 return false;
665 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
666 if ((ins->rex & REX_EV) && (segsize == 64))
667 opx->basereg += (ins->evex_p[0] & EVEX_P0RP ? 0 : 16);
668 break;
669 }
670
671 case 0172:
672 {
673 uint8_t ximm = *data++;
674 c = *r++;
675 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
676 ins->oprs[c >> 3].segment |= SEG_RMREG;
677 ins->oprs[c & 7].offset = ximm & 15;
678 }
679 break;
680
681 case 0173:
682 {
683 uint8_t ximm = *data++;
684 c = *r++;
685
686 if ((c ^ ximm) & 15)
687 return false;
688
689 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
690 ins->oprs[c >> 4].segment |= SEG_RMREG;
691 }
692 break;
693
694 case4(0174):
695 {
696 uint8_t ximm = *data++;
697
698 opx->basereg = (ximm >> 4) & regmask;
699 opx->segment |= SEG_RMREG;
700 }
701 break;
702
703 case4(0200):
704 case4(0204):
705 case4(0210):
706 case4(0214):
707 case4(0220):
708 case4(0224):
709 case4(0230):
710 case4(0234):
711 {
712 int modrm = *data++;
713 if (((modrm >> 3) & 07) != (c & 07))
714 return false; /* spare field doesn't match up */
715 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
716 if (!data)
717 return false;
718 break;
719 }
720
721 case4(0240):
722 case 0250:
723 {
724 uint8_t evexm = *r++;
725 uint8_t evexwlp = *r++;
726 ins->evex_tuple = *r++ - 0300;
727
728 ins->rex |= REX_EV;
729 if ((prefix->rex & (REX_EV|REX_V|REX_P)) != REX_EV)
730 return false;
731
732 if ((evexm & 0x1f) != prefix->vex_m)
733 return false;
734
735 switch (evexwlp & 060) {
736 case 000:
737 if (prefix->rex & REX_W)
738 return false;
739 break;
740 case 020:
741 if (!(prefix->rex & REX_W))
742 return false;
743 ins->rex |= REX_W;
744 break;
745 case 040: /* VEX.W is a don't care */
746 ins->rex &= ~REX_W;
747 break;
748 case 060:
749 break;
750 }
751
752 /* If EVEX.b is set, EVEX.L'L can be rounding control bits */
753 if ((evexwlp ^ prefix->vex_lp) &
754 ((prefix->evex[2] & EVEX_P2B) ? 0x03 : 0x0f))
755 return false;
756
757 if (c == 0250) {
758 if ((prefix->vex_v != 0) ||
759 (!(prefix->evex[2] & EVEX_P2VP) &&
760 ((eat < EA_XMMVSIB) || (eat > EA_ZMMVSIB))))
761 return false;
762 } else {
763 opx->segment |= SEG_RMREG;
764 opx->basereg = ((~prefix->evex[2] & EVEX_P2VP) << (4 - 3) ) |
765 prefix->vex_v;
766 }
767 vex_ok = true;
768 memcpy(ins->evex_p, prefix->evex, 3);
769 break;
770 }
771
772 case4(0260):
773 case 0270:
774 {
775 int vexm = *r++;
776 int vexwlp = *r++;
777
778 ins->rex |= REX_V;
779 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
780 return false;
781
782 if ((vexm & 0x1f) != prefix->vex_m)
783 return false;
784
785 switch (vexwlp & 060) {
786 case 000:
787 if (prefix->rex & REX_W)
788 return false;
789 break;
790 case 020:
791 if (!(prefix->rex & REX_W))
792 return false;
793 ins->rex &= ~REX_W;
794 break;
795 case 040: /* VEX.W is a don't care */
796 ins->rex &= ~REX_W;
797 break;
798 case 060:
799 break;
800 }
801
802 /* The 010 bit of vexwlp is set if VEX.L is ignored */
803 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
804 return false;
805
806 if (c == 0270) {
807 if (prefix->vex_v != 0)
808 return false;
809 } else {
810 opx->segment |= SEG_RMREG;
811 opx->basereg = prefix->vex_v;
812 }
813 vex_ok = true;
814 break;
815 }
816
817 case 0271:
818 if (prefix->rep == 0xF3)
819 drep = P_XRELEASE;
820 break;
821
822 case 0272:
823 if (prefix->rep == 0xF2)
824 drep = P_XACQUIRE;
825 else if (prefix->rep == 0xF3)
826 drep = P_XRELEASE;
827 break;
828
829 case 0273:
830 if (prefix->lock == 0xF0) {
831 if (prefix->rep == 0xF2)
832 drep = P_XACQUIRE;
833 else if (prefix->rep == 0xF3)
834 drep = P_XRELEASE;
835 }
836 break;
837
838 case 0310:
839 if (asize != 16)
840 return false;
841 else
842 a_used = true;
843 break;
844
845 case 0311:
846 if (asize != 32)
847 return false;
848 else
849 a_used = true;
850 break;
851
852 case 0312:
853 if (asize != segsize)
854 return false;
855 else
856 a_used = true;
857 break;
858
859 case 0313:
860 if (asize != 64)
861 return false;
862 else
863 a_used = true;
864 break;
865
866 case 0314:
867 if (prefix->rex & REX_B)
868 return false;
869 break;
870
871 case 0315:
872 if (prefix->rex & REX_X)
873 return false;
874 break;
875
876 case 0316:
877 if (prefix->rex & REX_R)
878 return false;
879 break;
880
881 case 0317:
882 if (prefix->rex & REX_W)
883 return false;
884 break;
885
886 case 0320:
887 if (osize != 16)
888 return false;
889 else
890 o_used = true;
891 break;
892
893 case 0321:
894 if (osize != 32)
895 return false;
896 else
897 o_used = true;
898 break;
899
900 case 0322:
901 if (osize != (segsize == 16) ? 16 : 32)
902 return false;
903 else
904 o_used = true;
905 break;
906
907 case 0323:
908 ins->rex |= REX_W; /* 64-bit only instruction */
909 osize = 64;
910 o_used = true;
911 break;
912
913 case 0324:
914 if (osize != 64)
915 return false;
916 o_used = true;
917 break;
918
919 case 0325:
920 ins->rex |= REX_NH;
921 break;
922
923 case 0330:
924 {
925 int t = *r++, d = *data++;
926 if (d < t || d > t + 15)
927 return false;
928 else
929 ins->condition = d - t;
930 break;
931 }
932
933 case 0326:
934 if (prefix->rep == 0xF3)
935 return false;
936 break;
937
938 case 0331:
939 if (prefix->rep)
940 return false;
941 break;
942
943 case 0332:
944 if (prefix->rep != 0xF2)
945 return false;
946 drep = 0;
947 break;
948
949 case 0333:
950 if (prefix->rep != 0xF3)
951 return false;
952 drep = 0;
953 break;
954
955 case 0334:
956 if (lock) {
957 ins->rex |= REX_R;
958 lock = 0;
959 }
960 break;
961
962 case 0335:
963 if (drep == P_REP)
964 drep = P_REPE;
965 break;
966
967 case 0336:
968 case 0337:
969 break;
970
971 case 0340:
972 return false;
973
974 case 0341:
975 if (prefix->wait != 0x9B)
976 return false;
977 dwait = 0;
978 break;
979
980 case 0360:
981 if (prefix->osp || prefix->rep)
982 return false;
983 break;
984
985 case 0361:
986 if (!prefix->osp || prefix->rep)
987 return false;
988 o_used = true;
989 break;
990
991 case 0364:
992 if (prefix->osp)
993 return false;
994 break;
995
996 case 0365:
997 if (prefix->asp)
998 return false;
999 break;
1000
1001 case 0366:
1002 if (!prefix->osp)
1003 return false;
1004 o_used = true;
1005 break;
1006
1007 case 0367:
1008 if (!prefix->asp)
1009 return false;
1010 a_used = true;
1011 break;
1012
1013 case 0370:
1014 case 0371:
1015 break;
1016
1017 case 0374:
1018 eat = EA_XMMVSIB;
1019 break;
1020
1021 case 0375:
1022 eat = EA_YMMVSIB;
1023 break;
1024
1025 case 0376:
1026 eat = EA_ZMMVSIB;
1027 break;
1028
1029 default:
1030 return false; /* Unknown code */
1031 }
1032 }
1033
1034 if (!vex_ok && (ins->rex & (REX_V | REX_EV)))
1035 return false;
1036
1037 /* REX cannot be combined with VEX */
1038 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
1039 return false;
1040
1041 /*
1042 * Check for unused rep or a/o prefixes.
1043 */
1044 for (i = 0; i < t->operands; i++) {
1045 if (ins->oprs[i].segment != SEG_RMREG)
1046 a_used = true;
1047 }
1048
1049 if (lock) {
1050 if (ins->prefixes[PPS_LOCK])
1051 return false;
1052 ins->prefixes[PPS_LOCK] = P_LOCK;
1053 }
1054 if (drep) {
1055 if (ins->prefixes[PPS_REP])
1056 return false;
1057 ins->prefixes[PPS_REP] = drep;
1058 }
1059 ins->prefixes[PPS_WAIT] = dwait;
1060 if (!o_used) {
1061 if (osize != ((segsize == 16) ? 16 : 32)) {
1062 enum prefixes pfx = 0;
1063
1064 switch (osize) {
1065 case 16:
1066 pfx = P_O16;
1067 break;
1068 case 32:
1069 pfx = P_O32;
1070 break;
1071 case 64:
1072 pfx = P_O64;
1073 break;
1074 }
1075
1076 if (ins->prefixes[PPS_OSIZE])
1077 return false;
1078 ins->prefixes[PPS_OSIZE] = pfx;
1079 }
1080 }
1081 if (!a_used && asize != segsize) {
1082 if (ins->prefixes[PPS_ASIZE])
1083 return false;
1084 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
1085 }
1086
1087 /* Fix: check for redundant REX prefixes */
1088
1089 return data - origdata;
1090 }
1091
1092 /* Condition names for disassembly, sorted by x86 code */
1093 static const char * const condition_name[16] = {
1094 "o", "no", "c", "nc", "z", "nz", "na", "a",
1095 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
1096 };
1097
1098 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
1099 int32_t offset, int autosync, iflags_t prefer)
1100 {
1101 const struct itemplate * const *p, * const *best_p;
1102 const struct disasm_index *ix;
1103 uint8_t *dp;
1104 int length, best_length = 0;
1105 char *segover;
1106 int i, slen, colon, n;
1107 uint8_t *origdata;
1108 int works;
1109 insn tmp_ins, ins;
1110 iflags_t goodness, best, flags;
1111 int best_pref;
1112 struct prefix_info prefix;
1113 bool end_prefix;
1114 bool is_evex;
1115
1116 memset(&ins, 0, sizeof ins);
1117
1118 /*
1119 * Scan for prefixes.
1120 */
1121 memset(&prefix, 0, sizeof prefix);
1122 prefix.asize = segsize;
1123 prefix.osize = (segsize == 64) ? 32 : segsize;
1124 segover = NULL;
1125 origdata = data;
1126
1127 ix = itable;
1128
1129 end_prefix = false;
1130 while (!end_prefix) {
1131 switch (*data) {
1132 case 0xF2:
1133 case 0xF3:
1134 prefix.rep = *data++;
1135 break;
1136
1137 case 0x9B:
1138 prefix.wait = *data++;
1139 break;
1140
1141 case 0xF0:
1142 prefix.lock = *data++;
1143 break;
1144
1145 case 0x2E:
1146 segover = "cs", prefix.seg = *data++;
1147 break;
1148 case 0x36:
1149 segover = "ss", prefix.seg = *data++;
1150 break;
1151 case 0x3E:
1152 segover = "ds", prefix.seg = *data++;
1153 break;
1154 case 0x26:
1155 segover = "es", prefix.seg = *data++;
1156 break;
1157 case 0x64:
1158 segover = "fs", prefix.seg = *data++;
1159 break;
1160 case 0x65:
1161 segover = "gs", prefix.seg = *data++;
1162 break;
1163
1164 case 0x66:
1165 prefix.osize = (segsize == 16) ? 32 : 16;
1166 prefix.osp = *data++;
1167 break;
1168 case 0x67:
1169 prefix.asize = (segsize == 32) ? 16 : 32;
1170 prefix.asp = *data++;
1171 break;
1172
1173 case 0xC4:
1174 case 0xC5:
1175 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1176 prefix.vex[0] = *data++;
1177 prefix.vex[1] = *data++;
1178
1179 prefix.rex = REX_V;
1180 prefix.vex_c = RV_VEX;
1181
1182 if (prefix.vex[0] == 0xc4) {
1183 prefix.vex[2] = *data++;
1184 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1185 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1186 prefix.vex_m = prefix.vex[1] & 0x1f;
1187 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1188 prefix.vex_lp = prefix.vex[2] & 7;
1189 } else {
1190 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1191 prefix.vex_m = 1;
1192 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1193 prefix.vex_lp = prefix.vex[1] & 7;
1194 }
1195
1196 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1197 }
1198 end_prefix = true;
1199 break;
1200
1201 case 0x62:
1202 {
1203 uint8_t evex_p0 = data[1] & 0x0f;
1204 if (segsize == 64 ||
1205 ((evex_p0 >= 0x01) && (evex_p0 <= 0x03))) {
1206 data++; /* 62h EVEX prefix */
1207 prefix.evex[0] = *data++;
1208 prefix.evex[1] = *data++;
1209 prefix.evex[2] = *data++;
1210
1211 prefix.rex = REX_EV;
1212 prefix.vex_c = RV_EVEX;
1213 prefix.rex |= (~prefix.evex[0] >> 5) & 7; /* REX_RXB */
1214 prefix.rex |= (prefix.evex[1] >> (7-3)) & REX_W;
1215 prefix.vex_m = prefix.evex[0] & EVEX_P0MM;
1216 prefix.vex_v = (~prefix.evex[1] & EVEX_P1VVVV) >> 3;
1217 prefix.vex_lp = ((prefix.evex[2] & EVEX_P2LL) >> (5-2)) |
1218 (prefix.evex[1] & EVEX_P1PP);
1219
1220 ix = itable_vex[prefix.vex_c][prefix.vex_m][prefix.vex_lp & 3];
1221 }
1222 end_prefix = true;
1223 break;
1224 }
1225
1226 case 0x8F:
1227 if ((data[1] & 030) != 0 &&
1228 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1229 prefix.vex[0] = *data++;
1230 prefix.vex[1] = *data++;
1231 prefix.vex[2] = *data++;
1232
1233 prefix.rex = REX_V;
1234 prefix.vex_c = RV_XOP;
1235
1236 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1237 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1238 prefix.vex_m = prefix.vex[1] & 0x1f;
1239 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1240 prefix.vex_lp = prefix.vex[2] & 7;
1241
1242 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1243 }
1244 end_prefix = true;
1245 break;
1246
1247 case REX_P + 0x0:
1248 case REX_P + 0x1:
1249 case REX_P + 0x2:
1250 case REX_P + 0x3:
1251 case REX_P + 0x4:
1252 case REX_P + 0x5:
1253 case REX_P + 0x6:
1254 case REX_P + 0x7:
1255 case REX_P + 0x8:
1256 case REX_P + 0x9:
1257 case REX_P + 0xA:
1258 case REX_P + 0xB:
1259 case REX_P + 0xC:
1260 case REX_P + 0xD:
1261 case REX_P + 0xE:
1262 case REX_P + 0xF:
1263 if (segsize == 64) {
1264 prefix.rex = *data++;
1265 if (prefix.rex & REX_W)
1266 prefix.osize = 64;
1267 }
1268 end_prefix = true;
1269 break;
1270
1271 default:
1272 end_prefix = true;
1273 break;
1274 }
1275 }
1276
1277 best = -1; /* Worst possible */
1278 best_p = NULL;
1279 best_pref = INT_MAX;
1280
1281 if (!ix)
1282 return 0; /* No instruction table at all... */
1283
1284 dp = data;
1285 ix += *dp++;
1286 while (ix->n == -1) {
1287 ix = (const struct disasm_index *)ix->p + *dp++;
1288 }
1289
1290 p = (const struct itemplate * const *)ix->p;
1291 for (n = ix->n; n; n--, p++) {
1292 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1293 works = true;
1294 /*
1295 * Final check to make sure the types of r/m match up.
1296 * XXX: Need to make sure this is actually correct.
1297 */
1298 for (i = 0; i < (*p)->operands; i++) {
1299 if (
1300 /* If it's a mem-only EA but we have a
1301 register, die. */
1302 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1303 is_class(MEMORY, (*p)->opd[i])) ||
1304 /* If it's a reg-only EA but we have a memory
1305 ref, die. */
1306 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1307 !(REG_EA & ~(*p)->opd[i]) &&
1308 !((*p)->opd[i] & REG_SMASK)) ||
1309 /* Register type mismatch (eg FS vs REG_DESS):
1310 die. */
1311 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1312 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1313 !whichreg((*p)->opd[i],
1314 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1315 ) {
1316 works = false;
1317 break;
1318 }
1319 }
1320
1321 /*
1322 * Note: we always prefer instructions which incorporate
1323 * prefixes in the instructions themselves. This is to allow
1324 * e.g. PAUSE to be preferred to REP NOP, and deal with
1325 * MMX/SSE instructions where prefixes are used to select
1326 * between MMX and SSE register sets or outright opcode
1327 * selection.
1328 */
1329 if (works) {
1330 int i, nprefix;
1331 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1332 nprefix = 0;
1333 for (i = 0; i < MAXPREFIX; i++)
1334 if (tmp_ins.prefixes[i])
1335 nprefix++;
1336 if (nprefix < best_pref ||
1337 (nprefix == best_pref && goodness < best)) {
1338 /* This is the best one found so far */
1339 best = goodness;
1340 best_p = p;
1341 best_pref = nprefix;
1342 best_length = length;
1343 ins = tmp_ins;
1344 }
1345 }
1346 }
1347 }
1348
1349 if (!best_p)
1350 return 0; /* no instruction was matched */
1351
1352 /* Pick the best match */
1353 p = best_p;
1354 length = best_length;
1355 flags = (*p)->flags;
1356
1357 slen = 0;
1358
1359 /* TODO: snprintf returns the value that the string would have if
1360 * the buffer were long enough, and not the actual length of
1361 * the returned string, so each instance of using the return
1362 * value of snprintf should actually be checked to assure that
1363 * the return value is "sane." Maybe a macro wrapper could
1364 * be used for that purpose.
1365 */
1366 for (i = 0; i < MAXPREFIX; i++) {
1367 const char *prefix = prefix_name(ins.prefixes[i]);
1368 if (prefix)
1369 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1370 }
1371
1372 i = (*p)->opcode;
1373 if (i >= FIRST_COND_OPCODE)
1374 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1375 nasm_insn_names[i], condition_name[ins.condition]);
1376 else
1377 slen += snprintf(output + slen, outbufsize - slen, "%s",
1378 nasm_insn_names[i]);
1379
1380 colon = false;
1381 is_evex = !!(ins.rex & REX_EV);
1382 length += data - origdata; /* fix up for prefixes */
1383 for (i = 0; i < (*p)->operands; i++) {
1384 opflags_t t = (*p)->opd[i];
1385 const operand *o = &ins.oprs[i];
1386 int64_t offs;
1387
1388 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1389
1390 offs = o->offset;
1391 if (o->segment & SEG_RELATIVE) {
1392 offs += offset + length;
1393 /*
1394 * sort out wraparound
1395 */
1396 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1397 offs &= 0xffff;
1398 else if (segsize != 64)
1399 offs &= 0xffffffff;
1400
1401 /*
1402 * add sync marker, if autosync is on
1403 */
1404 if (autosync)
1405 add_sync(offs, 0L);
1406 }
1407
1408 if (t & COLON)
1409 colon = true;
1410 else
1411 colon = false;
1412
1413 if ((t & (REGISTER | FPUREG)) ||
1414 (o->segment & SEG_RMREG)) {
1415 enum reg_enum reg;
1416 reg = whichreg(t, o->basereg, ins.rex);
1417 if (t & TO)
1418 slen += snprintf(output + slen, outbufsize - slen, "to ");
1419 slen += snprintf(output + slen, outbufsize - slen, "%s",
1420 nasm_reg_names[reg-EXPR_REG_START]);
1421 } else if (!(UNITY & ~t)) {
1422 output[slen++] = '1';
1423 } else if (t & IMMEDIATE) {
1424 if (t & BITS8) {
1425 slen +=
1426 snprintf(output + slen, outbufsize - slen, "byte ");
1427 if (o->segment & SEG_SIGNED) {
1428 if (offs < 0) {
1429 offs *= -1;
1430 output[slen++] = '-';
1431 } else
1432 output[slen++] = '+';
1433 }
1434 } else if (t & BITS16) {
1435 slen +=
1436 snprintf(output + slen, outbufsize - slen, "word ");
1437 } else if (t & BITS32) {
1438 slen +=
1439 snprintf(output + slen, outbufsize - slen, "dword ");
1440 } else if (t & BITS64) {
1441 slen +=
1442 snprintf(output + slen, outbufsize - slen, "qword ");
1443 } else if (t & NEAR) {
1444 slen +=
1445 snprintf(output + slen, outbufsize - slen, "near ");
1446 } else if (t & SHORT) {
1447 slen +=
1448 snprintf(output + slen, outbufsize - slen, "short ");
1449 }
1450 slen +=
1451 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1452 offs);
1453 } else if (!(MEM_OFFS & ~t)) {
1454 slen +=
1455 snprintf(output + slen, outbufsize - slen,
1456 "[%s%s%s0x%"PRIx64"]",
1457 (segover ? segover : ""),
1458 (segover ? ":" : ""),
1459 (o->disp_size == 64 ? "qword " :
1460 o->disp_size == 32 ? "dword " :
1461 o->disp_size == 16 ? "word " : ""), offs);
1462 segover = NULL;
1463 } else if (is_class(REGMEM, t)) {
1464 int started = false;
1465 if (t & BITS8)
1466 slen +=
1467 snprintf(output + slen, outbufsize - slen, "byte ");
1468 if (t & BITS16)
1469 slen +=
1470 snprintf(output + slen, outbufsize - slen, "word ");
1471 if (t & BITS32)
1472 slen +=
1473 snprintf(output + slen, outbufsize - slen, "dword ");
1474 if (t & BITS64)
1475 slen +=
1476 snprintf(output + slen, outbufsize - slen, "qword ");
1477 if (t & BITS80)
1478 slen +=
1479 snprintf(output + slen, outbufsize - slen, "tword ");
1480 if (t & BITS128)
1481 slen +=
1482 snprintf(output + slen, outbufsize - slen, "oword ");
1483 if (t & BITS256)
1484 slen +=
1485 snprintf(output + slen, outbufsize - slen, "yword ");
1486 if (t & BITS512)
1487 slen +=
1488 snprintf(output + slen, outbufsize - slen, "zword ");
1489 if (t & FAR)
1490 slen += snprintf(output + slen, outbufsize - slen, "far ");
1491 if (t & NEAR)
1492 slen +=
1493 snprintf(output + slen, outbufsize - slen, "near ");
1494 output[slen++] = '[';
1495 if (o->disp_size)
1496 slen += snprintf(output + slen, outbufsize - slen, "%s",
1497 (o->disp_size == 64 ? "qword " :
1498 o->disp_size == 32 ? "dword " :
1499 o->disp_size == 16 ? "word " :
1500 ""));
1501 if (o->eaflags & EAF_REL)
1502 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1503 if (segover) {
1504 slen +=
1505 snprintf(output + slen, outbufsize - slen, "%s:",
1506 segover);
1507 segover = NULL;
1508 }
1509 if (o->basereg != -1) {
1510 slen += snprintf(output + slen, outbufsize - slen, "%s",
1511 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1512 started = true;
1513 }
1514 if (o->indexreg != -1 && !(flags & IF_MIB)) {
1515 if (started)
1516 output[slen++] = '+';
1517 slen += snprintf(output + slen, outbufsize - slen, "%s",
1518 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1519 if (o->scale > 1)
1520 slen +=
1521 snprintf(output + slen, outbufsize - slen, "*%d",
1522 o->scale);
1523 started = true;
1524 }
1525
1526
1527 if (o->segment & SEG_DISP8) {
1528 if (is_evex) {
1529 const char *prefix;
1530 uint32_t offset = offs;
1531 if ((int32_t)offset < 0) {
1532 prefix = "-";
1533 offset = -offset;
1534 } else {
1535 prefix = "+";
1536 }
1537 slen +=
1538 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx32"",
1539 prefix, offset);
1540 } else {
1541 const char *prefix;
1542 uint8_t offset = offs;
1543 if ((int8_t)offset < 0) {
1544 prefix = "-";
1545 offset = -offset;
1546 } else {
1547 prefix = "+";
1548 }
1549 slen +=
1550 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1551 prefix, offset);
1552 }
1553 } else if (o->segment & SEG_DISP16) {
1554 const char *prefix;
1555 uint16_t offset = offs;
1556 if ((int16_t)offset < 0 && started) {
1557 offset = -offset;
1558 prefix = "-";
1559 } else {
1560 prefix = started ? "+" : "";
1561 }
1562 slen +=
1563 snprintf(output + slen, outbufsize - slen,
1564 "%s0x%"PRIx16"", prefix, offset);
1565 } else if (o->segment & SEG_DISP32) {
1566 if (prefix.asize == 64) {
1567 const char *prefix;
1568 uint64_t offset = (int64_t)(int32_t)offs;
1569 if ((int32_t)offs < 0 && started) {
1570 offset = -offset;
1571 prefix = "-";
1572 } else {
1573 prefix = started ? "+" : "";
1574 }
1575 slen +=
1576 snprintf(output + slen, outbufsize - slen,
1577 "%s0x%"PRIx64"", prefix, offset);
1578 } else {
1579 const char *prefix;
1580 uint32_t offset = offs;
1581 if ((int32_t) offset < 0 && started) {
1582 offset = -offset;
1583 prefix = "-";
1584 } else {
1585 prefix = started ? "+" : "";
1586 }
1587 slen +=
1588 snprintf(output + slen, outbufsize - slen,
1589 "%s0x%"PRIx32"", prefix, offset);
1590 }
1591 }
1592
1593 if (o->indexreg != -1 && (flags & IF_MIB)) {
1594 output[slen++] = ',';
1595 slen += snprintf(output + slen, outbufsize - slen, "%s",
1596 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1597 if (o->scale > 1)
1598 slen +=
1599 snprintf(output + slen, outbufsize - slen, "*%d",
1600 o->scale);
1601 started = true;
1602 }
1603
1604 output[slen++] = ']';
1605 } else {
1606 slen +=
1607 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1608 i);
1609 }
1610 }
1611 output[slen] = '\0';
1612 if (segover) { /* unused segment override */
1613 char *p = output;
1614 int count = slen + 1;
1615 while (count--)
1616 p[count + 3] = p[count];
1617 strncpy(output, segover, 2);
1618 output[2] = ' ';
1619 }
1620 return length;
1621 }
1622
1623 /*
1624 * This is called when we don't have a complete instruction. If it
1625 * is a standalone *single-byte* prefix show it as such, otherwise
1626 * print it as a literal.
1627 */
1628 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1629 {
1630 uint8_t byte = *data;
1631 const char *str = NULL;
1632
1633 switch (byte) {
1634 case 0xF2:
1635 str = "repne";
1636 break;
1637 case 0xF3:
1638 str = "rep";
1639 break;
1640 case 0x9B:
1641 str = "wait";
1642 break;
1643 case 0xF0:
1644 str = "lock";
1645 break;
1646 case 0x2E:
1647 str = "cs";
1648 break;
1649 case 0x36:
1650 str = "ss";
1651 break;
1652 case 0x3E:
1653 str = "ss";
1654 break;
1655 case 0x26:
1656 str = "es";
1657 break;
1658 case 0x64:
1659 str = "fs";
1660 break;
1661 case 0x65:
1662 str = "gs";
1663 break;
1664 case 0x66:
1665 str = (segsize == 16) ? "o32" : "o16";
1666 break;
1667 case 0x67:
1668 str = (segsize == 32) ? "a16" : "a32";
1669 break;
1670 case REX_P + 0x0:
1671 case REX_P + 0x1:
1672 case REX_P + 0x2:
1673 case REX_P + 0x3:
1674 case REX_P + 0x4:
1675 case REX_P + 0x5:
1676 case REX_P + 0x6:
1677 case REX_P + 0x7:
1678 case REX_P + 0x8:
1679 case REX_P + 0x9:
1680 case REX_P + 0xA:
1681 case REX_P + 0xB:
1682 case REX_P + 0xC:
1683 case REX_P + 0xD:
1684 case REX_P + 0xE:
1685 case REX_P + 0xF:
1686 if (segsize == 64) {
1687 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1688 (byte == REX_P) ? "" : ".",
1689 (byte & REX_W) ? "w" : "",
1690 (byte & REX_R) ? "r" : "",
1691 (byte & REX_X) ? "x" : "",
1692 (byte & REX_B) ? "b" : "");
1693 break;
1694 }
1695 /* else fall through */
1696 default:
1697 snprintf(output, outbufsize, "db 0x%02x", byte);
1698 break;
1699 }
1700
1701 if (str)
1702 snprintf(output, outbufsize, "%s", str);
1703
1704 return 1;
1705 }
The Netwide Assembler