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disp8: Consolidate a logic to get compressed displacement
[nasm.git] / assemble.c
bloba09b9643efe8b74b36ee9984f7ccf45e9f4df0fa
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
71 *
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
78 * cc 000 0mm
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
80 * and wlp is:
81 * 00 wwl lpp
82 * [l0] ll = 0 (.128, .lz)
83 * [l1] ll = 1 (.256)
84 * [l2] ll = 2 (.512)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
86 *
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
91 *
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
94 * [f3] pp = 2
95 * [f2] pp = 3
96 *
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
99 *
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
105 *
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
108 * 00 wwl lpp
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
112 *
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
117 *
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
119 *
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
170 */
171
172 #include "compiler.h"
173
174 #include <stdio.h>
175 #include <string.h>
176 #include <inttypes.h>
177
178 #include "nasm.h"
179 #include "nasmlib.h"
180 #include "assemble.h"
181 #include "insns.h"
182 #include "tables.h"
183 #include "disp8.h"
184
185 enum match_result {
186 /*
187 * Matching errors. These should be sorted so that more specific
188 * errors come later in the sequence.
189 */
190 MERR_INVALOP,
191 MERR_OPSIZEMISSING,
192 MERR_OPSIZEMISMATCH,
193 MERR_BRNUMMISMATCH,
194 MERR_BADCPU,
195 MERR_BADMODE,
196 MERR_BADHLE,
197 MERR_ENCMISMATCH,
198 MERR_BADBND,
199 /*
200 * Matching success; the conditional ones first
201 */
202 MOK_JUMP, /* Matching OK but needs jmp_match() */
203 MOK_GOOD /* Matching unconditionally OK */
204 };
205
206 typedef struct {
207 enum ea_type type; /* what kind of EA is this? */
208 int sib_present; /* is a SIB byte necessary? */
209 int bytes; /* # of bytes of offset needed */
210 int size; /* lazy - this is sib+bytes+1 */
211 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
212 int8_t disp8; /* compressed displacement for EVEX */
213 } ea;
214
215 #define GEN_SIB(scale, index, base) \
216 (((scale) << 6) | ((index) << 3) | ((base)))
217
218 #define GEN_MODRM(mod, reg, rm) \
219 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
220
221 static iflags_t cpu; /* cpu level received from nasm.c */
222 static efunc errfunc;
223 static struct ofmt *outfmt;
224 static ListGen *list;
225
226 static int64_t calcsize(int32_t, int64_t, int, insn *,
227 const struct itemplate *);
228 static void gencode(int32_t segment, int64_t offset, int bits,
229 insn * ins, const struct itemplate *temp,
230 int64_t insn_end);
231 static enum match_result find_match(const struct itemplate **tempp,
232 insn *instruction,
233 int32_t segment, int64_t offset, int bits);
234 static enum match_result matches(const struct itemplate *, insn *, int bits);
235 static opflags_t regflag(const operand *);
236 static int32_t regval(const operand *);
237 static int rexflags(int, opflags_t, int);
238 static int op_rexflags(const operand *, int);
239 static int op_evexflags(const operand *, int, uint8_t);
240 static void add_asp(insn *, int);
241
242 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
243
244 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
245 {
246 return ins->prefixes[pos] == prefix;
247 }
248
249 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
250 {
251 if (ins->prefixes[pos])
252 errfunc(ERR_NONFATAL, "invalid %s prefix",
253 prefix_name(ins->prefixes[pos]));
254 }
255
256 static const char *size_name(int size)
257 {
258 switch (size) {
259 case 1:
260 return "byte";
261 case 2:
262 return "word";
263 case 4:
264 return "dword";
265 case 8:
266 return "qword";
267 case 10:
268 return "tword";
269 case 16:
270 return "oword";
271 case 32:
272 return "yword";
273 case 64:
274 return "zword";
275 default:
276 return "???";
277 }
278 }
279
280 static void warn_overflow(int pass, int size)
281 {
282 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
283 "%s data exceeds bounds", size_name(size));
284 }
285
286 static void warn_overflow_const(int64_t data, int size)
287 {
288 if (overflow_general(data, size))
289 warn_overflow(ERR_PASS1, size);
290 }
291
292 static void warn_overflow_opd(const struct operand *o, int size)
293 {
294 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
295 if (overflow_general(o->offset, size))
296 warn_overflow(ERR_PASS2, size);
297 }
298 }
299
300 /*
301 * This routine wrappers the real output format's output routine,
302 * in order to pass a copy of the data off to the listing file
303 * generator at the same time.
304 */
305 static void out(int64_t offset, int32_t segto, const void *data,
306 enum out_type type, uint64_t size,
307 int32_t segment, int32_t wrt)
308 {
309 static int32_t lineno = 0; /* static!!! */
310 static char *lnfname = NULL;
311 uint8_t p[8];
312
313 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
314 /*
315 * This is a non-relocated address, and we're going to
316 * convert it into RAWDATA format.
317 */
318 uint8_t *q = p;
319
320 if (size > 8) {
321 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
322 return;
323 }
324
325 WRITEADDR(q, *(int64_t *)data, size);
326 data = p;
327 type = OUT_RAWDATA;
328 }
329
330 list->output(offset, data, type, size);
331
332 /*
333 * this call to src_get determines when we call the
334 * debug-format-specific "linenum" function
335 * it updates lineno and lnfname to the current values
336 * returning 0 if "same as last time", -2 if lnfname
337 * changed, and the amount by which lineno changed,
338 * if it did. thus, these variables must be static
339 */
340
341 if (src_get(&lineno, &lnfname))
342 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
343
344 outfmt->output(segto, data, type, size, segment, wrt);
345 }
346
347 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
348 {
349 if (opx->segment != NO_SEG) {
350 uint64_t data = opx->offset;
351 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
352 } else {
353 uint8_t byte = opx->offset;
354 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
355 }
356 }
357
358 static bool jmp_match(int32_t segment, int64_t offset, int bits,
359 insn * ins, const struct itemplate *temp)
360 {
361 int64_t isize;
362 const uint8_t *code = temp->code;
363 uint8_t c = code[0];
364
365 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
366 return false;
367 if (!optimizing)
368 return false;
369 if (optimizing < 0 && c == 0371)
370 return false;
371
372 isize = calcsize(segment, offset, bits, ins, temp);
373
374 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
375 /* Be optimistic in pass 1 */
376 return true;
377
378 if (ins->oprs[0].segment != segment)
379 return false;
380
381 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
382 return (isize >= -128 && isize <= 127); /* is it byte size? */
383 }
384
385 int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp,
386 insn * instruction, struct ofmt *output, efunc error,
387 ListGen * listgen)
388 {
389 const struct itemplate *temp;
390 int j;
391 enum match_result m;
392 int64_t insn_end;
393 int32_t itimes;
394 int64_t start = offset;
395 int64_t wsize; /* size for DB etc. */
396
397 errfunc = error; /* to pass to other functions */
398 cpu = cp;
399 outfmt = output; /* likewise */
400 list = listgen; /* and again */
401
402 wsize = idata_bytes(instruction->opcode);
403 if (wsize == -1)
404 return 0;
405
406 if (wsize) {
407 extop *e;
408 int32_t t = instruction->times;
409 if (t < 0)
410 errfunc(ERR_PANIC,
411 "instruction->times < 0 (%ld) in assemble()", t);
412
413 while (t--) { /* repeat TIMES times */
414 list_for_each(e, instruction->eops) {
415 if (e->type == EOT_DB_NUMBER) {
416 if (wsize > 8) {
417 errfunc(ERR_NONFATAL,
418 "integer supplied to a DT, DO or DY"
419 " instruction");
420 } else {
421 out(offset, segment, &e->offset,
422 OUT_ADDRESS, wsize, e->segment, e->wrt);
423 offset += wsize;
424 }
425 } else if (e->type == EOT_DB_STRING ||
426 e->type == EOT_DB_STRING_FREE) {
427 int align;
428
429 out(offset, segment, e->stringval,
430 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
431 align = e->stringlen % wsize;
432
433 if (align) {
434 align = wsize - align;
435 out(offset, segment, zero_buffer,
436 OUT_RAWDATA, align, NO_SEG, NO_SEG);
437 }
438 offset += e->stringlen + align;
439 }
440 }
441 if (t > 0 && t == instruction->times - 1) {
442 /*
443 * Dummy call to list->output to give the offset to the
444 * listing module.
445 */
446 list->output(offset, NULL, OUT_RAWDATA, 0);
447 list->uplevel(LIST_TIMES);
448 }
449 }
450 if (instruction->times > 1)
451 list->downlevel(LIST_TIMES);
452 return offset - start;
453 }
454
455 if (instruction->opcode == I_INCBIN) {
456 const char *fname = instruction->eops->stringval;
457 FILE *fp;
458
459 fp = fopen(fname, "rb");
460 if (!fp) {
461 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
462 fname);
463 } else if (fseek(fp, 0L, SEEK_END) < 0) {
464 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
465 fname);
466 fclose(fp);
467 } else {
468 static char buf[4096];
469 size_t t = instruction->times;
470 size_t base = 0;
471 size_t len;
472
473 len = ftell(fp);
474 if (instruction->eops->next) {
475 base = instruction->eops->next->offset;
476 len -= base;
477 if (instruction->eops->next->next &&
478 len > (size_t)instruction->eops->next->next->offset)
479 len = (size_t)instruction->eops->next->next->offset;
480 }
481 /*
482 * Dummy call to list->output to give the offset to the
483 * listing module.
484 */
485 list->output(offset, NULL, OUT_RAWDATA, 0);
486 list->uplevel(LIST_INCBIN);
487 while (t--) {
488 size_t l;
489
490 fseek(fp, base, SEEK_SET);
491 l = len;
492 while (l > 0) {
493 int32_t m;
494 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
495 if (!m) {
496 /*
497 * This shouldn't happen unless the file
498 * actually changes while we are reading
499 * it.
500 */
501 error(ERR_NONFATAL,
502 "`incbin': unexpected EOF while"
503 " reading file `%s'", fname);
504 t = 0; /* Try to exit cleanly */
505 break;
506 }
507 out(offset, segment, buf, OUT_RAWDATA, m,
508 NO_SEG, NO_SEG);
509 l -= m;
510 }
511 }
512 list->downlevel(LIST_INCBIN);
513 if (instruction->times > 1) {
514 /*
515 * Dummy call to list->output to give the offset to the
516 * listing module.
517 */
518 list->output(offset, NULL, OUT_RAWDATA, 0);
519 list->uplevel(LIST_TIMES);
520 list->downlevel(LIST_TIMES);
521 }
522 fclose(fp);
523 return instruction->times * len;
524 }
525 return 0; /* if we're here, there's an error */
526 }
527
528 /* Check to see if we need an address-size prefix */
529 add_asp(instruction, bits);
530
531 m = find_match(&temp, instruction, segment, offset, bits);
532
533 if (m == MOK_GOOD) {
534 /* Matches! */
535 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
536 itimes = instruction->times;
537 if (insn_size < 0) /* shouldn't be, on pass two */
538 error(ERR_PANIC, "errors made it through from pass one");
539 else
540 while (itimes--) {
541 for (j = 0; j < MAXPREFIX; j++) {
542 uint8_t c = 0;
543 switch (instruction->prefixes[j]) {
544 case P_WAIT:
545 c = 0x9B;
546 break;
547 case P_LOCK:
548 c = 0xF0;
549 break;
550 case P_REPNE:
551 case P_REPNZ:
552 case P_XACQUIRE:
553 case P_BND:
554 c = 0xF2;
555 break;
556 case P_REPE:
557 case P_REPZ:
558 case P_REP:
559 case P_XRELEASE:
560 c = 0xF3;
561 break;
562 case R_CS:
563 if (bits == 64) {
564 error(ERR_WARNING | ERR_PASS2,
565 "cs segment base generated, but will be ignored in 64-bit mode");
566 }
567 c = 0x2E;
568 break;
569 case R_DS:
570 if (bits == 64) {
571 error(ERR_WARNING | ERR_PASS2,
572 "ds segment base generated, but will be ignored in 64-bit mode");
573 }
574 c = 0x3E;
575 break;
576 case R_ES:
577 if (bits == 64) {
578 error(ERR_WARNING | ERR_PASS2,
579 "es segment base generated, but will be ignored in 64-bit mode");
580 }
581 c = 0x26;
582 break;
583 case R_FS:
584 c = 0x64;
585 break;
586 case R_GS:
587 c = 0x65;
588 break;
589 case R_SS:
590 if (bits == 64) {
591 error(ERR_WARNING | ERR_PASS2,
592 "ss segment base generated, but will be ignored in 64-bit mode");
593 }
594 c = 0x36;
595 break;
596 case R_SEGR6:
597 case R_SEGR7:
598 error(ERR_NONFATAL,
599 "segr6 and segr7 cannot be used as prefixes");
600 break;
601 case P_A16:
602 if (bits == 64) {
603 error(ERR_NONFATAL,
604 "16-bit addressing is not supported "
605 "in 64-bit mode");
606 } else if (bits != 16)
607 c = 0x67;
608 break;
609 case P_A32:
610 if (bits != 32)
611 c = 0x67;
612 break;
613 case P_A64:
614 if (bits != 64) {
615 error(ERR_NONFATAL,
616 "64-bit addressing is only supported "
617 "in 64-bit mode");
618 }
619 break;
620 case P_ASP:
621 c = 0x67;
622 break;
623 case P_O16:
624 if (bits != 16)
625 c = 0x66;
626 break;
627 case P_O32:
628 if (bits == 16)
629 c = 0x66;
630 break;
631 case P_O64:
632 /* REX.W */
633 break;
634 case P_OSP:
635 c = 0x66;
636 break;
637 case P_EVEX:
638 /* EVEX */
639 break;
640 case P_none:
641 break;
642 default:
643 error(ERR_PANIC, "invalid instruction prefix");
644 }
645 if (c != 0) {
646 out(offset, segment, &c, OUT_RAWDATA, 1,
647 NO_SEG, NO_SEG);
648 offset++;
649 }
650 }
651 insn_end = offset + insn_size;
652 gencode(segment, offset, bits, instruction,
653 temp, insn_end);
654 offset += insn_size;
655 if (itimes > 0 && itimes == instruction->times - 1) {
656 /*
657 * Dummy call to list->output to give the offset to the
658 * listing module.
659 */
660 list->output(offset, NULL, OUT_RAWDATA, 0);
661 list->uplevel(LIST_TIMES);
662 }
663 }
664 if (instruction->times > 1)
665 list->downlevel(LIST_TIMES);
666 return offset - start;
667 } else {
668 /* No match */
669 switch (m) {
670 case MERR_OPSIZEMISSING:
671 error(ERR_NONFATAL, "operation size not specified");
672 break;
673 case MERR_OPSIZEMISMATCH:
674 error(ERR_NONFATAL, "mismatch in operand sizes");
675 break;
676 case MERR_BRNUMMISMATCH:
677 error(ERR_NONFATAL,
678 "mismatch in the number of broadcasting elements");
679 break;
680 case MERR_BADCPU:
681 error(ERR_NONFATAL, "no instruction for this cpu level");
682 break;
683 case MERR_BADMODE:
684 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
685 bits);
686 break;
687 default:
688 error(ERR_NONFATAL,
689 "invalid combination of opcode and operands");
690 break;
691 }
692 }
693 return 0;
694 }
695
696 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp,
697 insn * instruction, efunc error)
698 {
699 const struct itemplate *temp;
700 enum match_result m;
701
702 errfunc = error; /* to pass to other functions */
703 cpu = cp;
704
705 if (instruction->opcode == I_none)
706 return 0;
707
708 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
709 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
710 instruction->opcode == I_DT || instruction->opcode == I_DO ||
711 instruction->opcode == I_DY) {
712 extop *e;
713 int32_t isize, osize, wsize;
714
715 isize = 0;
716 wsize = idata_bytes(instruction->opcode);
717
718 list_for_each(e, instruction->eops) {
719 int32_t align;
720
721 osize = 0;
722 if (e->type == EOT_DB_NUMBER) {
723 osize = 1;
724 warn_overflow_const(e->offset, wsize);
725 } else if (e->type == EOT_DB_STRING ||
726 e->type == EOT_DB_STRING_FREE)
727 osize = e->stringlen;
728
729 align = (-osize) % wsize;
730 if (align < 0)
731 align += wsize;
732 isize += osize + align;
733 }
734 return isize * instruction->times;
735 }
736
737 if (instruction->opcode == I_INCBIN) {
738 const char *fname = instruction->eops->stringval;
739 FILE *fp;
740 int64_t val = 0;
741 size_t len;
742
743 fp = fopen(fname, "rb");
744 if (!fp)
745 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
746 fname);
747 else if (fseek(fp, 0L, SEEK_END) < 0)
748 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
749 fname);
750 else {
751 len = ftell(fp);
752 if (instruction->eops->next) {
753 len -= instruction->eops->next->offset;
754 if (instruction->eops->next->next &&
755 len > (size_t)instruction->eops->next->next->offset) {
756 len = (size_t)instruction->eops->next->next->offset;
757 }
758 }
759 val = instruction->times * len;
760 }
761 if (fp)
762 fclose(fp);
763 return val;
764 }
765
766 /* Check to see if we need an address-size prefix */
767 add_asp(instruction, bits);
768
769 m = find_match(&temp, instruction, segment, offset, bits);
770 if (m == MOK_GOOD) {
771 /* we've matched an instruction. */
772 int64_t isize;
773 int j;
774
775 isize = calcsize(segment, offset, bits, instruction, temp);
776 if (isize < 0)
777 return -1;
778 for (j = 0; j < MAXPREFIX; j++) {
779 switch (instruction->prefixes[j]) {
780 case P_A16:
781 if (bits != 16)
782 isize++;
783 break;
784 case P_A32:
785 if (bits != 32)
786 isize++;
787 break;
788 case P_O16:
789 if (bits != 16)
790 isize++;
791 break;
792 case P_O32:
793 if (bits == 16)
794 isize++;
795 break;
796 case P_A64:
797 case P_O64:
798 case P_EVEX:
799 case P_none:
800 break;
801 default:
802 isize++;
803 break;
804 }
805 }
806 return isize * instruction->times;
807 } else {
808 return -1; /* didn't match any instruction */
809 }
810 }
811
812 static void bad_hle_warn(const insn * ins, uint8_t hleok)
813 {
814 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
815 enum whatwarn { w_none, w_lock, w_inval } ww;
816 static const enum whatwarn warn[2][4] =
817 {
818 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
819 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
820 };
821 unsigned int n;
822
823 n = (unsigned int)rep_pfx - P_XACQUIRE;
824 if (n > 1)
825 return; /* Not XACQUIRE/XRELEASE */
826
827 ww = warn[n][hleok];
828 if (!is_class(MEMORY, ins->oprs[0].type))
829 ww = w_inval; /* HLE requires operand 0 to be memory */
830
831 switch (ww) {
832 case w_none:
833 break;
834
835 case w_lock:
836 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
837 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
838 "%s with this instruction requires lock",
839 prefix_name(rep_pfx));
840 }
841 break;
842
843 case w_inval:
844 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
845 "%s invalid with this instruction",
846 prefix_name(rep_pfx));
847 break;
848 }
849 }
850
851 /* Common construct */
852 #define case3(x) case (x): case (x)+1: case (x)+2
853 #define case4(x) case3(x): case (x)+3
854
855 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
856 insn * ins, const struct itemplate *temp)
857 {
858 const uint8_t *codes = temp->code;
859 int64_t length = 0;
860 uint8_t c;
861 int rex_mask = ~0;
862 int op1, op2;
863 struct operand *opx;
864 uint8_t opex = 0;
865 enum ea_type eat;
866 uint8_t hleok = 0;
867 bool lockcheck = true;
868 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
869
870 ins->rex = 0; /* Ensure REX is reset */
871 eat = EA_SCALAR; /* Expect a scalar EA */
872 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
873
874 if (ins->prefixes[PPS_OSIZE] == P_O64)
875 ins->rex |= REX_W;
876
877 (void)segment; /* Don't warn that this parameter is unused */
878 (void)offset; /* Don't warn that this parameter is unused */
879
880 while (*codes) {
881 c = *codes++;
882 op1 = (c & 3) + ((opex & 1) << 2);
883 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
884 opx = &ins->oprs[op1];
885 opex = 0; /* For the next iteration */
886
887 switch (c) {
888 case4(01):
889 codes += c, length += c;
890 break;
891
892 case3(05):
893 opex = c;
894 break;
895
896 case4(010):
897 ins->rex |=
898 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
899 codes++, length++;
900 break;
901
902 case4(014):
903 /* this is an index reg of MIB operand */
904 mib_index = opx->basereg;
905 break;
906
907 case4(020):
908 case4(024):
909 length++;
910 break;
911
912 case4(030):
913 length += 2;
914 break;
915
916 case4(034):
917 if (opx->type & (BITS16 | BITS32 | BITS64))
918 length += (opx->type & BITS16) ? 2 : 4;
919 else
920 length += (bits == 16) ? 2 : 4;
921 break;
922
923 case4(040):
924 length += 4;
925 break;
926
927 case4(044):
928 length += ins->addr_size >> 3;
929 break;
930
931 case4(050):
932 length++;
933 break;
934
935 case4(054):
936 length += 8; /* MOV reg64/imm */
937 break;
938
939 case4(060):
940 length += 2;
941 break;
942
943 case4(064):
944 if (opx->type & (BITS16 | BITS32 | BITS64))
945 length += (opx->type & BITS16) ? 2 : 4;
946 else
947 length += (bits == 16) ? 2 : 4;
948 break;
949
950 case4(070):
951 length += 4;
952 break;
953
954 case4(074):
955 length += 2;
956 break;
957
958 case 0172:
959 case 0173:
960 codes++;
961 length++;
962 break;
963
964 case4(0174):
965 length++;
966 break;
967
968 case4(0240):
969 ins->rex |= REX_EV;
970 ins->vexreg = regval(opx);
971 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
972 ins->vex_cm = *codes++;
973 ins->vex_wlp = *codes++;
974 ins->evex_tuple = (*codes++ - 0300);
975 break;
976
977 case 0250:
978 ins->rex |= REX_EV;
979 ins->vexreg = 0;
980 ins->vex_cm = *codes++;
981 ins->vex_wlp = *codes++;
982 ins->evex_tuple = (*codes++ - 0300);
983 break;
984
985 case4(0254):
986 length += 4;
987 break;
988
989 case4(0260):
990 ins->rex |= REX_V;
991 ins->vexreg = regval(opx);
992 ins->vex_cm = *codes++;
993 ins->vex_wlp = *codes++;
994 break;
995
996 case 0270:
997 ins->rex |= REX_V;
998 ins->vexreg = 0;
999 ins->vex_cm = *codes++;
1000 ins->vex_wlp = *codes++;
1001 break;
1002
1003 case3(0271):
1004 hleok = c & 3;
1005 break;
1006
1007 case4(0274):
1008 length++;
1009 break;
1010
1011 case4(0300):
1012 break;
1013
1014 case 0310:
1015 if (bits == 64)
1016 return -1;
1017 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1018 break;
1019
1020 case 0311:
1021 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1022 break;
1023
1024 case 0312:
1025 break;
1026
1027 case 0313:
1028 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1029 has_prefix(ins, PPS_ASIZE, P_A32))
1030 return -1;
1031 break;
1032
1033 case4(0314):
1034 break;
1035
1036 case 0320:
1037 {
1038 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1039 if (pfx == P_O16)
1040 break;
1041 if (pfx != P_none)
1042 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1043 else
1044 ins->prefixes[PPS_OSIZE] = P_O16;
1045 break;
1046 }
1047
1048 case 0321:
1049 {
1050 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1051 if (pfx == P_O32)
1052 break;
1053 if (pfx != P_none)
1054 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1055 else
1056 ins->prefixes[PPS_OSIZE] = P_O32;
1057 break;
1058 }
1059
1060 case 0322:
1061 break;
1062
1063 case 0323:
1064 rex_mask &= ~REX_W;
1065 break;
1066
1067 case 0324:
1068 ins->rex |= REX_W;
1069 break;
1070
1071 case 0325:
1072 ins->rex |= REX_NH;
1073 break;
1074
1075 case 0326:
1076 break;
1077
1078 case 0330:
1079 codes++, length++;
1080 break;
1081
1082 case 0331:
1083 break;
1084
1085 case 0332:
1086 case 0333:
1087 length++;
1088 break;
1089
1090 case 0334:
1091 ins->rex |= REX_L;
1092 break;
1093
1094 case 0335:
1095 break;
1096
1097 case 0336:
1098 if (!ins->prefixes[PPS_REP])
1099 ins->prefixes[PPS_REP] = P_REP;
1100 break;
1101
1102 case 0337:
1103 if (!ins->prefixes[PPS_REP])
1104 ins->prefixes[PPS_REP] = P_REPNE;
1105 break;
1106
1107 case 0340:
1108 if (ins->oprs[0].segment != NO_SEG)
1109 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1110 " quantity of BSS space");
1111 else
1112 length += ins->oprs[0].offset;
1113 break;
1114
1115 case 0341:
1116 if (!ins->prefixes[PPS_WAIT])
1117 ins->prefixes[PPS_WAIT] = P_WAIT;
1118 break;
1119
1120 case 0360:
1121 break;
1122
1123 case 0361:
1124 length++;
1125 break;
1126
1127 case 0364:
1128 case 0365:
1129 break;
1130
1131 case 0366:
1132 case 0367:
1133 length++;
1134 break;
1135
1136 case 0370:
1137 case 0371:
1138 break;
1139
1140 case 0373:
1141 length++;
1142 break;
1143
1144 case 0374:
1145 eat = EA_XMMVSIB;
1146 break;
1147
1148 case 0375:
1149 eat = EA_YMMVSIB;
1150 break;
1151
1152 case 0376:
1153 eat = EA_ZMMVSIB;
1154 break;
1155
1156 case4(0100):
1157 case4(0110):
1158 case4(0120):
1159 case4(0130):
1160 case4(0200):
1161 case4(0204):
1162 case4(0210):
1163 case4(0214):
1164 case4(0220):
1165 case4(0224):
1166 case4(0230):
1167 case4(0234):
1168 {
1169 ea ea_data;
1170 int rfield;
1171 opflags_t rflags;
1172 struct operand *opy = &ins->oprs[op2];
1173 struct operand *op_er_sae;
1174
1175 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1176
1177 if (c <= 0177) {
1178 /* pick rfield from operand b (opx) */
1179 rflags = regflag(opx);
1180 rfield = nasm_regvals[opx->basereg];
1181 } else {
1182 rflags = 0;
1183 rfield = c & 7;
1184 }
1185
1186 /* EVEX.b1 : evex_brerop contains the operand position */
1187 op_er_sae = (ins->evex_brerop >= 0 ?
1188 &ins->oprs[ins->evex_brerop] : NULL);
1189
1190 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1191 /* set EVEX.b */
1192 ins->evex_p[2] |= EVEX_P2B;
1193 if (op_er_sae->decoflags & ER) {
1194 /* set EVEX.RC (rounding control) */
1195 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1196 & EVEX_P2RC;
1197 }
1198 } else {
1199 /* set EVEX.L'L (vector length) */
1200 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1201 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1202 if (opy->decoflags & BRDCAST_MASK) {
1203 /* set EVEX.b */
1204 ins->evex_p[2] |= EVEX_P2B;
1205 }
1206 }
1207
1208 /*
1209 * if a separate form of MIB (ICC style) is used,
1210 * the index reg info is merged into mem operand
1211 */
1212 if (mib_index != R_none) {
1213 opy->indexreg = mib_index;
1214 opy->scale = 1;
1215 opy->hintbase = mib_index;
1216 opy->hinttype = EAH_NOTBASE;
1217 }
1218
1219 /*
1220 * only for mib operands, make a single reg index [reg*1].
1221 * gas uses this form to explicitly denote index register.
1222 */
1223 if ((temp->flags & IF_MIB) &&
1224 (opy->indexreg == -1 && opy->hintbase == opy->basereg &&
1225 opy->hinttype == EAH_NOTBASE)) {
1226 opy->indexreg = opy->basereg;
1227 opy->basereg = -1;
1228 opy->scale = 1;
1229 }
1230
1231 if (process_ea(opy, &ea_data, bits,
1232 rfield, rflags, ins) != eat) {
1233 errfunc(ERR_NONFATAL, "invalid effective address");
1234 return -1;
1235 } else {
1236 ins->rex |= ea_data.rex;
1237 length += ea_data.size;
1238 }
1239 }
1240 break;
1241
1242 default:
1243 errfunc(ERR_PANIC, "internal instruction table corrupt"
1244 ": instruction code \\%o (0x%02X) given", c, c);
1245 break;
1246 }
1247 }
1248
1249 ins->rex &= rex_mask;
1250
1251 if (ins->rex & REX_NH) {
1252 if (ins->rex & REX_H) {
1253 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1254 return -1;
1255 }
1256 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1257 }
1258
1259 if (ins->rex & (REX_V | REX_EV)) {
1260 int bad32 = REX_R|REX_W|REX_X|REX_B;
1261
1262 if (ins->rex & REX_H) {
1263 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1264 return -1;
1265 }
1266 switch (ins->vex_wlp & 060) {
1267 case 000:
1268 case 040:
1269 ins->rex &= ~REX_W;
1270 break;
1271 case 020:
1272 ins->rex |= REX_W;
1273 bad32 &= ~REX_W;
1274 break;
1275 case 060:
1276 /* Follow REX_W */
1277 break;
1278 }
1279
1280 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1281 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1282 return -1;
1283 } else if (!(ins->rex & REX_EV) &&
1284 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1285 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1286 return -1;
1287 }
1288 if (ins->rex & REX_EV)
1289 length += 4;
1290 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1291 length += 3;
1292 else
1293 length += 2;
1294 } else if (ins->rex & REX_REAL) {
1295 if (ins->rex & REX_H) {
1296 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1297 return -1;
1298 } else if (bits == 64) {
1299 length++;
1300 } else if ((ins->rex & REX_L) &&
1301 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1302 cpu >= IF_X86_64) {
1303 /* LOCK-as-REX.R */
1304 assert_no_prefix(ins, PPS_LOCK);
1305 lockcheck = false; /* Already errored, no need for warning */
1306 length++;
1307 } else {
1308 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1309 return -1;
1310 }
1311 }
1312
1313 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1314 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1315 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1316 "instruction is not lockable");
1317 }
1318
1319 bad_hle_warn(ins, hleok);
1320
1321 return length;
1322 }
1323
1324 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1325 {
1326 if (bits == 64) {
1327 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1328 ins->rex = (ins->rex & REX_REAL) | REX_P;
1329 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1330 ins->rex = 0;
1331 return 1;
1332 }
1333 }
1334
1335 return 0;
1336 }
1337
1338 static void gencode(int32_t segment, int64_t offset, int bits,
1339 insn * ins, const struct itemplate *temp,
1340 int64_t insn_end)
1341 {
1342 uint8_t c;
1343 uint8_t bytes[4];
1344 int64_t size;
1345 int64_t data;
1346 int op1, op2;
1347 struct operand *opx;
1348 const uint8_t *codes = temp->code;
1349 uint8_t opex = 0;
1350 enum ea_type eat = EA_SCALAR;
1351
1352 while (*codes) {
1353 c = *codes++;
1354 op1 = (c & 3) + ((opex & 1) << 2);
1355 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1356 opx = &ins->oprs[op1];
1357 opex = 0; /* For the next iteration */
1358
1359 switch (c) {
1360 case 01:
1361 case 02:
1362 case 03:
1363 case 04:
1364 offset += emit_rex(ins, segment, offset, bits);
1365 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1366 codes += c;
1367 offset += c;
1368 break;
1369
1370 case 05:
1371 case 06:
1372 case 07:
1373 opex = c;
1374 break;
1375
1376 case4(010):
1377 offset += emit_rex(ins, segment, offset, bits);
1378 bytes[0] = *codes++ + (regval(opx) & 7);
1379 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1380 offset += 1;
1381 break;
1382
1383 case4(014):
1384 break;
1385
1386 case4(020):
1387 if (opx->offset < -256 || opx->offset > 255) {
1388 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1389 "byte value exceeds bounds");
1390 }
1391 out_imm8(offset, segment, opx);
1392 offset += 1;
1393 break;
1394
1395 case4(024):
1396 if (opx->offset < 0 || opx->offset > 255)
1397 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1398 "unsigned byte value exceeds bounds");
1399 out_imm8(offset, segment, opx);
1400 offset += 1;
1401 break;
1402
1403 case4(030):
1404 warn_overflow_opd(opx, 2);
1405 data = opx->offset;
1406 out(offset, segment, &data, OUT_ADDRESS, 2,
1407 opx->segment, opx->wrt);
1408 offset += 2;
1409 break;
1410
1411 case4(034):
1412 if (opx->type & (BITS16 | BITS32))
1413 size = (opx->type & BITS16) ? 2 : 4;
1414 else
1415 size = (bits == 16) ? 2 : 4;
1416 warn_overflow_opd(opx, size);
1417 data = opx->offset;
1418 out(offset, segment, &data, OUT_ADDRESS, size,
1419 opx->segment, opx->wrt);
1420 offset += size;
1421 break;
1422
1423 case4(040):
1424 warn_overflow_opd(opx, 4);
1425 data = opx->offset;
1426 out(offset, segment, &data, OUT_ADDRESS, 4,
1427 opx->segment, opx->wrt);
1428 offset += 4;
1429 break;
1430
1431 case4(044):
1432 data = opx->offset;
1433 size = ins->addr_size >> 3;
1434 warn_overflow_opd(opx, size);
1435 out(offset, segment, &data, OUT_ADDRESS, size,
1436 opx->segment, opx->wrt);
1437 offset += size;
1438 break;
1439
1440 case4(050):
1441 if (opx->segment != segment) {
1442 data = opx->offset;
1443 out(offset, segment, &data,
1444 OUT_REL1ADR, insn_end - offset,
1445 opx->segment, opx->wrt);
1446 } else {
1447 data = opx->offset - insn_end;
1448 if (data > 127 || data < -128)
1449 errfunc(ERR_NONFATAL, "short jump is out of range");
1450 out(offset, segment, &data,
1451 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1452 }
1453 offset += 1;
1454 break;
1455
1456 case4(054):
1457 data = (int64_t)opx->offset;
1458 out(offset, segment, &data, OUT_ADDRESS, 8,
1459 opx->segment, opx->wrt);
1460 offset += 8;
1461 break;
1462
1463 case4(060):
1464 if (opx->segment != segment) {
1465 data = opx->offset;
1466 out(offset, segment, &data,
1467 OUT_REL2ADR, insn_end - offset,
1468 opx->segment, opx->wrt);
1469 } else {
1470 data = opx->offset - insn_end;
1471 out(offset, segment, &data,
1472 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1473 }
1474 offset += 2;
1475 break;
1476
1477 case4(064):
1478 if (opx->type & (BITS16 | BITS32 | BITS64))
1479 size = (opx->type & BITS16) ? 2 : 4;
1480 else
1481 size = (bits == 16) ? 2 : 4;
1482 if (opx->segment != segment) {
1483 data = opx->offset;
1484 out(offset, segment, &data,
1485 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1486 insn_end - offset, opx->segment, opx->wrt);
1487 } else {
1488 data = opx->offset - insn_end;
1489 out(offset, segment, &data,
1490 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1491 }
1492 offset += size;
1493 break;
1494
1495 case4(070):
1496 if (opx->segment != segment) {
1497 data = opx->offset;
1498 out(offset, segment, &data,
1499 OUT_REL4ADR, insn_end - offset,
1500 opx->segment, opx->wrt);
1501 } else {
1502 data = opx->offset - insn_end;
1503 out(offset, segment, &data,
1504 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1505 }
1506 offset += 4;
1507 break;
1508
1509 case4(074):
1510 if (opx->segment == NO_SEG)
1511 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1512 " relocatable");
1513 data = 0;
1514 out(offset, segment, &data, OUT_ADDRESS, 2,
1515 outfmt->segbase(1 + opx->segment),
1516 opx->wrt);
1517 offset += 2;
1518 break;
1519
1520 case 0172:
1521 c = *codes++;
1522 opx = &ins->oprs[c >> 3];
1523 bytes[0] = nasm_regvals[opx->basereg] << 4;
1524 opx = &ins->oprs[c & 7];
1525 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1526 errfunc(ERR_NONFATAL,
1527 "non-absolute expression not permitted as argument %d",
1528 c & 7);
1529 } else {
1530 if (opx->offset & ~15) {
1531 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1532 "four-bit argument exceeds bounds");
1533 }
1534 bytes[0] |= opx->offset & 15;
1535 }
1536 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1537 offset++;
1538 break;
1539
1540 case 0173:
1541 c = *codes++;
1542 opx = &ins->oprs[c >> 4];
1543 bytes[0] = nasm_regvals[opx->basereg] << 4;
1544 bytes[0] |= c & 15;
1545 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1546 offset++;
1547 break;
1548
1549 case4(0174):
1550 bytes[0] = nasm_regvals[opx->basereg] << 4;
1551 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1552 offset++;
1553 break;
1554
1555 case4(0254):
1556 data = opx->offset;
1557 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1558 (int32_t)data != (int64_t)data) {
1559 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1560 "signed dword immediate exceeds bounds");
1561 }
1562 out(offset, segment, &data, OUT_ADDRESS, 4,
1563 opx->segment, opx->wrt);
1564 offset += 4;
1565 break;
1566
1567 case4(0240):
1568 case 0250:
1569 codes += 3;
1570 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1571 EVEX_P2Z | EVEX_P2AAA, 2);
1572 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1573 bytes[0] = 0x62;
1574 /* EVEX.X can be set by either REX or EVEX for different reasons */
1575 bytes[1] = ((((ins->rex & 7) << 5) |
1576 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1577 (ins->vex_cm & 3);
1578 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1579 ((~ins->vexreg & 15) << 3) |
1580 (1 << 2) | (ins->vex_wlp & 3);
1581 bytes[3] = ins->evex_p[2];
1582 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1583 offset += 4;
1584 break;
1585
1586 case4(0260):
1587 case 0270:
1588 codes += 2;
1589 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1590 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1591 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1592 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1593 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1594 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1595 offset += 3;
1596 } else {
1597 bytes[0] = 0xc5;
1598 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1599 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1600 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1601 offset += 2;
1602 }
1603 break;
1604
1605 case 0271:
1606 case 0272:
1607 case 0273:
1608 break;
1609
1610 case4(0274):
1611 {
1612 uint64_t uv, um;
1613 int s;
1614
1615 if (ins->rex & REX_W)
1616 s = 64;
1617 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1618 s = 16;
1619 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1620 s = 32;
1621 else
1622 s = bits;
1623
1624 um = (uint64_t)2 << (s-1);
1625 uv = opx->offset;
1626
1627 if (uv > 127 && uv < (uint64_t)-128 &&
1628 (uv < um-128 || uv > um-1)) {
1629 /* If this wasn't explicitly byte-sized, warn as though we
1630 * had fallen through to the imm16/32/64 case.
1631 */
1632 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1633 "%s value exceeds bounds",
1634 (opx->type & BITS8) ? "signed byte" :
1635 s == 16 ? "word" :
1636 s == 32 ? "dword" :
1637 "signed dword");
1638 }
1639 if (opx->segment != NO_SEG) {
1640 data = uv;
1641 out(offset, segment, &data, OUT_ADDRESS, 1,
1642 opx->segment, opx->wrt);
1643 } else {
1644 bytes[0] = uv;
1645 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1646 NO_SEG);
1647 }
1648 offset += 1;
1649 break;
1650 }
1651
1652 case4(0300):
1653 break;
1654
1655 case 0310:
1656 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1657 *bytes = 0x67;
1658 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1659 offset += 1;
1660 } else
1661 offset += 0;
1662 break;
1663
1664 case 0311:
1665 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1666 *bytes = 0x67;
1667 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1668 offset += 1;
1669 } else
1670 offset += 0;
1671 break;
1672
1673 case 0312:
1674 break;
1675
1676 case 0313:
1677 ins->rex = 0;
1678 break;
1679
1680 case4(0314):
1681 break;
1682
1683 case 0320:
1684 case 0321:
1685 break;
1686
1687 case 0322:
1688 case 0323:
1689 break;
1690
1691 case 0324:
1692 ins->rex |= REX_W;
1693 break;
1694
1695 case 0325:
1696 break;
1697
1698 case 0326:
1699 break;
1700
1701 case 0330:
1702 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1703 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1704 offset += 1;
1705 break;
1706
1707 case 0331:
1708 break;
1709
1710 case 0332:
1711 case 0333:
1712 *bytes = c - 0332 + 0xF2;
1713 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1714 offset += 1;
1715 break;
1716
1717 case 0334:
1718 if (ins->rex & REX_R) {
1719 *bytes = 0xF0;
1720 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1721 offset += 1;
1722 }
1723 ins->rex &= ~(REX_L|REX_R);
1724 break;
1725
1726 case 0335:
1727 break;
1728
1729 case 0336:
1730 case 0337:
1731 break;
1732
1733 case 0340:
1734 if (ins->oprs[0].segment != NO_SEG)
1735 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1736 else {
1737 int64_t size = ins->oprs[0].offset;
1738 if (size > 0)
1739 out(offset, segment, NULL,
1740 OUT_RESERVE, size, NO_SEG, NO_SEG);
1741 offset += size;
1742 }
1743 break;
1744
1745 case 0341:
1746 break;
1747
1748 case 0360:
1749 break;
1750
1751 case 0361:
1752 bytes[0] = 0x66;
1753 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1754 offset += 1;
1755 break;
1756
1757 case 0364:
1758 case 0365:
1759 break;
1760
1761 case 0366:
1762 case 0367:
1763 *bytes = c - 0366 + 0x66;
1764 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1765 offset += 1;
1766 break;
1767
1768 case3(0370):
1769 break;
1770
1771 case 0373:
1772 *bytes = bits == 16 ? 3 : 5;
1773 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1774 offset += 1;
1775 break;
1776
1777 case 0374:
1778 eat = EA_XMMVSIB;
1779 break;
1780
1781 case 0375:
1782 eat = EA_YMMVSIB;
1783 break;
1784
1785 case 0376:
1786 eat = EA_ZMMVSIB;
1787 break;
1788
1789 case4(0100):
1790 case4(0110):
1791 case4(0120):
1792 case4(0130):
1793 case4(0200):
1794 case4(0204):
1795 case4(0210):
1796 case4(0214):
1797 case4(0220):
1798 case4(0224):
1799 case4(0230):
1800 case4(0234):
1801 {
1802 ea ea_data;
1803 int rfield;
1804 opflags_t rflags;
1805 uint8_t *p;
1806 int32_t s;
1807 struct operand *opy = &ins->oprs[op2];
1808
1809 if (c <= 0177) {
1810 /* pick rfield from operand b (opx) */
1811 rflags = regflag(opx);
1812 rfield = nasm_regvals[opx->basereg];
1813 } else {
1814 /* rfield is constant */
1815 rflags = 0;
1816 rfield = c & 7;
1817 }
1818
1819 if (process_ea(opy, &ea_data, bits,
1820 rfield, rflags, ins) != eat)
1821 errfunc(ERR_NONFATAL, "invalid effective address");
1822
1823 p = bytes;
1824 *p++ = ea_data.modrm;
1825 if (ea_data.sib_present)
1826 *p++ = ea_data.sib;
1827
1828 s = p - bytes;
1829 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1830
1831 /*
1832 * Make sure the address gets the right offset in case
1833 * the line breaks in the .lst file (BR 1197827)
1834 */
1835 offset += s;
1836 s = 0;
1837
1838 switch (ea_data.bytes) {
1839 case 0:
1840 break;
1841 case 1:
1842 case 2:
1843 case 4:
1844 case 8:
1845 /* use compressed displacement, if available */
1846 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1847 s += ea_data.bytes;
1848 if (ea_data.rip) {
1849 if (opy->segment == segment) {
1850 data -= insn_end;
1851 if (overflow_signed(data, ea_data.bytes))
1852 warn_overflow(ERR_PASS2, ea_data.bytes);
1853 out(offset, segment, &data, OUT_ADDRESS,
1854 ea_data.bytes, NO_SEG, NO_SEG);
1855 } else {
1856 /* overflow check in output/linker? */
1857 out(offset, segment, &data, OUT_REL4ADR,
1858 insn_end - offset, opy->segment, opy->wrt);
1859 }
1860 } else {
1861 if (overflow_general(data, ins->addr_size >> 3) ||
1862 signed_bits(data, ins->addr_size) !=
1863 signed_bits(data, ea_data.bytes * 8))
1864 warn_overflow(ERR_PASS2, ea_data.bytes);
1865
1866 out(offset, segment, &data, OUT_ADDRESS,
1867 ea_data.bytes, opy->segment, opy->wrt);
1868 }
1869 break;
1870 default:
1871 /* Impossible! */
1872 errfunc(ERR_PANIC,
1873 "Invalid amount of bytes (%d) for offset?!",
1874 ea_data.bytes);
1875 break;
1876 }
1877 offset += s;
1878 }
1879 break;
1880
1881 default:
1882 errfunc(ERR_PANIC, "internal instruction table corrupt"
1883 ": instruction code \\%o (0x%02X) given", c, c);
1884 break;
1885 }
1886 }
1887 }
1888
1889 static opflags_t regflag(const operand * o)
1890 {
1891 if (!is_register(o->basereg))
1892 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1893 return nasm_reg_flags[o->basereg];
1894 }
1895
1896 static int32_t regval(const operand * o)
1897 {
1898 if (!is_register(o->basereg))
1899 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1900 return nasm_regvals[o->basereg];
1901 }
1902
1903 static int op_rexflags(const operand * o, int mask)
1904 {
1905 opflags_t flags;
1906 int val;
1907
1908 if (!is_register(o->basereg))
1909 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1910
1911 flags = nasm_reg_flags[o->basereg];
1912 val = nasm_regvals[o->basereg];
1913
1914 return rexflags(val, flags, mask);
1915 }
1916
1917 static int rexflags(int val, opflags_t flags, int mask)
1918 {
1919 int rex = 0;
1920
1921 if (val >= 0 && (val & 8))
1922 rex |= REX_B|REX_X|REX_R;
1923 if (flags & BITS64)
1924 rex |= REX_W;
1925 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1926 rex |= REX_H;
1927 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1928 rex |= REX_P;
1929
1930 return rex & mask;
1931 }
1932
1933 static int evexflags(int val, decoflags_t deco,
1934 int mask, uint8_t byte)
1935 {
1936 int evex = 0;
1937
1938 switch (byte) {
1939 case 0:
1940 if (val >= 0 && (val & 16))
1941 evex |= (EVEX_P0RP | EVEX_P0X);
1942 break;
1943 case 2:
1944 if (val >= 0 && (val & 16))
1945 evex |= EVEX_P2VP;
1946 if (deco & Z)
1947 evex |= EVEX_P2Z;
1948 if (deco & OPMASK_MASK)
1949 evex |= deco & EVEX_P2AAA;
1950 break;
1951 }
1952 return evex & mask;
1953 }
1954
1955 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1956 {
1957 int val;
1958
1959 if (!is_register(o->basereg))
1960 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1961
1962 val = nasm_regvals[o->basereg];
1963
1964 return evexflags(val, o->decoflags, mask, byte);
1965 }
1966
1967 static enum match_result find_match(const struct itemplate **tempp,
1968 insn *instruction,
1969 int32_t segment, int64_t offset, int bits)
1970 {
1971 const struct itemplate *temp;
1972 enum match_result m, merr;
1973 opflags_t xsizeflags[MAX_OPERANDS];
1974 bool opsizemissing = false;
1975 int8_t broadcast = instruction->evex_brerop;
1976 int i;
1977
1978 /* broadcasting uses a different data element size */
1979 for (i = 0; i < instruction->operands; i++)
1980 if (i == broadcast)
1981 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
1982 else
1983 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1984
1985 merr = MERR_INVALOP;
1986
1987 for (temp = nasm_instructions[instruction->opcode];
1988 temp->opcode != I_none; temp++) {
1989 m = matches(temp, instruction, bits);
1990 if (m == MOK_JUMP) {
1991 if (jmp_match(segment, offset, bits, instruction, temp))
1992 m = MOK_GOOD;
1993 else
1994 m = MERR_INVALOP;
1995 } else if (m == MERR_OPSIZEMISSING &&
1996 (temp->flags & IF_SMASK) != IF_SX) {
1997 /*
1998 * Missing operand size and a candidate for fuzzy matching...
1999 */
2000 for (i = 0; i < temp->operands; i++)
2001 if (i == broadcast)
2002 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2003 else
2004 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2005 opsizemissing = true;
2006 }
2007 if (m > merr)
2008 merr = m;
2009 if (merr == MOK_GOOD)
2010 goto done;
2011 }
2012
2013 /* No match, but see if we can get a fuzzy operand size match... */
2014 if (!opsizemissing)
2015 goto done;
2016
2017 for (i = 0; i < instruction->operands; i++) {
2018 /*
2019 * We ignore extrinsic operand sizes on registers, so we should
2020 * never try to fuzzy-match on them. This also resolves the case
2021 * when we have e.g. "xmmrm128" in two different positions.
2022 */
2023 if (is_class(REGISTER, instruction->oprs[i].type))
2024 continue;
2025
2026 /* This tests if xsizeflags[i] has more than one bit set */
2027 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2028 goto done; /* No luck */
2029
2030 if (i == broadcast) {
2031 instruction->oprs[i].decoflags |= xsizeflags[i];
2032 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2033 BITS32 : BITS64);
2034 } else {
2035 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2036 }
2037 }
2038
2039 /* Try matching again... */
2040 for (temp = nasm_instructions[instruction->opcode];
2041 temp->opcode != I_none; temp++) {
2042 m = matches(temp, instruction, bits);
2043 if (m == MOK_JUMP) {
2044 if (jmp_match(segment, offset, bits, instruction, temp))
2045 m = MOK_GOOD;
2046 else
2047 m = MERR_INVALOP;
2048 }
2049 if (m > merr)
2050 merr = m;
2051 if (merr == MOK_GOOD)
2052 goto done;
2053 }
2054
2055 done:
2056 *tempp = temp;
2057 return merr;
2058 }
2059
2060 static enum match_result matches(const struct itemplate *itemp,
2061 insn *instruction, int bits)
2062 {
2063 opflags_t size[MAX_OPERANDS], asize;
2064 bool opsizemissing = false;
2065 int i, oprs;
2066
2067 /*
2068 * Check the opcode
2069 */
2070 if (itemp->opcode != instruction->opcode)
2071 return MERR_INVALOP;
2072
2073 /*
2074 * Count the operands
2075 */
2076 if (itemp->operands != instruction->operands)
2077 return MERR_INVALOP;
2078
2079 /*
2080 * Is it legal?
2081 */
2082 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2083 return MERR_INVALOP;
2084
2085 /*
2086 * Check that no spurious colons or TOs are present
2087 */
2088 for (i = 0; i < itemp->operands; i++)
2089 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2090 return MERR_INVALOP;
2091
2092 /*
2093 * Process size flags
2094 */
2095 switch (itemp->flags & IF_SMASK) {
2096 case IF_SB:
2097 asize = BITS8;
2098 break;
2099 case IF_SW:
2100 asize = BITS16;
2101 break;
2102 case IF_SD:
2103 asize = BITS32;
2104 break;
2105 case IF_SQ:
2106 asize = BITS64;
2107 break;
2108 case IF_SO:
2109 asize = BITS128;
2110 break;
2111 case IF_SY:
2112 asize = BITS256;
2113 break;
2114 case IF_SZ:
2115 asize = BITS512;
2116 break;
2117 case IF_SIZE:
2118 switch (bits) {
2119 case 16:
2120 asize = BITS16;
2121 break;
2122 case 32:
2123 asize = BITS32;
2124 break;
2125 case 64:
2126 asize = BITS64;
2127 break;
2128 default:
2129 asize = 0;
2130 break;
2131 }
2132 break;
2133 default:
2134 asize = 0;
2135 break;
2136 }
2137
2138 if (itemp->flags & IF_ARMASK) {
2139 /* S- flags only apply to a specific operand */
2140 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2141 memset(size, 0, sizeof size);
2142 size[i] = asize;
2143 } else {
2144 /* S- flags apply to all operands */
2145 for (i = 0; i < MAX_OPERANDS; i++)
2146 size[i] = asize;
2147 }
2148
2149 /*
2150 * Check that the operand flags all match up,
2151 * it's a bit tricky so lets be verbose:
2152 *
2153 * 1) Find out the size of operand. If instruction
2154 * doesn't have one specified -- we're trying to
2155 * guess it either from template (IF_S* flag) or
2156 * from code bits.
2157 *
2158 * 2) If template operand do not match the instruction OR
2159 * template has an operand size specified AND this size differ
2160 * from which instruction has (perhaps we got it from code bits)
2161 * we are:
2162 * a) Check that only size of instruction and operand is differ
2163 * other characteristics do match
2164 * b) Perhaps it's a register specified in instruction so
2165 * for such a case we just mark that operand as "size
2166 * missing" and this will turn on fuzzy operand size
2167 * logic facility (handled by a caller)
2168 */
2169 for (i = 0; i < itemp->operands; i++) {
2170 opflags_t type = instruction->oprs[i].type;
2171 decoflags_t deco = instruction->oprs[i].decoflags;
2172 bool is_broadcast = deco & BRDCAST_MASK;
2173 uint8_t brcast_num = 0;
2174 opflags_t template_opsize, insn_opsize;
2175
2176 if (!(type & SIZE_MASK))
2177 type |= size[i];
2178
2179 insn_opsize = type & SIZE_MASK;
2180 if (!is_broadcast) {
2181 template_opsize = itemp->opd[i] & SIZE_MASK;
2182 } else {
2183 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2184 /*
2185 * when broadcasting, the element size depends on
2186 * the instruction type. decorator flag should match.
2187 */
2188
2189 if (deco_brsize) {
2190 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2191 /* calculate the proper number : {1to<brcast_num>} */
2192 brcast_num = (itemp->opd[i] & SIZE_MASK) / BITS128 *
2193 BITS64 / template_opsize * 2;
2194 } else {
2195 template_opsize = 0;
2196 }
2197 }
2198
2199 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2200 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2201 return MERR_INVALOP;
2202 } else if (template_opsize) {
2203 if (template_opsize != insn_opsize) {
2204 if (insn_opsize) {
2205 return MERR_INVALOP;
2206 } else if (!is_class(REGISTER, type)) {
2207 /*
2208 * Note: we don't honor extrinsic operand sizes for registers,
2209 * so "missing operand size" for a register should be
2210 * considered a wildcard match rather than an error.
2211 */
2212 opsizemissing = true;
2213 }
2214 } else if (is_broadcast &&
2215 (brcast_num !=
2216 (8U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2217 /*
2218 * broadcasting opsize matches but the number of repeated memory
2219 * element does not match.
2220 * if 64b double precision float is broadcasted to zmm (512b),
2221 * broadcasting decorator must be {1to8}.
2222 */
2223 return MERR_BRNUMMISMATCH;
2224 }
2225 } else if (is_register(instruction->oprs[i].basereg) &&
2226 nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
2227 !(itemp->flags & IF_AVX512)) {
2228 return MERR_ENCMISMATCH;
2229 } else if (instruction->prefixes[PPS_EVEX] &&
2230 !(itemp->flags & IF_AVX512)) {
2231 return MERR_ENCMISMATCH;
2232 }
2233 }
2234
2235 if (opsizemissing)
2236 return MERR_OPSIZEMISSING;
2237
2238 /*
2239 * Check operand sizes
2240 */
2241 if (itemp->flags & (IF_SM | IF_SM2)) {
2242 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2243 for (i = 0; i < oprs; i++) {
2244 asize = itemp->opd[i] & SIZE_MASK;
2245 if (asize) {
2246 for (i = 0; i < oprs; i++)
2247 size[i] = asize;
2248 break;
2249 }
2250 }
2251 } else {
2252 oprs = itemp->operands;
2253 }
2254
2255 for (i = 0; i < itemp->operands; i++) {
2256 if (!(itemp->opd[i] & SIZE_MASK) &&
2257 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2258 return MERR_OPSIZEMISMATCH;
2259 }
2260
2261 /*
2262 * Check template is okay at the set cpu level
2263 */
2264 if (((itemp->flags & IF_PLEVEL) > cpu))
2265 return MERR_BADCPU;
2266
2267 /*
2268 * Verify the appropriate long mode flag.
2269 */
2270 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2271 return MERR_BADMODE;
2272
2273 /*
2274 * If we have a HLE prefix, look for the NOHLE flag
2275 */
2276 if ((itemp->flags & IF_NOHLE) &&
2277 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2278 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2279 return MERR_BADHLE;
2280
2281 /*
2282 * Check if special handling needed for Jumps
2283 */
2284 if ((itemp->code[0] & ~1) == 0370)
2285 return MOK_JUMP;
2286
2287 /*
2288 * Check if BND prefix is allowed
2289 */
2290 if ((IF_BND & ~itemp->flags) &&
2291 has_prefix(instruction, PPS_REP, P_BND))
2292 return MERR_BADBND;
2293
2294 return MOK_GOOD;
2295 }
2296
2297 /*
2298 * Check if ModR/M.mod should/can be 01.
2299 * - EAF_BYTEOFFS is set
2300 * - offset can fit in a byte when EVEX is not used
2301 * - offset can be compressed when EVEX is used
2302 */
2303 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2304 (o >= -128 && o <= 127 && \
2305 seg == NO_SEG && !forw_ref && \
2306 !(input->eaflags & EAF_WORDOFFS) && \
2307 !(ins->rex & REX_EV)) || \
2308 (ins->rex & REX_EV && \
2309 is_disp8n(input, ins, &output->disp8)))
2310
2311 static enum ea_type process_ea(operand *input, ea *output, int bits,
2312 int rfield, opflags_t rflags, insn *ins)
2313 {
2314 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2315 int addrbits = ins->addr_size;
2316
2317 output->type = EA_SCALAR;
2318 output->rip = false;
2319 output->disp8 = 0;
2320
2321 /* REX flags for the rfield operand */
2322 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2323 /* EVEX.R' flag for the REG operand */
2324 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2325
2326 if (is_class(REGISTER, input->type)) {
2327 /*
2328 * It's a direct register.
2329 */
2330 if (!is_register(input->basereg))
2331 goto err;
2332
2333 if (!is_reg_class(REG_EA, input->basereg))
2334 goto err;
2335
2336 /* broadcasting is not available with a direct register operand. */
2337 if (input->decoflags & BRDCAST_MASK) {
2338 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2339 goto err;
2340 }
2341
2342 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2343 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2344 output->sib_present = false; /* no SIB necessary */
2345 output->bytes = 0; /* no offset necessary either */
2346 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2347 } else {
2348 /*
2349 * It's a memory reference.
2350 */
2351
2352 /* Embedded rounding or SAE is not available with a mem ref operand. */
2353 if (input->decoflags & (ER | SAE)) {
2354 nasm_error(ERR_NONFATAL,
2355 "Embedded rounding is available only with reg-reg op.");
2356 return -1;
2357 }
2358
2359 if (input->basereg == -1 &&
2360 (input->indexreg == -1 || input->scale == 0)) {
2361 /*
2362 * It's a pure offset.
2363 */
2364 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2365 input->segment == NO_SEG) {
2366 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2367 input->type &= ~IP_REL;
2368 input->type |= MEMORY;
2369 }
2370
2371 if (input->eaflags & EAF_BYTEOFFS ||
2372 (input->eaflags & EAF_WORDOFFS &&
2373 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2374 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2375 }
2376
2377 if (bits == 64 && (~input->type & IP_REL)) {
2378 output->sib_present = true;
2379 output->sib = GEN_SIB(0, 4, 5);
2380 output->bytes = 4;
2381 output->modrm = GEN_MODRM(0, rfield, 4);
2382 output->rip = false;
2383 } else {
2384 output->sib_present = false;
2385 output->bytes = (addrbits != 16 ? 4 : 2);
2386 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2387 output->rip = bits == 64;
2388 }
2389 } else {
2390 /*
2391 * It's an indirection.
2392 */
2393 int i = input->indexreg, b = input->basereg, s = input->scale;
2394 int32_t seg = input->segment;
2395 int hb = input->hintbase, ht = input->hinttype;
2396 int t, it, bt; /* register numbers */
2397 opflags_t x, ix, bx; /* register flags */
2398
2399 if (s == 0)
2400 i = -1; /* make this easy, at least */
2401
2402 if (is_register(i)) {
2403 it = nasm_regvals[i];
2404 ix = nasm_reg_flags[i];
2405 } else {
2406 it = -1;
2407 ix = 0;
2408 }
2409
2410 if (is_register(b)) {
2411 bt = nasm_regvals[b];
2412 bx = nasm_reg_flags[b];
2413 } else {
2414 bt = -1;
2415 bx = 0;
2416 }
2417
2418 /* if either one are a vector register... */
2419 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2420 opflags_t sok = BITS32 | BITS64;
2421 int32_t o = input->offset;
2422 int mod, scale, index, base;
2423
2424 /*
2425 * For a vector SIB, one has to be a vector and the other,
2426 * if present, a GPR. The vector must be the index operand.
2427 */
2428 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2429 if (s == 0)
2430 s = 1;
2431 else if (s != 1)
2432 goto err;
2433
2434 t = bt, bt = it, it = t;
2435 x = bx, bx = ix, ix = x;
2436 }
2437
2438 if (bt != -1) {
2439 if (REG_GPR & ~bx)
2440 goto err;
2441 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2442 sok &= bx;
2443 else
2444 goto err;
2445 }
2446
2447 /*
2448 * While we're here, ensure the user didn't specify
2449 * WORD or QWORD
2450 */
2451 if (input->disp_size == 16 || input->disp_size == 64)
2452 goto err;
2453
2454 if (addrbits == 16 ||
2455 (addrbits == 32 && !(sok & BITS32)) ||
2456 (addrbits == 64 && !(sok & BITS64)))
2457 goto err;
2458
2459 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2460 : ((ix & YMMREG & ~REG_EA)
2461 ? EA_YMMVSIB : EA_XMMVSIB));
2462
2463 output->rex |= rexflags(it, ix, REX_X);
2464 output->rex |= rexflags(bt, bx, REX_B);
2465 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2466
2467 index = it & 7; /* it is known to be != -1 */
2468
2469 switch (s) {
2470 case 1:
2471 scale = 0;
2472 break;
2473 case 2:
2474 scale = 1;
2475 break;
2476 case 4:
2477 scale = 2;
2478 break;
2479 case 8:
2480 scale = 3;
2481 break;
2482 default: /* then what the smeg is it? */
2483 goto err; /* panic */
2484 }
2485
2486 if (bt == -1) {
2487 base = 5;
2488 mod = 0;
2489 } else {
2490 base = (bt & 7);
2491 if (base != REG_NUM_EBP && o == 0 &&
2492 seg == NO_SEG && !forw_ref &&
2493 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2494 mod = 0;
2495 else if (IS_MOD_01())
2496 mod = 1;
2497 else
2498 mod = 2;
2499 }
2500
2501 output->sib_present = true;
2502 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2503 output->modrm = GEN_MODRM(mod, rfield, 4);
2504 output->sib = GEN_SIB(scale, index, base);
2505 } else if ((ix|bx) & (BITS32|BITS64)) {
2506 /*
2507 * it must be a 32/64-bit memory reference. Firstly we have
2508 * to check that all registers involved are type E/Rxx.
2509 */
2510 opflags_t sok = BITS32 | BITS64;
2511 int32_t o = input->offset;
2512
2513 if (it != -1) {
2514 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2515 sok &= ix;
2516 else
2517 goto err;
2518 }
2519
2520 if (bt != -1) {
2521 if (REG_GPR & ~bx)
2522 goto err; /* Invalid register */
2523 if (~sok & bx & SIZE_MASK)
2524 goto err; /* Invalid size */
2525 sok &= bx;
2526 }
2527
2528 /*
2529 * While we're here, ensure the user didn't specify
2530 * WORD or QWORD
2531 */
2532 if (input->disp_size == 16 || input->disp_size == 64)
2533 goto err;
2534
2535 if (addrbits == 16 ||
2536 (addrbits == 32 && !(sok & BITS32)) ||
2537 (addrbits == 64 && !(sok & BITS64)))
2538 goto err;
2539
2540 /* now reorganize base/index */
2541 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2542 ((hb == b && ht == EAH_NOTBASE) ||
2543 (hb == i && ht == EAH_MAKEBASE))) {
2544 /* swap if hints say so */
2545 t = bt, bt = it, it = t;
2546 x = bx, bx = ix, ix = x;
2547 }
2548 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2549 bt = -1, bx = 0, s++;
2550 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2551 /* make single reg base, unless hint */
2552 bt = it, bx = ix, it = -1, ix = 0;
2553 }
2554 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2555 s == 3 || s == 5 || s == 9) && bt == -1)
2556 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2557 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2558 (input->eaflags & EAF_TIMESTWO))
2559 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2560 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2561 if (s == 1 && it == REG_NUM_ESP) {
2562 /* swap ESP into base if scale is 1 */
2563 t = it, it = bt, bt = t;
2564 x = ix, ix = bx, bx = x;
2565 }
2566 if (it == REG_NUM_ESP ||
2567 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2568 goto err; /* wrong, for various reasons */
2569
2570 output->rex |= rexflags(it, ix, REX_X);
2571 output->rex |= rexflags(bt, bx, REX_B);
2572
2573 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2574 /* no SIB needed */
2575 int mod, rm;
2576
2577 if (bt == -1) {
2578 rm = 5;
2579 mod = 0;
2580 } else {
2581 rm = (bt & 7);
2582 if (rm != REG_NUM_EBP && o == 0 &&
2583 seg == NO_SEG && !forw_ref &&
2584 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2585 mod = 0;
2586 else if (IS_MOD_01())
2587 mod = 1;
2588 else
2589 mod = 2;
2590 }
2591
2592 output->sib_present = false;
2593 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2594 output->modrm = GEN_MODRM(mod, rfield, rm);
2595 } else {
2596 /* we need a SIB */
2597 int mod, scale, index, base;
2598
2599 if (it == -1)
2600 index = 4, s = 1;
2601 else
2602 index = (it & 7);
2603
2604 switch (s) {
2605 case 1:
2606 scale = 0;
2607 break;
2608 case 2:
2609 scale = 1;
2610 break;
2611 case 4:
2612 scale = 2;
2613 break;
2614 case 8:
2615 scale = 3;
2616 break;
2617 default: /* then what the smeg is it? */
2618 goto err; /* panic */
2619 }
2620
2621 if (bt == -1) {
2622 base = 5;
2623 mod = 0;
2624 } else {
2625 base = (bt & 7);
2626 if (base != REG_NUM_EBP && o == 0 &&
2627 seg == NO_SEG && !forw_ref &&
2628 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2629 mod = 0;
2630 else if (IS_MOD_01())
2631 mod = 1;
2632 else
2633 mod = 2;
2634 }
2635
2636 output->sib_present = true;
2637 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2638 output->modrm = GEN_MODRM(mod, rfield, 4);
2639 output->sib = GEN_SIB(scale, index, base);
2640 }
2641 } else { /* it's 16-bit */
2642 int mod, rm;
2643 int16_t o = input->offset;
2644
2645 /* check for 64-bit long mode */
2646 if (addrbits == 64)
2647 goto err;
2648
2649 /* check all registers are BX, BP, SI or DI */
2650 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2651 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2652 goto err;
2653
2654 /* ensure the user didn't specify DWORD/QWORD */
2655 if (input->disp_size == 32 || input->disp_size == 64)
2656 goto err;
2657
2658 if (s != 1 && i != -1)
2659 goto err; /* no can do, in 16-bit EA */
2660 if (b == -1 && i != -1) {
2661 int tmp = b;
2662 b = i;
2663 i = tmp;
2664 } /* swap */
2665 if ((b == R_SI || b == R_DI) && i != -1) {
2666 int tmp = b;
2667 b = i;
2668 i = tmp;
2669 }
2670 /* have BX/BP as base, SI/DI index */
2671 if (b == i)
2672 goto err; /* shouldn't ever happen, in theory */
2673 if (i != -1 && b != -1 &&
2674 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2675 goto err; /* invalid combinations */
2676 if (b == -1) /* pure offset: handled above */
2677 goto err; /* so if it gets to here, panic! */
2678
2679 rm = -1;
2680 if (i != -1)
2681 switch (i * 256 + b) {
2682 case R_SI * 256 + R_BX:
2683 rm = 0;
2684 break;
2685 case R_DI * 256 + R_BX:
2686 rm = 1;
2687 break;
2688 case R_SI * 256 + R_BP:
2689 rm = 2;
2690 break;
2691 case R_DI * 256 + R_BP:
2692 rm = 3;
2693 break;
2694 } else
2695 switch (b) {
2696 case R_SI:
2697 rm = 4;
2698 break;
2699 case R_DI:
2700 rm = 5;
2701 break;
2702 case R_BP:
2703 rm = 6;
2704 break;
2705 case R_BX:
2706 rm = 7;
2707 break;
2708 }
2709 if (rm == -1) /* can't happen, in theory */
2710 goto err; /* so panic if it does */
2711
2712 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2713 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2714 mod = 0;
2715 else if (IS_MOD_01())
2716 mod = 1;
2717 else
2718 mod = 2;
2719
2720 output->sib_present = false; /* no SIB - it's 16-bit */
2721 output->bytes = mod; /* bytes of offset needed */
2722 output->modrm = GEN_MODRM(mod, rfield, rm);
2723 }
2724 }
2725 }
2726
2727 output->size = 1 + output->sib_present + output->bytes;
2728 return output->type;
2729
2730 err:
2731 return output->type = EA_INVALID;
2732 }
2733
2734 static void add_asp(insn *ins, int addrbits)
2735 {
2736 int j, valid;
2737 int defdisp;
2738
2739 valid = (addrbits == 64) ? 64|32 : 32|16;
2740
2741 switch (ins->prefixes[PPS_ASIZE]) {
2742 case P_A16:
2743 valid &= 16;
2744 break;
2745 case P_A32:
2746 valid &= 32;
2747 break;
2748 case P_A64:
2749 valid &= 64;
2750 break;
2751 case P_ASP:
2752 valid &= (addrbits == 32) ? 16 : 32;
2753 break;
2754 default:
2755 break;
2756 }
2757
2758 for (j = 0; j < ins->operands; j++) {
2759 if (is_class(MEMORY, ins->oprs[j].type)) {
2760 opflags_t i, b;
2761
2762 /* Verify as Register */
2763 if (!is_register(ins->oprs[j].indexreg))
2764 i = 0;
2765 else
2766 i = nasm_reg_flags[ins->oprs[j].indexreg];
2767
2768 /* Verify as Register */
2769 if (!is_register(ins->oprs[j].basereg))
2770 b = 0;
2771 else
2772 b = nasm_reg_flags[ins->oprs[j].basereg];
2773
2774 if (ins->oprs[j].scale == 0)
2775 i = 0;
2776
2777 if (!i && !b) {
2778 int ds = ins->oprs[j].disp_size;
2779 if ((addrbits != 64 && ds > 8) ||
2780 (addrbits == 64 && ds == 16))
2781 valid &= ds;
2782 } else {
2783 if (!(REG16 & ~b))
2784 valid &= 16;
2785 if (!(REG32 & ~b))
2786 valid &= 32;
2787 if (!(REG64 & ~b))
2788 valid &= 64;
2789
2790 if (!(REG16 & ~i))
2791 valid &= 16;
2792 if (!(REG32 & ~i))
2793 valid &= 32;
2794 if (!(REG64 & ~i))
2795 valid &= 64;
2796 }
2797 }
2798 }
2799
2800 if (valid & addrbits) {
2801 ins->addr_size = addrbits;
2802 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2803 /* Add an address size prefix */
2804 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2805 ins->addr_size = (addrbits == 32) ? 16 : 32;
2806 } else {
2807 /* Impossible... */
2808 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2809 ins->addr_size = addrbits; /* Error recovery */
2810 }
2811
2812 defdisp = ins->addr_size == 16 ? 16 : 32;
2813
2814 for (j = 0; j < ins->operands; j++) {
2815 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2816 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2817 /*
2818 * mem_offs sizes must match the address size; if not,
2819 * strip the MEM_OFFS bit and match only EA instructions
2820 */
2821 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2822 }
2823 }
2824 }
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