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[nasm.git] / disasm.c
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1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43 #include <inttypes.h>
44
45 #include "nasm.h"
46 #include "disasm.h"
47 #include "sync.h"
48 #include "insns.h"
49 #include "tables.h"
50 #include "regdis.h"
51
52 /*
53 * Flags that go into the `segment' field of `insn' structures
54 * during disassembly.
55 */
56 #define SEG_RELATIVE 1
57 #define SEG_32BIT 2
58 #define SEG_RMREG 4
59 #define SEG_DISP8 8
60 #define SEG_DISP16 16
61 #define SEG_DISP32 32
62 #define SEG_NODISP 64
63 #define SEG_SIGNED 128
64 #define SEG_64BIT 256
65
66 /*
67 * Prefix information
68 */
69 struct prefix_info {
70 uint8_t osize; /* Operand size */
71 uint8_t asize; /* Address size */
72 uint8_t osp; /* Operand size prefix present */
73 uint8_t asp; /* Address size prefix present */
74 uint8_t rep; /* Rep prefix present */
75 uint8_t seg; /* Segment override prefix present */
76 uint8_t wait; /* WAIT "prefix" present */
77 uint8_t lock; /* Lock prefix present */
78 uint8_t vex[3]; /* VEX prefix present */
79 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
80 uint8_t vex_m; /* VEX.M field */
81 uint8_t vex_v;
82 uint8_t vex_lp; /* VEX.LP fields */
83 uint32_t rex; /* REX prefix present */
84 };
85
86 #define getu8(x) (*(uint8_t *)(x))
87 #if X86_MEMORY
88 /* Littleendian CPU which can handle unaligned references */
89 #define getu16(x) (*(uint16_t *)(x))
90 #define getu32(x) (*(uint32_t *)(x))
91 #define getu64(x) (*(uint64_t *)(x))
92 #else
93 static uint16_t getu16(uint8_t *data)
94 {
95 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
96 }
97 static uint32_t getu32(uint8_t *data)
98 {
99 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
100 }
101 static uint64_t getu64(uint8_t *data)
102 {
103 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
104 }
105 #endif
106
107 #define gets8(x) ((int8_t)getu8(x))
108 #define gets16(x) ((int16_t)getu16(x))
109 #define gets32(x) ((int32_t)getu32(x))
110 #define gets64(x) ((int64_t)getu64(x))
111
112 /* Important: regval must already have been adjusted for rex extensions */
113 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
114 {
115 if (!(regflags & (REGISTER|REGMEM)))
116 return 0; /* Registers not permissible?! */
117
118 regflags |= REGISTER;
119
120 if (!(REG_AL & ~regflags))
121 return R_AL;
122 if (!(REG_AX & ~regflags))
123 return R_AX;
124 if (!(REG_EAX & ~regflags))
125 return R_EAX;
126 if (!(REG_RAX & ~regflags))
127 return R_RAX;
128 if (!(REG_DL & ~regflags))
129 return R_DL;
130 if (!(REG_DX & ~regflags))
131 return R_DX;
132 if (!(REG_EDX & ~regflags))
133 return R_EDX;
134 if (!(REG_RDX & ~regflags))
135 return R_RDX;
136 if (!(REG_CL & ~regflags))
137 return R_CL;
138 if (!(REG_CX & ~regflags))
139 return R_CX;
140 if (!(REG_ECX & ~regflags))
141 return R_ECX;
142 if (!(REG_RCX & ~regflags))
143 return R_RCX;
144 if (!(FPU0 & ~regflags))
145 return R_ST0;
146 if (!(XMM0 & ~regflags))
147 return R_XMM0;
148 if (!(YMM0 & ~regflags))
149 return R_YMM0;
150 if (!(REG_CS & ~regflags))
151 return (regval == 1) ? R_CS : 0;
152 if (!(REG_DESS & ~regflags))
153 return (regval == 0 || regval == 2
154 || regval == 3 ? nasm_rd_sreg[regval] : 0);
155 if (!(REG_FSGS & ~regflags))
156 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
157 if (!(REG_SEG67 & ~regflags))
158 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
159
160 /* All the entries below look up regval in an 16-entry array */
161 if (regval < 0 || regval > 15)
162 return 0;
163
164 if (!(REG8 & ~regflags)) {
165 if (rex & (REX_P|REX_NH))
166 return nasm_rd_reg8_rex[regval];
167 else
168 return nasm_rd_reg8[regval];
169 }
170 if (!(REG16 & ~regflags))
171 return nasm_rd_reg16[regval];
172 if (!(REG32 & ~regflags))
173 return nasm_rd_reg32[regval];
174 if (!(REG64 & ~regflags))
175 return nasm_rd_reg64[regval];
176 if (!(REG_SREG & ~regflags))
177 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
178 if (!(REG_CREG & ~regflags))
179 return nasm_rd_creg[regval];
180 if (!(REG_DREG & ~regflags))
181 return nasm_rd_dreg[regval];
182 if (!(REG_TREG & ~regflags)) {
183 if (regval > 7)
184 return 0; /* TR registers are ill-defined with rex */
185 return nasm_rd_treg[regval];
186 }
187 if (!(FPUREG & ~regflags))
188 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
189 if (!(MMXREG & ~regflags))
190 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
191 if (!(XMMREG & ~regflags))
192 return nasm_rd_xmmreg[regval];
193 if (!(YMMREG & ~regflags))
194 return nasm_rd_ymmreg[regval];
195
196 return 0;
197 }
198
199 /*
200 * Process an effective address (ModRM) specification.
201 */
202 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
203 int segsize, enum ea_type type,
204 operand *op, insn *ins)
205 {
206 int mod, rm, scale, index, base;
207 int rex;
208 uint8_t sib = 0;
209
210 mod = (modrm >> 6) & 03;
211 rm = modrm & 07;
212
213 if (mod != 3 && asize != 16 && rm == 4)
214 sib = *data++;
215
216 rex = ins->rex;
217
218 if (mod == 3) { /* pure register version */
219 op->basereg = rm+(rex & REX_B ? 8 : 0);
220 op->segment |= SEG_RMREG;
221 return data;
222 }
223
224 op->disp_size = 0;
225 op->eaflags = 0;
226
227 if (asize == 16) {
228 /*
229 * <mod> specifies the displacement size (none, byte or
230 * word), and <rm> specifies the register combination.
231 * Exception: mod=0,rm=6 does not specify [BP] as one might
232 * expect, but instead specifies [disp16].
233 */
234
235 if (type != EA_SCALAR)
236 return NULL;
237
238 op->indexreg = op->basereg = -1;
239 op->scale = 1; /* always, in 16 bits */
240 switch (rm) {
241 case 0:
242 op->basereg = R_BX;
243 op->indexreg = R_SI;
244 break;
245 case 1:
246 op->basereg = R_BX;
247 op->indexreg = R_DI;
248 break;
249 case 2:
250 op->basereg = R_BP;
251 op->indexreg = R_SI;
252 break;
253 case 3:
254 op->basereg = R_BP;
255 op->indexreg = R_DI;
256 break;
257 case 4:
258 op->basereg = R_SI;
259 break;
260 case 5:
261 op->basereg = R_DI;
262 break;
263 case 6:
264 op->basereg = R_BP;
265 break;
266 case 7:
267 op->basereg = R_BX;
268 break;
269 }
270 if (rm == 6 && mod == 0) { /* special case */
271 op->basereg = -1;
272 if (segsize != 16)
273 op->disp_size = 16;
274 mod = 2; /* fake disp16 */
275 }
276 switch (mod) {
277 case 0:
278 op->segment |= SEG_NODISP;
279 break;
280 case 1:
281 op->segment |= SEG_DISP8;
282 op->offset = (int8_t)*data++;
283 break;
284 case 2:
285 op->segment |= SEG_DISP16;
286 op->offset = *data++;
287 op->offset |= ((unsigned)*data++) << 8;
288 break;
289 }
290 return data;
291 } else {
292 /*
293 * Once again, <mod> specifies displacement size (this time
294 * none, byte or *dword*), while <rm> specifies the base
295 * register. Again, [EBP] is missing, replaced by a pure
296 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
297 * and RIP-relative addressing in 64-bit mode.
298 *
299 * However, rm=4
300 * indicates not a single base register, but instead the
301 * presence of a SIB byte...
302 */
303 int a64 = asize == 64;
304
305 op->indexreg = -1;
306
307 if (a64)
308 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
309 else
310 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
311
312 if (rm == 5 && mod == 0) {
313 if (segsize == 64) {
314 op->eaflags |= EAF_REL;
315 op->segment |= SEG_RELATIVE;
316 mod = 2; /* fake disp32 */
317 }
318
319 if (asize != 64)
320 op->disp_size = asize;
321
322 op->basereg = -1;
323 mod = 2; /* fake disp32 */
324 }
325
326
327 if (rm == 4) { /* process SIB */
328 scale = (sib >> 6) & 03;
329 index = (sib >> 3) & 07;
330 base = sib & 07;
331
332 op->scale = 1 << scale;
333
334 if (type == EA_XMMVSIB)
335 op->indexreg = nasm_rd_xmmreg[index | ((rex & REX_X) ? 8 : 0)];
336 else if (type == EA_YMMVSIB)
337 op->indexreg = nasm_rd_ymmreg[index | ((rex & REX_X) ? 8 : 0)];
338 else if (index == 4 && !(rex & REX_X))
339 op->indexreg = -1; /* ESP/RSP cannot be an index */
340 else if (a64)
341 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
342 else
343 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
344
345 if (base == 5 && mod == 0) {
346 op->basereg = -1;
347 mod = 2; /* Fake disp32 */
348 } else if (a64)
349 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
350 else
351 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
352
353 if (segsize == 16)
354 op->disp_size = 32;
355 } else if (type != EA_SCALAR) {
356 /* Can't have VSIB without SIB */
357 return NULL;
358 }
359
360 switch (mod) {
361 case 0:
362 op->segment |= SEG_NODISP;
363 break;
364 case 1:
365 op->segment |= SEG_DISP8;
366 op->offset = gets8(data);
367 data++;
368 break;
369 case 2:
370 op->segment |= SEG_DISP32;
371 op->offset = gets32(data);
372 data += 4;
373 break;
374 }
375 return data;
376 }
377 }
378
379 /*
380 * Determine whether the instruction template in t corresponds to the data
381 * stream in data. Return the number of bytes matched if so.
382 */
383 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
384
385 static int matches(const struct itemplate *t, uint8_t *data,
386 const struct prefix_info *prefix, int segsize, insn *ins)
387 {
388 uint8_t *r = (uint8_t *)(t->code);
389 uint8_t *origdata = data;
390 bool a_used = false, o_used = false;
391 enum prefixes drep = 0;
392 enum prefixes dwait = 0;
393 uint8_t lock = prefix->lock;
394 int osize = prefix->osize;
395 int asize = prefix->asize;
396 int i, c;
397 int op1, op2;
398 struct operand *opx, *opy;
399 uint8_t opex = 0;
400 bool vex_ok = false;
401 int regmask = (segsize == 64) ? 15 : 7;
402 enum ea_type eat = EA_SCALAR;
403
404 for (i = 0; i < MAX_OPERANDS; i++) {
405 ins->oprs[i].segment = ins->oprs[i].disp_size =
406 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
407 }
408 ins->condition = -1;
409 ins->rex = prefix->rex;
410 memset(ins->prefixes, 0, sizeof ins->prefixes);
411
412 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
413 return false;
414
415 if (prefix->rep == 0xF2)
416 drep = P_REPNE;
417 else if (prefix->rep == 0xF3)
418 drep = P_REP;
419
420 dwait = prefix->wait ? P_WAIT : 0;
421
422 while ((c = *r++) != 0) {
423 op1 = (c & 3) + ((opex & 1) << 2);
424 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
425 opx = &ins->oprs[op1];
426 opy = &ins->oprs[op2];
427 opex = 0;
428
429 switch (c) {
430 case 01:
431 case 02:
432 case 03:
433 case 04:
434 while (c--)
435 if (*r++ != *data++)
436 return false;
437 break;
438
439 case 05:
440 case 06:
441 case 07:
442 opex = c;
443 break;
444
445 case4(010):
446 {
447 int t = *r++, d = *data++;
448 if (d < t || d > t + 7)
449 return false;
450 else {
451 opx->basereg = (d-t)+
452 (ins->rex & REX_B ? 8 : 0);
453 opx->segment |= SEG_RMREG;
454 }
455 break;
456 }
457
458 case4(0274):
459 opx->offset = (int8_t)*data++;
460 opx->segment |= SEG_SIGNED;
461 break;
462
463 case4(020):
464 opx->offset = *data++;
465 break;
466
467 case4(024):
468 opx->offset = *data++;
469 break;
470
471 case4(030):
472 opx->offset = getu16(data);
473 data += 2;
474 break;
475
476 case4(034):
477 if (osize == 32) {
478 opx->offset = getu32(data);
479 data += 4;
480 } else {
481 opx->offset = getu16(data);
482 data += 2;
483 }
484 if (segsize != asize)
485 opx->disp_size = asize;
486 break;
487
488 case4(040):
489 opx->offset = getu32(data);
490 data += 4;
491 break;
492
493 case4(0254):
494 opx->offset = gets32(data);
495 data += 4;
496 break;
497
498 case4(044):
499 switch (asize) {
500 case 16:
501 opx->offset = getu16(data);
502 data += 2;
503 if (segsize != 16)
504 opx->disp_size = 16;
505 break;
506 case 32:
507 opx->offset = getu32(data);
508 data += 4;
509 if (segsize == 16)
510 opx->disp_size = 32;
511 break;
512 case 64:
513 opx->offset = getu64(data);
514 opx->disp_size = 64;
515 data += 8;
516 break;
517 }
518 break;
519
520 case4(050):
521 opx->offset = gets8(data++);
522 opx->segment |= SEG_RELATIVE;
523 break;
524
525 case4(054):
526 opx->offset = getu64(data);
527 data += 8;
528 break;
529
530 case4(060):
531 opx->offset = gets16(data);
532 data += 2;
533 opx->segment |= SEG_RELATIVE;
534 opx->segment &= ~SEG_32BIT;
535 break;
536
537 case4(064): /* rel */
538 opx->segment |= SEG_RELATIVE;
539 /* In long mode rel is always 32 bits, sign extended. */
540 if (segsize == 64 || osize == 32) {
541 opx->offset = gets32(data);
542 data += 4;
543 if (segsize != 64)
544 opx->segment |= SEG_32BIT;
545 opx->type = (opx->type & ~SIZE_MASK)
546 | (segsize == 64 ? BITS64 : BITS32);
547 } else {
548 opx->offset = gets16(data);
549 data += 2;
550 opx->segment &= ~SEG_32BIT;
551 opx->type = (opx->type & ~SIZE_MASK) | BITS16;
552 }
553 break;
554
555 case4(070):
556 opx->offset = gets32(data);
557 data += 4;
558 opx->segment |= SEG_32BIT | SEG_RELATIVE;
559 break;
560
561 case4(0100):
562 case4(0110):
563 case4(0120):
564 case4(0130):
565 {
566 int modrm = *data++;
567 opx->segment |= SEG_RMREG;
568 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
569 if (!data)
570 return false;
571 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
572 break;
573 }
574
575 case 0172:
576 {
577 uint8_t ximm = *data++;
578 c = *r++;
579 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
580 ins->oprs[c >> 3].segment |= SEG_RMREG;
581 ins->oprs[c & 7].offset = ximm & 15;
582 }
583 break;
584
585 case 0173:
586 {
587 uint8_t ximm = *data++;
588 c = *r++;
589
590 if ((c ^ ximm) & 15)
591 return false;
592
593 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
594 ins->oprs[c >> 4].segment |= SEG_RMREG;
595 }
596 break;
597
598 case4(0174):
599 {
600 uint8_t ximm = *data++;
601
602 opx->basereg = (ximm >> 4) & regmask;
603 opx->segment |= SEG_RMREG;
604 }
605 break;
606
607 case4(0200):
608 case4(0204):
609 case4(0210):
610 case4(0214):
611 case4(0220):
612 case4(0224):
613 case4(0230):
614 case4(0234):
615 {
616 int modrm = *data++;
617 if (((modrm >> 3) & 07) != (c & 07))
618 return false; /* spare field doesn't match up */
619 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
620 if (!data)
621 return false;
622 break;
623 }
624
625 case4(0260):
626 case 0270:
627 {
628 int vexm = *r++;
629 int vexwlp = *r++;
630
631 ins->rex |= REX_V;
632 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
633 return false;
634
635 if ((vexm & 0x1f) != prefix->vex_m)
636 return false;
637
638 switch (vexwlp & 060) {
639 case 000:
640 if (prefix->rex & REX_W)
641 return false;
642 break;
643 case 020:
644 if (!(prefix->rex & REX_W))
645 return false;
646 ins->rex &= ~REX_W;
647 break;
648 case 040: /* VEX.W is a don't care */
649 ins->rex &= ~REX_W;
650 break;
651 case 060:
652 break;
653 }
654
655 /* The 010 bit of vexwlp is set if VEX.L is ignored */
656 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
657 return false;
658
659 if (c == 0270) {
660 if (prefix->vex_v != 0)
661 return false;
662 } else {
663 opx->segment |= SEG_RMREG;
664 opx->basereg = prefix->vex_v;
665 }
666 vex_ok = true;
667 break;
668 }
669
670 case 0271:
671 if (prefix->rep == 0xF3)
672 drep = P_XRELEASE;
673 break;
674
675 case 0272:
676 if (prefix->rep == 0xF2)
677 drep = P_XACQUIRE;
678 else if (prefix->rep == 0xF3)
679 drep = P_XRELEASE;
680 break;
681
682 case 0273:
683 if (prefix->lock == 0xF0) {
684 if (prefix->rep == 0xF2)
685 drep = P_XACQUIRE;
686 else if (prefix->rep == 0xF3)
687 drep = P_XRELEASE;
688 }
689 break;
690
691 case 0310:
692 if (asize != 16)
693 return false;
694 else
695 a_used = true;
696 break;
697
698 case 0311:
699 if (asize != 32)
700 return false;
701 else
702 a_used = true;
703 break;
704
705 case 0312:
706 if (asize != segsize)
707 return false;
708 else
709 a_used = true;
710 break;
711
712 case 0313:
713 if (asize != 64)
714 return false;
715 else
716 a_used = true;
717 break;
718
719 case 0314:
720 if (prefix->rex & REX_B)
721 return false;
722 break;
723
724 case 0315:
725 if (prefix->rex & REX_X)
726 return false;
727 break;
728
729 case 0316:
730 if (prefix->rex & REX_R)
731 return false;
732 break;
733
734 case 0317:
735 if (prefix->rex & REX_W)
736 return false;
737 break;
738
739 case 0320:
740 if (osize != 16)
741 return false;
742 else
743 o_used = true;
744 break;
745
746 case 0321:
747 if (osize != 32)
748 return false;
749 else
750 o_used = true;
751 break;
752
753 case 0322:
754 if (osize != (segsize == 16) ? 16 : 32)
755 return false;
756 else
757 o_used = true;
758 break;
759
760 case 0323:
761 ins->rex |= REX_W; /* 64-bit only instruction */
762 osize = 64;
763 o_used = true;
764 break;
765
766 case 0324:
767 if (osize != 64)
768 return false;
769 o_used = true;
770 break;
771
772 case 0325:
773 ins->rex |= REX_NH;
774 break;
775
776 case 0330:
777 {
778 int t = *r++, d = *data++;
779 if (d < t || d > t + 15)
780 return false;
781 else
782 ins->condition = d - t;
783 break;
784 }
785
786 case 0326:
787 if (prefix->rep == 0xF3)
788 return false;
789 break;
790
791 case 0331:
792 if (prefix->rep)
793 return false;
794 break;
795
796 case 0332:
797 if (prefix->rep != 0xF2)
798 return false;
799 drep = 0;
800 break;
801
802 case 0333:
803 if (prefix->rep != 0xF3)
804 return false;
805 drep = 0;
806 break;
807
808 case 0334:
809 if (lock) {
810 ins->rex |= REX_R;
811 lock = 0;
812 }
813 break;
814
815 case 0335:
816 if (drep == P_REP)
817 drep = P_REPE;
818 break;
819
820 case 0336:
821 case 0337:
822 break;
823
824 case 0340:
825 return false;
826
827 case 0341:
828 if (prefix->wait != 0x9B)
829 return false;
830 dwait = 0;
831 break;
832
833 case4(0344):
834 ins->oprs[0].basereg = (*data++ >> 3) & 7;
835 break;
836
837 case 0360:
838 if (prefix->osp || prefix->rep)
839 return false;
840 break;
841
842 case 0361:
843 if (!prefix->osp || prefix->rep)
844 return false;
845 o_used = true;
846 break;
847
848 case 0362:
849 if (prefix->osp || prefix->rep != 0xf2)
850 return false;
851 drep = 0;
852 break;
853
854 case 0363:
855 if (prefix->osp || prefix->rep != 0xf3)
856 return false;
857 drep = 0;
858 break;
859
860 case 0364:
861 if (prefix->osp)
862 return false;
863 break;
864
865 case 0365:
866 if (prefix->asp)
867 return false;
868 break;
869
870 case 0366:
871 if (!prefix->osp)
872 return false;
873 o_used = true;
874 break;
875
876 case 0367:
877 if (!prefix->asp)
878 return false;
879 a_used = true;
880 break;
881
882 case 0370:
883 case 0371:
884 break;
885
886 case 0374:
887 eat = EA_XMMVSIB;
888 break;
889
890 case 0375:
891 eat = EA_YMMVSIB;
892 break;
893
894 default:
895 return false; /* Unknown code */
896 }
897 }
898
899 if (!vex_ok && (ins->rex & REX_V))
900 return false;
901
902 /* REX cannot be combined with VEX */
903 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
904 return false;
905
906 /*
907 * Check for unused rep or a/o prefixes.
908 */
909 for (i = 0; i < t->operands; i++) {
910 if (ins->oprs[i].segment != SEG_RMREG)
911 a_used = true;
912 }
913
914 if (lock) {
915 if (ins->prefixes[PPS_LOCK])
916 return false;
917 ins->prefixes[PPS_LOCK] = P_LOCK;
918 }
919 if (drep) {
920 if (ins->prefixes[PPS_REP])
921 return false;
922 ins->prefixes[PPS_REP] = drep;
923 }
924 ins->prefixes[PPS_WAIT] = dwait;
925 if (!o_used) {
926 if (osize != ((segsize == 16) ? 16 : 32)) {
927 enum prefixes pfx = 0;
928
929 switch (osize) {
930 case 16:
931 pfx = P_O16;
932 break;
933 case 32:
934 pfx = P_O32;
935 break;
936 case 64:
937 pfx = P_O64;
938 break;
939 }
940
941 if (ins->prefixes[PPS_OSIZE])
942 return false;
943 ins->prefixes[PPS_OSIZE] = pfx;
944 }
945 }
946 if (!a_used && asize != segsize) {
947 if (ins->prefixes[PPS_ASIZE])
948 return false;
949 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
950 }
951
952 /* Fix: check for redundant REX prefixes */
953
954 return data - origdata;
955 }
956
957 /* Condition names for disassembly, sorted by x86 code */
958 static const char * const condition_name[16] = {
959 "o", "no", "c", "nc", "z", "nz", "na", "a",
960 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
961 };
962
963 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
964 int32_t offset, int autosync, uint32_t prefer)
965 {
966 const struct itemplate * const *p, * const *best_p;
967 const struct disasm_index *ix;
968 uint8_t *dp;
969 int length, best_length = 0;
970 char *segover;
971 int i, slen, colon, n;
972 uint8_t *origdata;
973 int works;
974 insn tmp_ins, ins;
975 uint32_t goodness, best;
976 int best_pref;
977 struct prefix_info prefix;
978 bool end_prefix;
979
980 memset(&ins, 0, sizeof ins);
981
982 /*
983 * Scan for prefixes.
984 */
985 memset(&prefix, 0, sizeof prefix);
986 prefix.asize = segsize;
987 prefix.osize = (segsize == 64) ? 32 : segsize;
988 segover = NULL;
989 origdata = data;
990
991 ix = itable;
992
993 end_prefix = false;
994 while (!end_prefix) {
995 switch (*data) {
996 case 0xF2:
997 case 0xF3:
998 prefix.rep = *data++;
999 break;
1000
1001 case 0x9B:
1002 prefix.wait = *data++;
1003 break;
1004
1005 case 0xF0:
1006 prefix.lock = *data++;
1007 break;
1008
1009 case 0x2E:
1010 segover = "cs", prefix.seg = *data++;
1011 break;
1012 case 0x36:
1013 segover = "ss", prefix.seg = *data++;
1014 break;
1015 case 0x3E:
1016 segover = "ds", prefix.seg = *data++;
1017 break;
1018 case 0x26:
1019 segover = "es", prefix.seg = *data++;
1020 break;
1021 case 0x64:
1022 segover = "fs", prefix.seg = *data++;
1023 break;
1024 case 0x65:
1025 segover = "gs", prefix.seg = *data++;
1026 break;
1027
1028 case 0x66:
1029 prefix.osize = (segsize == 16) ? 32 : 16;
1030 prefix.osp = *data++;
1031 break;
1032 case 0x67:
1033 prefix.asize = (segsize == 32) ? 16 : 32;
1034 prefix.asp = *data++;
1035 break;
1036
1037 case 0xC4:
1038 case 0xC5:
1039 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1040 prefix.vex[0] = *data++;
1041 prefix.vex[1] = *data++;
1042
1043 prefix.rex = REX_V;
1044 prefix.vex_c = RV_VEX;
1045
1046 if (prefix.vex[0] == 0xc4) {
1047 prefix.vex[2] = *data++;
1048 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1049 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1050 prefix.vex_m = prefix.vex[1] & 0x1f;
1051 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1052 prefix.vex_lp = prefix.vex[2] & 7;
1053 } else {
1054 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1055 prefix.vex_m = 1;
1056 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1057 prefix.vex_lp = prefix.vex[1] & 7;
1058 }
1059
1060 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1061 }
1062 end_prefix = true;
1063 break;
1064
1065 case 0x8F:
1066 if ((data[1] & 030) != 0 &&
1067 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1068 prefix.vex[0] = *data++;
1069 prefix.vex[1] = *data++;
1070 prefix.vex[2] = *data++;
1071
1072 prefix.rex = REX_V;
1073 prefix.vex_c = RV_XOP;
1074
1075 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1076 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1077 prefix.vex_m = prefix.vex[1] & 0x1f;
1078 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1079 prefix.vex_lp = prefix.vex[2] & 7;
1080
1081 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1082 }
1083 end_prefix = true;
1084 break;
1085
1086 case REX_P + 0x0:
1087 case REX_P + 0x1:
1088 case REX_P + 0x2:
1089 case REX_P + 0x3:
1090 case REX_P + 0x4:
1091 case REX_P + 0x5:
1092 case REX_P + 0x6:
1093 case REX_P + 0x7:
1094 case REX_P + 0x8:
1095 case REX_P + 0x9:
1096 case REX_P + 0xA:
1097 case REX_P + 0xB:
1098 case REX_P + 0xC:
1099 case REX_P + 0xD:
1100 case REX_P + 0xE:
1101 case REX_P + 0xF:
1102 if (segsize == 64) {
1103 prefix.rex = *data++;
1104 if (prefix.rex & REX_W)
1105 prefix.osize = 64;
1106 }
1107 end_prefix = true;
1108 break;
1109
1110 default:
1111 end_prefix = true;
1112 break;
1113 }
1114 }
1115
1116 best = -1; /* Worst possible */
1117 best_p = NULL;
1118 best_pref = INT_MAX;
1119
1120 if (!ix)
1121 return 0; /* No instruction table at all... */
1122
1123 dp = data;
1124 ix += *dp++;
1125 while (ix->n == -1) {
1126 ix = (const struct disasm_index *)ix->p + *dp++;
1127 }
1128
1129 p = (const struct itemplate * const *)ix->p;
1130 for (n = ix->n; n; n--, p++) {
1131 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1132 works = true;
1133 /*
1134 * Final check to make sure the types of r/m match up.
1135 * XXX: Need to make sure this is actually correct.
1136 */
1137 for (i = 0; i < (*p)->operands; i++) {
1138 if (!((*p)->opd[i] & SAME_AS) &&
1139 (
1140 /* If it's a mem-only EA but we have a
1141 register, die. */
1142 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1143 is_class(MEMORY, (*p)->opd[i])) ||
1144 /* If it's a reg-only EA but we have a memory
1145 ref, die. */
1146 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1147 !(REG_EA & ~(*p)->opd[i]) &&
1148 !((*p)->opd[i] & REG_SMASK)) ||
1149 /* Register type mismatch (eg FS vs REG_DESS):
1150 die. */
1151 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1152 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1153 !whichreg((*p)->opd[i],
1154 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1155 )) {
1156 works = false;
1157 break;
1158 }
1159 }
1160
1161 /*
1162 * Note: we always prefer instructions which incorporate
1163 * prefixes in the instructions themselves. This is to allow
1164 * e.g. PAUSE to be preferred to REP NOP, and deal with
1165 * MMX/SSE instructions where prefixes are used to select
1166 * between MMX and SSE register sets or outright opcode
1167 * selection.
1168 */
1169 if (works) {
1170 int i, nprefix;
1171 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1172 nprefix = 0;
1173 for (i = 0; i < MAXPREFIX; i++)
1174 if (tmp_ins.prefixes[i])
1175 nprefix++;
1176 if (nprefix < best_pref ||
1177 (nprefix == best_pref && goodness < best)) {
1178 /* This is the best one found so far */
1179 best = goodness;
1180 best_p = p;
1181 best_pref = nprefix;
1182 best_length = length;
1183 ins = tmp_ins;
1184 }
1185 }
1186 }
1187 }
1188
1189 if (!best_p)
1190 return 0; /* no instruction was matched */
1191
1192 /* Pick the best match */
1193 p = best_p;
1194 length = best_length;
1195
1196 slen = 0;
1197
1198 /* TODO: snprintf returns the value that the string would have if
1199 * the buffer were long enough, and not the actual length of
1200 * the returned string, so each instance of using the return
1201 * value of snprintf should actually be checked to assure that
1202 * the return value is "sane." Maybe a macro wrapper could
1203 * be used for that purpose.
1204 */
1205 for (i = 0; i < MAXPREFIX; i++) {
1206 const char *prefix = prefix_name(ins.prefixes[i]);
1207 if (prefix)
1208 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1209 }
1210
1211 i = (*p)->opcode;
1212 if (i >= FIRST_COND_OPCODE)
1213 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1214 nasm_insn_names[i], condition_name[ins.condition]);
1215 else
1216 slen += snprintf(output + slen, outbufsize - slen, "%s",
1217 nasm_insn_names[i]);
1218
1219 colon = false;
1220 length += data - origdata; /* fix up for prefixes */
1221 for (i = 0; i < (*p)->operands; i++) {
1222 opflags_t t = (*p)->opd[i];
1223 const operand *o = &ins.oprs[i];
1224 int64_t offs;
1225
1226 if (t & SAME_AS) {
1227 o = &ins.oprs[t & ~SAME_AS];
1228 t = (*p)->opd[t & ~SAME_AS];
1229 }
1230
1231 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1232
1233 offs = o->offset;
1234 if (o->segment & SEG_RELATIVE) {
1235 offs += offset + length;
1236 /*
1237 * sort out wraparound
1238 */
1239 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1240 offs &= 0xffff;
1241 else if (segsize != 64)
1242 offs &= 0xffffffff;
1243
1244 /*
1245 * add sync marker, if autosync is on
1246 */
1247 if (autosync)
1248 add_sync(offs, 0L);
1249 }
1250
1251 if (t & COLON)
1252 colon = true;
1253 else
1254 colon = false;
1255
1256 if ((t & (REGISTER | FPUREG)) ||
1257 (o->segment & SEG_RMREG)) {
1258 enum reg_enum reg;
1259 reg = whichreg(t, o->basereg, ins.rex);
1260 if (t & TO)
1261 slen += snprintf(output + slen, outbufsize - slen, "to ");
1262 slen += snprintf(output + slen, outbufsize - slen, "%s",
1263 nasm_reg_names[reg-EXPR_REG_START]);
1264 } else if (!(UNITY & ~t)) {
1265 output[slen++] = '1';
1266 } else if (t & IMMEDIATE) {
1267 if (t & BITS8) {
1268 slen +=
1269 snprintf(output + slen, outbufsize - slen, "byte ");
1270 if (o->segment & SEG_SIGNED) {
1271 if (offs < 0) {
1272 offs *= -1;
1273 output[slen++] = '-';
1274 } else
1275 output[slen++] = '+';
1276 }
1277 } else if (t & BITS16) {
1278 slen +=
1279 snprintf(output + slen, outbufsize - slen, "word ");
1280 } else if (t & BITS32) {
1281 slen +=
1282 snprintf(output + slen, outbufsize - slen, "dword ");
1283 } else if (t & BITS64) {
1284 slen +=
1285 snprintf(output + slen, outbufsize - slen, "qword ");
1286 } else if (t & NEAR) {
1287 slen +=
1288 snprintf(output + slen, outbufsize - slen, "near ");
1289 } else if (t & SHORT) {
1290 slen +=
1291 snprintf(output + slen, outbufsize - slen, "short ");
1292 }
1293 slen +=
1294 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1295 offs);
1296 } else if (!(MEM_OFFS & ~t)) {
1297 slen +=
1298 snprintf(output + slen, outbufsize - slen,
1299 "[%s%s%s0x%"PRIx64"]",
1300 (segover ? segover : ""),
1301 (segover ? ":" : ""),
1302 (o->disp_size == 64 ? "qword " :
1303 o->disp_size == 32 ? "dword " :
1304 o->disp_size == 16 ? "word " : ""), offs);
1305 segover = NULL;
1306 } else if (is_class(REGMEM, t)) {
1307 int started = false;
1308 if (t & BITS8)
1309 slen +=
1310 snprintf(output + slen, outbufsize - slen, "byte ");
1311 if (t & BITS16)
1312 slen +=
1313 snprintf(output + slen, outbufsize - slen, "word ");
1314 if (t & BITS32)
1315 slen +=
1316 snprintf(output + slen, outbufsize - slen, "dword ");
1317 if (t & BITS64)
1318 slen +=
1319 snprintf(output + slen, outbufsize - slen, "qword ");
1320 if (t & BITS80)
1321 slen +=
1322 snprintf(output + slen, outbufsize - slen, "tword ");
1323 if (t & BITS128)
1324 slen +=
1325 snprintf(output + slen, outbufsize - slen, "oword ");
1326 if (t & BITS256)
1327 slen +=
1328 snprintf(output + slen, outbufsize - slen, "yword ");
1329 if (t & FAR)
1330 slen += snprintf(output + slen, outbufsize - slen, "far ");
1331 if (t & NEAR)
1332 slen +=
1333 snprintf(output + slen, outbufsize - slen, "near ");
1334 output[slen++] = '[';
1335 if (o->disp_size)
1336 slen += snprintf(output + slen, outbufsize - slen, "%s",
1337 (o->disp_size == 64 ? "qword " :
1338 o->disp_size == 32 ? "dword " :
1339 o->disp_size == 16 ? "word " :
1340 ""));
1341 if (o->eaflags & EAF_REL)
1342 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1343 if (segover) {
1344 slen +=
1345 snprintf(output + slen, outbufsize - slen, "%s:",
1346 segover);
1347 segover = NULL;
1348 }
1349 if (o->basereg != -1) {
1350 slen += snprintf(output + slen, outbufsize - slen, "%s",
1351 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1352 started = true;
1353 }
1354 if (o->indexreg != -1) {
1355 if (started)
1356 output[slen++] = '+';
1357 slen += snprintf(output + slen, outbufsize - slen, "%s",
1358 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1359 if (o->scale > 1)
1360 slen +=
1361 snprintf(output + slen, outbufsize - slen, "*%d",
1362 o->scale);
1363 started = true;
1364 }
1365
1366
1367 if (o->segment & SEG_DISP8) {
1368 const char *prefix;
1369 uint8_t offset = offs;
1370 if ((int8_t)offset < 0) {
1371 prefix = "-";
1372 offset = -offset;
1373 } else {
1374 prefix = "+";
1375 }
1376 slen +=
1377 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1378 prefix, offset);
1379 } else if (o->segment & SEG_DISP16) {
1380 const char *prefix;
1381 uint16_t offset = offs;
1382 if ((int16_t)offset < 0 && started) {
1383 offset = -offset;
1384 prefix = "-";
1385 } else {
1386 prefix = started ? "+" : "";
1387 }
1388 slen +=
1389 snprintf(output + slen, outbufsize - slen,
1390 "%s0x%"PRIx16"", prefix, offset);
1391 } else if (o->segment & SEG_DISP32) {
1392 if (prefix.asize == 64) {
1393 const char *prefix;
1394 uint64_t offset = (int64_t)(int32_t)offs;
1395 if ((int32_t)offs < 0 && started) {
1396 offset = -offset;
1397 prefix = "-";
1398 } else {
1399 prefix = started ? "+" : "";
1400 }
1401 slen +=
1402 snprintf(output + slen, outbufsize - slen,
1403 "%s0x%"PRIx64"", prefix, offset);
1404 } else {
1405 const char *prefix;
1406 uint32_t offset = offs;
1407 if ((int32_t) offset < 0 && started) {
1408 offset = -offset;
1409 prefix = "-";
1410 } else {
1411 prefix = started ? "+" : "";
1412 }
1413 slen +=
1414 snprintf(output + slen, outbufsize - slen,
1415 "%s0x%"PRIx32"", prefix, offset);
1416 }
1417 }
1418 output[slen++] = ']';
1419 } else {
1420 slen +=
1421 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1422 i);
1423 }
1424 }
1425 output[slen] = '\0';
1426 if (segover) { /* unused segment override */
1427 char *p = output;
1428 int count = slen + 1;
1429 while (count--)
1430 p[count + 3] = p[count];
1431 strncpy(output, segover, 2);
1432 output[2] = ' ';
1433 }
1434 return length;
1435 }
1436
1437 /*
1438 * This is called when we don't have a complete instruction. If it
1439 * is a standalone *single-byte* prefix show it as such, otherwise
1440 * print it as a literal.
1441 */
1442 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1443 {
1444 uint8_t byte = *data;
1445 const char *str = NULL;
1446
1447 switch (byte) {
1448 case 0xF2:
1449 str = "repne";
1450 break;
1451 case 0xF3:
1452 str = "rep";
1453 break;
1454 case 0x9B:
1455 str = "wait";
1456 break;
1457 case 0xF0:
1458 str = "lock";
1459 break;
1460 case 0x2E:
1461 str = "cs";
1462 break;
1463 case 0x36:
1464 str = "ss";
1465 break;
1466 case 0x3E:
1467 str = "ss";
1468 break;
1469 case 0x26:
1470 str = "es";
1471 break;
1472 case 0x64:
1473 str = "fs";
1474 break;
1475 case 0x65:
1476 str = "gs";
1477 break;
1478 case 0x66:
1479 str = (segsize == 16) ? "o32" : "o16";
1480 break;
1481 case 0x67:
1482 str = (segsize == 32) ? "a16" : "a32";
1483 break;
1484 case REX_P + 0x0:
1485 case REX_P + 0x1:
1486 case REX_P + 0x2:
1487 case REX_P + 0x3:
1488 case REX_P + 0x4:
1489 case REX_P + 0x5:
1490 case REX_P + 0x6:
1491 case REX_P + 0x7:
1492 case REX_P + 0x8:
1493 case REX_P + 0x9:
1494 case REX_P + 0xA:
1495 case REX_P + 0xB:
1496 case REX_P + 0xC:
1497 case REX_P + 0xD:
1498 case REX_P + 0xE:
1499 case REX_P + 0xF:
1500 if (segsize == 64) {
1501 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1502 (byte == REX_P) ? "" : ".",
1503 (byte & REX_W) ? "w" : "",
1504 (byte & REX_R) ? "r" : "",
1505 (byte & REX_X) ? "x" : "",
1506 (byte & REX_B) ? "b" : "");
1507 break;
1508 }
1509 /* else fall through */
1510 default:
1511 snprintf(output, outbufsize, "db 0x%02x", byte);
1512 break;
1513 }
1514
1515 if (str)
1516 snprintf(output, outbufsize, "%s", str);
1517
1518 return 1;
1519 }
The Netwide Assembler