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output: elf64 -- increase .symtab and .rel* alignment to 8
[nasm.git] / assemble.c
blob4976c4664cd8a8e443e23e2373f6b806d27eb2e1
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2014 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * Bytecode specification
38 * ----------------------
39 *
40 *
41 * Codes Mnemonic Explanation
42 *
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
76 *
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
81 *
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
84 * cc 000 0mm
85 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
86 * and wlp is:
87 * 00 wwl lpp
88 * [l0] ll = 0 (.128, .lz)
89 * [l1] ll = 1 (.256)
90 * [l2] ll = 2 (.512)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
100 * [f3] pp = 2
101 * [f2] pp = 3
102 *
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
105 *
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
111 *
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
114 * 00 wwl lpp
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
118 *
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
123 *
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
125 *
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
176 */
177
178 #include "compiler.h"
179
180 #include <stdio.h>
181 #include <string.h>
182 #include <stdlib.h>
183 #include <inttypes.h>
184
185 #include "nasm.h"
186 #include "nasmlib.h"
187 #include "assemble.h"
188 #include "insns.h"
189 #include "tables.h"
190 #include "disp8.h"
191
192 enum match_result {
193 /*
194 * Matching errors. These should be sorted so that more specific
195 * errors come later in the sequence.
196 */
197 MERR_INVALOP,
198 MERR_OPSIZEMISSING,
199 MERR_OPSIZEMISMATCH,
200 MERR_BRNUMMISMATCH,
201 MERR_BADCPU,
202 MERR_BADMODE,
203 MERR_BADHLE,
204 MERR_ENCMISMATCH,
205 MERR_BADBND,
206 MERR_BADREPNE,
207 /*
208 * Matching success; the conditional ones first
209 */
210 MOK_JUMP, /* Matching OK but needs jmp_match() */
211 MOK_GOOD /* Matching unconditionally OK */
212 };
213
214 typedef struct {
215 enum ea_type type; /* what kind of EA is this? */
216 int sib_present; /* is a SIB byte necessary? */
217 int bytes; /* # of bytes of offset needed */
218 int size; /* lazy - this is sib+bytes+1 */
219 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
220 int8_t disp8; /* compressed displacement for EVEX */
221 } ea;
222
223 #define GEN_SIB(scale, index, base) \
224 (((scale) << 6) | ((index) << 3) | ((base)))
225
226 #define GEN_MODRM(mod, reg, rm) \
227 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
228
229 static iflag_t cpu; /* cpu level received from nasm.c */
230 static efunc errfunc;
231 static struct ofmt *outfmt;
232 static ListGen *list;
233
234 static int64_t calcsize(int32_t, int64_t, int, insn *,
235 const struct itemplate *);
236 static void gencode(int32_t segment, int64_t offset, int bits,
237 insn * ins, const struct itemplate *temp,
238 int64_t insn_end);
239 static enum match_result find_match(const struct itemplate **tempp,
240 insn *instruction,
241 int32_t segment, int64_t offset, int bits);
242 static enum match_result matches(const struct itemplate *, insn *, int bits);
243 static opflags_t regflag(const operand *);
244 static int32_t regval(const operand *);
245 static int rexflags(int, opflags_t, int);
246 static int op_rexflags(const operand *, int);
247 static int op_evexflags(const operand *, int, uint8_t);
248 static void add_asp(insn *, int);
249
250 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
251
252 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
253 {
254 return ins->prefixes[pos] == prefix;
255 }
256
257 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
258 {
259 if (ins->prefixes[pos])
260 errfunc(ERR_NONFATAL, "invalid %s prefix",
261 prefix_name(ins->prefixes[pos]));
262 }
263
264 static const char *size_name(int size)
265 {
266 switch (size) {
267 case 1:
268 return "byte";
269 case 2:
270 return "word";
271 case 4:
272 return "dword";
273 case 8:
274 return "qword";
275 case 10:
276 return "tword";
277 case 16:
278 return "oword";
279 case 32:
280 return "yword";
281 case 64:
282 return "zword";
283 default:
284 return "???";
285 }
286 }
287
288 static void warn_overflow(int pass, int size)
289 {
290 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
291 "%s data exceeds bounds", size_name(size));
292 }
293
294 static void warn_overflow_const(int64_t data, int size)
295 {
296 if (overflow_general(data, size))
297 warn_overflow(ERR_PASS1, size);
298 }
299
300 static void warn_overflow_opd(const struct operand *o, int size)
301 {
302 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
303 if (overflow_general(o->offset, size))
304 warn_overflow(ERR_PASS2, size);
305 }
306 }
307
308 /*
309 * This routine wrappers the real output format's output routine,
310 * in order to pass a copy of the data off to the listing file
311 * generator at the same time.
312 */
313 static void out(int64_t offset, int32_t segto, const void *data,
314 enum out_type type, uint64_t size,
315 int32_t segment, int32_t wrt)
316 {
317 static int32_t lineno = 0; /* static!!! */
318 static char *lnfname = NULL;
319 uint8_t p[8];
320
321 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
322 /*
323 * This is a non-relocated address, and we're going to
324 * convert it into RAWDATA format.
325 */
326 uint8_t *q = p;
327
328 size = abs((int)size);
329 if (size > 8) {
330 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
331 return;
332 }
333
334 WRITEADDR(q, *(int64_t *)data, size);
335 data = p;
336 type = OUT_RAWDATA;
337 }
338
339 list->output(offset, data, type, size);
340
341 /*
342 * this call to src_get determines when we call the
343 * debug-format-specific "linenum" function
344 * it updates lineno and lnfname to the current values
345 * returning 0 if "same as last time", -2 if lnfname
346 * changed, and the amount by which lineno changed,
347 * if it did. thus, these variables must be static
348 */
349
350 if (src_get(&lineno, &lnfname))
351 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
352
353 outfmt->output(segto, data, type, size, segment, wrt);
354 }
355
356 static void out_imm8(int64_t offset, int32_t segment,
357 struct operand *opx, int asize)
358 {
359 if (opx->segment != NO_SEG) {
360 uint64_t data = opx->offset;
361 out(offset, segment, &data, OUT_ADDRESS, asize, opx->segment, opx->wrt);
362 } else {
363 uint8_t byte = opx->offset;
364 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
365 }
366 }
367
368 static bool jmp_match(int32_t segment, int64_t offset, int bits,
369 insn * ins, const struct itemplate *temp)
370 {
371 int64_t isize;
372 const uint8_t *code = temp->code;
373 uint8_t c = code[0];
374 bool is_byte;
375
376 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
377 return false;
378 if (!optimizing)
379 return false;
380 if (optimizing < 0 && c == 0371)
381 return false;
382
383 isize = calcsize(segment, offset, bits, ins, temp);
384
385 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
386 /* Be optimistic in pass 1 */
387 return true;
388
389 if (ins->oprs[0].segment != segment)
390 return false;
391
392 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
393 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
394
395 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
396 /* jmp short (opcode eb) cannot be used with bnd prefix. */
397 ins->prefixes[PPS_REP] = P_none;
398 errfunc(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
399 "jmp short does not init bnd regs - bnd prefix dropped.");
400 }
401
402 return is_byte;
403 }
404
405 int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
406 insn * instruction, struct ofmt *output, efunc error,
407 ListGen * listgen)
408 {
409 const struct itemplate *temp;
410 int j;
411 enum match_result m;
412 int64_t insn_end;
413 int32_t itimes;
414 int64_t start = offset;
415 int64_t wsize; /* size for DB etc. */
416
417 errfunc = error; /* to pass to other functions */
418 cpu = cp;
419 outfmt = output; /* likewise */
420 list = listgen; /* and again */
421
422 wsize = idata_bytes(instruction->opcode);
423 if (wsize == -1)
424 return 0;
425
426 if (wsize) {
427 extop *e;
428 int32_t t = instruction->times;
429 if (t < 0)
430 errfunc(ERR_PANIC,
431 "instruction->times < 0 (%ld) in assemble()", t);
432
433 while (t--) { /* repeat TIMES times */
434 list_for_each(e, instruction->eops) {
435 if (e->type == EOT_DB_NUMBER) {
436 if (wsize > 8) {
437 errfunc(ERR_NONFATAL,
438 "integer supplied to a DT, DO or DY"
439 " instruction");
440 } else {
441 out(offset, segment, &e->offset,
442 OUT_ADDRESS, wsize, e->segment, e->wrt);
443 offset += wsize;
444 }
445 } else if (e->type == EOT_DB_STRING ||
446 e->type == EOT_DB_STRING_FREE) {
447 int align;
448
449 out(offset, segment, e->stringval,
450 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
451 align = e->stringlen % wsize;
452
453 if (align) {
454 align = wsize - align;
455 out(offset, segment, zero_buffer,
456 OUT_RAWDATA, align, NO_SEG, NO_SEG);
457 }
458 offset += e->stringlen + align;
459 }
460 }
461 if (t > 0 && t == instruction->times - 1) {
462 /*
463 * Dummy call to list->output to give the offset to the
464 * listing module.
465 */
466 list->output(offset, NULL, OUT_RAWDATA, 0);
467 list->uplevel(LIST_TIMES);
468 }
469 }
470 if (instruction->times > 1)
471 list->downlevel(LIST_TIMES);
472 return offset - start;
473 }
474
475 if (instruction->opcode == I_INCBIN) {
476 const char *fname = instruction->eops->stringval;
477 FILE *fp;
478
479 fp = fopen(fname, "rb");
480 if (!fp) {
481 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
482 fname);
483 } else if (fseek(fp, 0L, SEEK_END) < 0) {
484 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
485 fname);
486 fclose(fp);
487 } else {
488 static char buf[4096];
489 size_t t = instruction->times;
490 size_t base = 0;
491 size_t len;
492
493 len = ftell(fp);
494 if (instruction->eops->next) {
495 base = instruction->eops->next->offset;
496 len -= base;
497 if (instruction->eops->next->next &&
498 len > (size_t)instruction->eops->next->next->offset)
499 len = (size_t)instruction->eops->next->next->offset;
500 }
501 /*
502 * Dummy call to list->output to give the offset to the
503 * listing module.
504 */
505 list->output(offset, NULL, OUT_RAWDATA, 0);
506 list->uplevel(LIST_INCBIN);
507 while (t--) {
508 size_t l;
509
510 fseek(fp, base, SEEK_SET);
511 l = len;
512 while (l > 0) {
513 int32_t m;
514 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
515 if (!m) {
516 /*
517 * This shouldn't happen unless the file
518 * actually changes while we are reading
519 * it.
520 */
521 error(ERR_NONFATAL,
522 "`incbin': unexpected EOF while"
523 " reading file `%s'", fname);
524 t = 0; /* Try to exit cleanly */
525 break;
526 }
527 out(offset, segment, buf, OUT_RAWDATA, m,
528 NO_SEG, NO_SEG);
529 l -= m;
530 }
531 }
532 list->downlevel(LIST_INCBIN);
533 if (instruction->times > 1) {
534 /*
535 * Dummy call to list->output to give the offset to the
536 * listing module.
537 */
538 list->output(offset, NULL, OUT_RAWDATA, 0);
539 list->uplevel(LIST_TIMES);
540 list->downlevel(LIST_TIMES);
541 }
542 fclose(fp);
543 return instruction->times * len;
544 }
545 return 0; /* if we're here, there's an error */
546 }
547
548 /* Check to see if we need an address-size prefix */
549 add_asp(instruction, bits);
550
551 m = find_match(&temp, instruction, segment, offset, bits);
552
553 if (m == MOK_GOOD) {
554 /* Matches! */
555 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
556 itimes = instruction->times;
557 if (insn_size < 0) /* shouldn't be, on pass two */
558 error(ERR_PANIC, "errors made it through from pass one");
559 else
560 while (itimes--) {
561 for (j = 0; j < MAXPREFIX; j++) {
562 uint8_t c = 0;
563 switch (instruction->prefixes[j]) {
564 case P_WAIT:
565 c = 0x9B;
566 break;
567 case P_LOCK:
568 c = 0xF0;
569 break;
570 case P_REPNE:
571 case P_REPNZ:
572 case P_XACQUIRE:
573 case P_BND:
574 c = 0xF2;
575 break;
576 case P_REPE:
577 case P_REPZ:
578 case P_REP:
579 case P_XRELEASE:
580 c = 0xF3;
581 break;
582 case R_CS:
583 if (bits == 64) {
584 error(ERR_WARNING | ERR_PASS2,
585 "cs segment base generated, but will be ignored in 64-bit mode");
586 }
587 c = 0x2E;
588 break;
589 case R_DS:
590 if (bits == 64) {
591 error(ERR_WARNING | ERR_PASS2,
592 "ds segment base generated, but will be ignored in 64-bit mode");
593 }
594 c = 0x3E;
595 break;
596 case R_ES:
597 if (bits == 64) {
598 error(ERR_WARNING | ERR_PASS2,
599 "es segment base generated, but will be ignored in 64-bit mode");
600 }
601 c = 0x26;
602 break;
603 case R_FS:
604 c = 0x64;
605 break;
606 case R_GS:
607 c = 0x65;
608 break;
609 case R_SS:
610 if (bits == 64) {
611 error(ERR_WARNING | ERR_PASS2,
612 "ss segment base generated, but will be ignored in 64-bit mode");
613 }
614 c = 0x36;
615 break;
616 case R_SEGR6:
617 case R_SEGR7:
618 error(ERR_NONFATAL,
619 "segr6 and segr7 cannot be used as prefixes");
620 break;
621 case P_A16:
622 if (bits == 64) {
623 error(ERR_NONFATAL,
624 "16-bit addressing is not supported "
625 "in 64-bit mode");
626 } else if (bits != 16)
627 c = 0x67;
628 break;
629 case P_A32:
630 if (bits != 32)
631 c = 0x67;
632 break;
633 case P_A64:
634 if (bits != 64) {
635 error(ERR_NONFATAL,
636 "64-bit addressing is only supported "
637 "in 64-bit mode");
638 }
639 break;
640 case P_ASP:
641 c = 0x67;
642 break;
643 case P_O16:
644 if (bits != 16)
645 c = 0x66;
646 break;
647 case P_O32:
648 if (bits == 16)
649 c = 0x66;
650 break;
651 case P_O64:
652 /* REX.W */
653 break;
654 case P_OSP:
655 c = 0x66;
656 break;
657 case P_EVEX:
658 case P_VEX3:
659 case P_VEX2:
660 case P_NOBND:
661 case P_none:
662 break;
663 default:
664 error(ERR_PANIC, "invalid instruction prefix");
665 }
666 if (c != 0) {
667 out(offset, segment, &c, OUT_RAWDATA, 1,
668 NO_SEG, NO_SEG);
669 offset++;
670 }
671 }
672 insn_end = offset + insn_size;
673 gencode(segment, offset, bits, instruction,
674 temp, insn_end);
675 offset += insn_size;
676 if (itimes > 0 && itimes == instruction->times - 1) {
677 /*
678 * Dummy call to list->output to give the offset to the
679 * listing module.
680 */
681 list->output(offset, NULL, OUT_RAWDATA, 0);
682 list->uplevel(LIST_TIMES);
683 }
684 }
685 if (instruction->times > 1)
686 list->downlevel(LIST_TIMES);
687 return offset - start;
688 } else {
689 /* No match */
690 switch (m) {
691 case MERR_OPSIZEMISSING:
692 error(ERR_NONFATAL, "operation size not specified");
693 break;
694 case MERR_OPSIZEMISMATCH:
695 error(ERR_NONFATAL, "mismatch in operand sizes");
696 break;
697 case MERR_BRNUMMISMATCH:
698 error(ERR_NONFATAL,
699 "mismatch in the number of broadcasting elements");
700 break;
701 case MERR_BADCPU:
702 error(ERR_NONFATAL, "no instruction for this cpu level");
703 break;
704 case MERR_BADMODE:
705 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
706 bits);
707 break;
708 case MERR_ENCMISMATCH:
709 error(ERR_NONFATAL, "specific encoding scheme not available");
710 break;
711 case MERR_BADBND:
712 error(ERR_NONFATAL, "bnd prefix is not allowed");
713 break;
714 case MERR_BADREPNE:
715 error(ERR_NONFATAL, "%s prefix is not allowed",
716 (has_prefix(instruction, PPS_REP, P_REPNE) ?
717 "repne" : "repnz"));
718 break;
719 default:
720 error(ERR_NONFATAL,
721 "invalid combination of opcode and operands");
722 break;
723 }
724 }
725 return 0;
726 }
727
728 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
729 insn * instruction, efunc error)
730 {
731 const struct itemplate *temp;
732 enum match_result m;
733
734 errfunc = error; /* to pass to other functions */
735 cpu = cp;
736
737 if (instruction->opcode == I_none)
738 return 0;
739
740 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
741 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
742 instruction->opcode == I_DT || instruction->opcode == I_DO ||
743 instruction->opcode == I_DY) {
744 extop *e;
745 int32_t isize, osize, wsize;
746
747 isize = 0;
748 wsize = idata_bytes(instruction->opcode);
749
750 list_for_each(e, instruction->eops) {
751 int32_t align;
752
753 osize = 0;
754 if (e->type == EOT_DB_NUMBER) {
755 osize = 1;
756 warn_overflow_const(e->offset, wsize);
757 } else if (e->type == EOT_DB_STRING ||
758 e->type == EOT_DB_STRING_FREE)
759 osize = e->stringlen;
760
761 align = (-osize) % wsize;
762 if (align < 0)
763 align += wsize;
764 isize += osize + align;
765 }
766 return isize * instruction->times;
767 }
768
769 if (instruction->opcode == I_INCBIN) {
770 const char *fname = instruction->eops->stringval;
771 FILE *fp;
772 int64_t val = 0;
773 size_t len;
774
775 fp = fopen(fname, "rb");
776 if (!fp)
777 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
778 fname);
779 else if (fseek(fp, 0L, SEEK_END) < 0)
780 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
781 fname);
782 else {
783 len = ftell(fp);
784 if (instruction->eops->next) {
785 len -= instruction->eops->next->offset;
786 if (instruction->eops->next->next &&
787 len > (size_t)instruction->eops->next->next->offset) {
788 len = (size_t)instruction->eops->next->next->offset;
789 }
790 }
791 val = instruction->times * len;
792 }
793 if (fp)
794 fclose(fp);
795 return val;
796 }
797
798 /* Check to see if we need an address-size prefix */
799 add_asp(instruction, bits);
800
801 m = find_match(&temp, instruction, segment, offset, bits);
802 if (m == MOK_GOOD) {
803 /* we've matched an instruction. */
804 int64_t isize;
805 int j;
806
807 isize = calcsize(segment, offset, bits, instruction, temp);
808 if (isize < 0)
809 return -1;
810 for (j = 0; j < MAXPREFIX; j++) {
811 switch (instruction->prefixes[j]) {
812 case P_A16:
813 if (bits != 16)
814 isize++;
815 break;
816 case P_A32:
817 if (bits != 32)
818 isize++;
819 break;
820 case P_O16:
821 if (bits != 16)
822 isize++;
823 break;
824 case P_O32:
825 if (bits == 16)
826 isize++;
827 break;
828 case P_A64:
829 case P_O64:
830 case P_EVEX:
831 case P_VEX3:
832 case P_VEX2:
833 case P_NOBND:
834 case P_none:
835 break;
836 default:
837 isize++;
838 break;
839 }
840 }
841 return isize * instruction->times;
842 } else {
843 return -1; /* didn't match any instruction */
844 }
845 }
846
847 static void bad_hle_warn(const insn * ins, uint8_t hleok)
848 {
849 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
850 enum whatwarn { w_none, w_lock, w_inval } ww;
851 static const enum whatwarn warn[2][4] =
852 {
853 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
854 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
855 };
856 unsigned int n;
857
858 n = (unsigned int)rep_pfx - P_XACQUIRE;
859 if (n > 1)
860 return; /* Not XACQUIRE/XRELEASE */
861
862 ww = warn[n][hleok];
863 if (!is_class(MEMORY, ins->oprs[0].type))
864 ww = w_inval; /* HLE requires operand 0 to be memory */
865
866 switch (ww) {
867 case w_none:
868 break;
869
870 case w_lock:
871 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
872 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
873 "%s with this instruction requires lock",
874 prefix_name(rep_pfx));
875 }
876 break;
877
878 case w_inval:
879 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
880 "%s invalid with this instruction",
881 prefix_name(rep_pfx));
882 break;
883 }
884 }
885
886 /* Common construct */
887 #define case3(x) case (x): case (x)+1: case (x)+2
888 #define case4(x) case3(x): case (x)+3
889
890 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
891 insn * ins, const struct itemplate *temp)
892 {
893 const uint8_t *codes = temp->code;
894 int64_t length = 0;
895 uint8_t c;
896 int rex_mask = ~0;
897 int op1, op2;
898 struct operand *opx;
899 uint8_t opex = 0;
900 enum ea_type eat;
901 uint8_t hleok = 0;
902 bool lockcheck = true;
903 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
904
905 ins->rex = 0; /* Ensure REX is reset */
906 eat = EA_SCALAR; /* Expect a scalar EA */
907 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
908
909 if (ins->prefixes[PPS_OSIZE] == P_O64)
910 ins->rex |= REX_W;
911
912 (void)segment; /* Don't warn that this parameter is unused */
913 (void)offset; /* Don't warn that this parameter is unused */
914
915 while (*codes) {
916 c = *codes++;
917 op1 = (c & 3) + ((opex & 1) << 2);
918 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
919 opx = &ins->oprs[op1];
920 opex = 0; /* For the next iteration */
921
922 switch (c) {
923 case4(01):
924 codes += c, length += c;
925 break;
926
927 case3(05):
928 opex = c;
929 break;
930
931 case4(010):
932 ins->rex |=
933 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
934 codes++, length++;
935 break;
936
937 case4(014):
938 /* this is an index reg of MIB operand */
939 mib_index = opx->basereg;
940 break;
941
942 case4(020):
943 case4(024):
944 length++;
945 break;
946
947 case4(030):
948 length += 2;
949 break;
950
951 case4(034):
952 if (opx->type & (BITS16 | BITS32 | BITS64))
953 length += (opx->type & BITS16) ? 2 : 4;
954 else
955 length += (bits == 16) ? 2 : 4;
956 break;
957
958 case4(040):
959 length += 4;
960 break;
961
962 case4(044):
963 length += ins->addr_size >> 3;
964 break;
965
966 case4(050):
967 length++;
968 break;
969
970 case4(054):
971 length += 8; /* MOV reg64/imm */
972 break;
973
974 case4(060):
975 length += 2;
976 break;
977
978 case4(064):
979 if (opx->type & (BITS16 | BITS32 | BITS64))
980 length += (opx->type & BITS16) ? 2 : 4;
981 else
982 length += (bits == 16) ? 2 : 4;
983 break;
984
985 case4(070):
986 length += 4;
987 break;
988
989 case4(074):
990 length += 2;
991 break;
992
993 case 0172:
994 case 0173:
995 codes++;
996 length++;
997 break;
998
999 case4(0174):
1000 length++;
1001 break;
1002
1003 case4(0240):
1004 ins->rex |= REX_EV;
1005 ins->vexreg = regval(opx);
1006 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
1007 ins->vex_cm = *codes++;
1008 ins->vex_wlp = *codes++;
1009 ins->evex_tuple = (*codes++ - 0300);
1010 break;
1011
1012 case 0250:
1013 ins->rex |= REX_EV;
1014 ins->vexreg = 0;
1015 ins->vex_cm = *codes++;
1016 ins->vex_wlp = *codes++;
1017 ins->evex_tuple = (*codes++ - 0300);
1018 break;
1019
1020 case4(0254):
1021 length += 4;
1022 break;
1023
1024 case4(0260):
1025 ins->rex |= REX_V;
1026 ins->vexreg = regval(opx);
1027 ins->vex_cm = *codes++;
1028 ins->vex_wlp = *codes++;
1029 break;
1030
1031 case 0270:
1032 ins->rex |= REX_V;
1033 ins->vexreg = 0;
1034 ins->vex_cm = *codes++;
1035 ins->vex_wlp = *codes++;
1036 break;
1037
1038 case3(0271):
1039 hleok = c & 3;
1040 break;
1041
1042 case4(0274):
1043 length++;
1044 break;
1045
1046 case4(0300):
1047 break;
1048
1049 case 0310:
1050 if (bits == 64)
1051 return -1;
1052 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1053 break;
1054
1055 case 0311:
1056 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1057 break;
1058
1059 case 0312:
1060 break;
1061
1062 case 0313:
1063 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1064 has_prefix(ins, PPS_ASIZE, P_A32))
1065 return -1;
1066 break;
1067
1068 case4(0314):
1069 break;
1070
1071 case 0320:
1072 {
1073 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1074 if (pfx == P_O16)
1075 break;
1076 if (pfx != P_none)
1077 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1078 else
1079 ins->prefixes[PPS_OSIZE] = P_O16;
1080 break;
1081 }
1082
1083 case 0321:
1084 {
1085 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1086 if (pfx == P_O32)
1087 break;
1088 if (pfx != P_none)
1089 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1090 else
1091 ins->prefixes[PPS_OSIZE] = P_O32;
1092 break;
1093 }
1094
1095 case 0322:
1096 break;
1097
1098 case 0323:
1099 rex_mask &= ~REX_W;
1100 break;
1101
1102 case 0324:
1103 ins->rex |= REX_W;
1104 break;
1105
1106 case 0325:
1107 ins->rex |= REX_NH;
1108 break;
1109
1110 case 0326:
1111 break;
1112
1113 case 0330:
1114 codes++, length++;
1115 break;
1116
1117 case 0331:
1118 break;
1119
1120 case 0332:
1121 case 0333:
1122 length++;
1123 break;
1124
1125 case 0334:
1126 ins->rex |= REX_L;
1127 break;
1128
1129 case 0335:
1130 break;
1131
1132 case 0336:
1133 if (!ins->prefixes[PPS_REP])
1134 ins->prefixes[PPS_REP] = P_REP;
1135 break;
1136
1137 case 0337:
1138 if (!ins->prefixes[PPS_REP])
1139 ins->prefixes[PPS_REP] = P_REPNE;
1140 break;
1141
1142 case 0340:
1143 if (ins->oprs[0].segment != NO_SEG)
1144 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1145 " quantity of BSS space");
1146 else
1147 length += ins->oprs[0].offset;
1148 break;
1149
1150 case 0341:
1151 if (!ins->prefixes[PPS_WAIT])
1152 ins->prefixes[PPS_WAIT] = P_WAIT;
1153 break;
1154
1155 case 0360:
1156 break;
1157
1158 case 0361:
1159 length++;
1160 break;
1161
1162 case 0364:
1163 case 0365:
1164 break;
1165
1166 case 0366:
1167 case 0367:
1168 length++;
1169 break;
1170
1171 case 0370:
1172 case 0371:
1173 break;
1174
1175 case 0373:
1176 length++;
1177 break;
1178
1179 case 0374:
1180 eat = EA_XMMVSIB;
1181 break;
1182
1183 case 0375:
1184 eat = EA_YMMVSIB;
1185 break;
1186
1187 case 0376:
1188 eat = EA_ZMMVSIB;
1189 break;
1190
1191 case4(0100):
1192 case4(0110):
1193 case4(0120):
1194 case4(0130):
1195 case4(0200):
1196 case4(0204):
1197 case4(0210):
1198 case4(0214):
1199 case4(0220):
1200 case4(0224):
1201 case4(0230):
1202 case4(0234):
1203 {
1204 ea ea_data;
1205 int rfield;
1206 opflags_t rflags;
1207 struct operand *opy = &ins->oprs[op2];
1208 struct operand *op_er_sae;
1209
1210 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1211
1212 if (c <= 0177) {
1213 /* pick rfield from operand b (opx) */
1214 rflags = regflag(opx);
1215 rfield = nasm_regvals[opx->basereg];
1216 } else {
1217 rflags = 0;
1218 rfield = c & 7;
1219 }
1220
1221 /* EVEX.b1 : evex_brerop contains the operand position */
1222 op_er_sae = (ins->evex_brerop >= 0 ?
1223 &ins->oprs[ins->evex_brerop] : NULL);
1224
1225 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1226 /* set EVEX.b */
1227 ins->evex_p[2] |= EVEX_P2B;
1228 if (op_er_sae->decoflags & ER) {
1229 /* set EVEX.RC (rounding control) */
1230 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1231 & EVEX_P2RC;
1232 }
1233 } else {
1234 /* set EVEX.L'L (vector length) */
1235 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1236 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1237 if (opy->decoflags & BRDCAST_MASK) {
1238 /* set EVEX.b */
1239 ins->evex_p[2] |= EVEX_P2B;
1240 }
1241 }
1242
1243 if (itemp_has(temp, IF_MIB)) {
1244 opy->eaflags |= EAF_MIB;
1245 /*
1246 * if a separate form of MIB (ICC style) is used,
1247 * the index reg info is merged into mem operand
1248 */
1249 if (mib_index != R_none) {
1250 opy->indexreg = mib_index;
1251 opy->scale = 1;
1252 opy->hintbase = mib_index;
1253 opy->hinttype = EAH_NOTBASE;
1254 }
1255 }
1256
1257 if (process_ea(opy, &ea_data, bits,
1258 rfield, rflags, ins) != eat) {
1259 errfunc(ERR_NONFATAL, "invalid effective address");
1260 return -1;
1261 } else {
1262 ins->rex |= ea_data.rex;
1263 length += ea_data.size;
1264 }
1265 }
1266 break;
1267
1268 default:
1269 errfunc(ERR_PANIC, "internal instruction table corrupt"
1270 ": instruction code \\%o (0x%02X) given", c, c);
1271 break;
1272 }
1273 }
1274
1275 ins->rex &= rex_mask;
1276
1277 if (ins->rex & REX_NH) {
1278 if (ins->rex & REX_H) {
1279 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1280 return -1;
1281 }
1282 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1283 }
1284
1285 switch (ins->prefixes[PPS_VEX]) {
1286 case P_EVEX:
1287 if (!(ins->rex & REX_EV))
1288 return -1;
1289 break;
1290 case P_VEX3:
1291 case P_VEX2:
1292 if (!(ins->rex & REX_V))
1293 return -1;
1294 break;
1295 default:
1296 break;
1297 }
1298
1299 if (ins->rex & (REX_V | REX_EV)) {
1300 int bad32 = REX_R|REX_W|REX_X|REX_B;
1301
1302 if (ins->rex & REX_H) {
1303 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1304 return -1;
1305 }
1306 switch (ins->vex_wlp & 060) {
1307 case 000:
1308 case 040:
1309 ins->rex &= ~REX_W;
1310 break;
1311 case 020:
1312 ins->rex |= REX_W;
1313 bad32 &= ~REX_W;
1314 break;
1315 case 060:
1316 /* Follow REX_W */
1317 break;
1318 }
1319
1320 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1321 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1322 return -1;
1323 } else if (!(ins->rex & REX_EV) &&
1324 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1325 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1326 return -1;
1327 }
1328 if (ins->rex & REX_EV)
1329 length += 4;
1330 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1331 ins->prefixes[PPS_VEX] == P_VEX3)
1332 length += 3;
1333 else
1334 length += 2;
1335 } else if (ins->rex & REX_MASK) {
1336 if (ins->rex & REX_H) {
1337 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1338 return -1;
1339 } else if (bits == 64) {
1340 length++;
1341 } else if ((ins->rex & REX_L) &&
1342 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1343 iflag_ffs(&cpu) >= IF_X86_64) {
1344 /* LOCK-as-REX.R */
1345 assert_no_prefix(ins, PPS_LOCK);
1346 lockcheck = false; /* Already errored, no need for warning */
1347 length++;
1348 } else {
1349 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1350 return -1;
1351 }
1352 }
1353
1354 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1355 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1356 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1357 "instruction is not lockable");
1358 }
1359
1360 bad_hle_warn(ins, hleok);
1361
1362 /*
1363 * when BND prefix is set by DEFAULT directive,
1364 * BND prefix is added to every appropriate instruction line
1365 * unless it is overridden by NOBND prefix.
1366 */
1367 if (globalbnd &&
1368 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1369 ins->prefixes[PPS_REP] = P_BND;
1370
1371 return length;
1372 }
1373
1374 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1375 {
1376 if (bits == 64) {
1377 if ((ins->rex & REX_MASK) &&
1378 !(ins->rex & (REX_V | REX_EV)) &&
1379 !ins->rex_done) {
1380 int rex = (ins->rex & REX_MASK) | REX_P;
1381 out(offset, segment, &rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1382 ins->rex_done = true;
1383 return 1;
1384 }
1385 }
1386
1387 return 0;
1388 }
1389
1390 static void gencode(int32_t segment, int64_t offset, int bits,
1391 insn * ins, const struct itemplate *temp,
1392 int64_t insn_end)
1393 {
1394 uint8_t c;
1395 uint8_t bytes[4];
1396 int64_t size;
1397 int64_t data;
1398 int op1, op2;
1399 struct operand *opx;
1400 const uint8_t *codes = temp->code;
1401 uint8_t opex = 0;
1402 enum ea_type eat = EA_SCALAR;
1403
1404 ins->rex_done = false;
1405
1406 while (*codes) {
1407 c = *codes++;
1408 op1 = (c & 3) + ((opex & 1) << 2);
1409 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1410 opx = &ins->oprs[op1];
1411 opex = 0; /* For the next iteration */
1412
1413 switch (c) {
1414 case 01:
1415 case 02:
1416 case 03:
1417 case 04:
1418 offset += emit_rex(ins, segment, offset, bits);
1419 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1420 codes += c;
1421 offset += c;
1422 break;
1423
1424 case 05:
1425 case 06:
1426 case 07:
1427 opex = c;
1428 break;
1429
1430 case4(010):
1431 offset += emit_rex(ins, segment, offset, bits);
1432 bytes[0] = *codes++ + (regval(opx) & 7);
1433 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1434 offset += 1;
1435 break;
1436
1437 case4(014):
1438 break;
1439
1440 case4(020):
1441 if (opx->offset < -256 || opx->offset > 255) {
1442 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1443 "byte value exceeds bounds");
1444 }
1445 out_imm8(offset, segment, opx, -1);
1446 offset += 1;
1447 break;
1448
1449 case4(024):
1450 if (opx->offset < 0 || opx->offset > 255)
1451 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1452 "unsigned byte value exceeds bounds");
1453 out_imm8(offset, segment, opx, 1);
1454 offset += 1;
1455 break;
1456
1457 case4(030):
1458 warn_overflow_opd(opx, 2);
1459 data = opx->offset;
1460 out(offset, segment, &data, OUT_ADDRESS, 2,
1461 opx->segment, opx->wrt);
1462 offset += 2;
1463 break;
1464
1465 case4(034):
1466 if (opx->type & (BITS16 | BITS32))
1467 size = (opx->type & BITS16) ? 2 : 4;
1468 else
1469 size = (bits == 16) ? 2 : 4;
1470 warn_overflow_opd(opx, size);
1471 data = opx->offset;
1472 out(offset, segment, &data, OUT_ADDRESS, size,
1473 opx->segment, opx->wrt);
1474 offset += size;
1475 break;
1476
1477 case4(040):
1478 warn_overflow_opd(opx, 4);
1479 data = opx->offset;
1480 out(offset, segment, &data, OUT_ADDRESS, 4,
1481 opx->segment, opx->wrt);
1482 offset += 4;
1483 break;
1484
1485 case4(044):
1486 data = opx->offset;
1487 size = ins->addr_size >> 3;
1488 warn_overflow_opd(opx, size);
1489 out(offset, segment, &data, OUT_ADDRESS, size,
1490 opx->segment, opx->wrt);
1491 offset += size;
1492 break;
1493
1494 case4(050):
1495 if (opx->segment != segment) {
1496 data = opx->offset;
1497 out(offset, segment, &data,
1498 OUT_REL1ADR, insn_end - offset,
1499 opx->segment, opx->wrt);
1500 } else {
1501 data = opx->offset - insn_end;
1502 if (data > 127 || data < -128)
1503 errfunc(ERR_NONFATAL, "short jump is out of range");
1504 out(offset, segment, &data,
1505 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1506 }
1507 offset += 1;
1508 break;
1509
1510 case4(054):
1511 data = (int64_t)opx->offset;
1512 out(offset, segment, &data, OUT_ADDRESS, 8,
1513 opx->segment, opx->wrt);
1514 offset += 8;
1515 break;
1516
1517 case4(060):
1518 if (opx->segment != segment) {
1519 data = opx->offset;
1520 out(offset, segment, &data,
1521 OUT_REL2ADR, insn_end - offset,
1522 opx->segment, opx->wrt);
1523 } else {
1524 data = opx->offset - insn_end;
1525 out(offset, segment, &data,
1526 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1527 }
1528 offset += 2;
1529 break;
1530
1531 case4(064):
1532 if (opx->type & (BITS16 | BITS32 | BITS64))
1533 size = (opx->type & BITS16) ? 2 : 4;
1534 else
1535 size = (bits == 16) ? 2 : 4;
1536 if (opx->segment != segment) {
1537 data = opx->offset;
1538 out(offset, segment, &data,
1539 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1540 insn_end - offset, opx->segment, opx->wrt);
1541 } else {
1542 data = opx->offset - insn_end;
1543 out(offset, segment, &data,
1544 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1545 }
1546 offset += size;
1547 break;
1548
1549 case4(070):
1550 if (opx->segment != segment) {
1551 data = opx->offset;
1552 out(offset, segment, &data,
1553 OUT_REL4ADR, insn_end - offset,
1554 opx->segment, opx->wrt);
1555 } else {
1556 data = opx->offset - insn_end;
1557 out(offset, segment, &data,
1558 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1559 }
1560 offset += 4;
1561 break;
1562
1563 case4(074):
1564 if (opx->segment == NO_SEG)
1565 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1566 " relocatable");
1567 data = 0;
1568 out(offset, segment, &data, OUT_ADDRESS, 2,
1569 outfmt->segbase(1 + opx->segment),
1570 opx->wrt);
1571 offset += 2;
1572 break;
1573
1574 case 0172:
1575 c = *codes++;
1576 opx = &ins->oprs[c >> 3];
1577 bytes[0] = nasm_regvals[opx->basereg] << 4;
1578 opx = &ins->oprs[c & 7];
1579 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1580 errfunc(ERR_NONFATAL,
1581 "non-absolute expression not permitted as argument %d",
1582 c & 7);
1583 } else {
1584 if (opx->offset & ~15) {
1585 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1586 "four-bit argument exceeds bounds");
1587 }
1588 bytes[0] |= opx->offset & 15;
1589 }
1590 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1591 offset++;
1592 break;
1593
1594 case 0173:
1595 c = *codes++;
1596 opx = &ins->oprs[c >> 4];
1597 bytes[0] = nasm_regvals[opx->basereg] << 4;
1598 bytes[0] |= c & 15;
1599 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1600 offset++;
1601 break;
1602
1603 case4(0174):
1604 bytes[0] = nasm_regvals[opx->basereg] << 4;
1605 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1606 offset++;
1607 break;
1608
1609 case4(0254):
1610 data = opx->offset;
1611 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1612 (int32_t)data != (int64_t)data) {
1613 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1614 "signed dword immediate exceeds bounds");
1615 }
1616 out(offset, segment, &data, OUT_ADDRESS, -4,
1617 opx->segment, opx->wrt);
1618 offset += 4;
1619 break;
1620
1621 case4(0240):
1622 case 0250:
1623 codes += 3;
1624 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1625 EVEX_P2Z | EVEX_P2AAA, 2);
1626 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1627 bytes[0] = 0x62;
1628 /* EVEX.X can be set by either REX or EVEX for different reasons */
1629 bytes[1] = ((((ins->rex & 7) << 5) |
1630 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1631 (ins->vex_cm & 3);
1632 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1633 ((~ins->vexreg & 15) << 3) |
1634 (1 << 2) | (ins->vex_wlp & 3);
1635 bytes[3] = ins->evex_p[2];
1636 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1637 offset += 4;
1638 break;
1639
1640 case4(0260):
1641 case 0270:
1642 codes += 2;
1643 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1644 ins->prefixes[PPS_VEX] == P_VEX3) {
1645 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1646 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1647 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1648 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1649 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1650 offset += 3;
1651 } else {
1652 bytes[0] = 0xc5;
1653 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1654 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1655 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1656 offset += 2;
1657 }
1658 break;
1659
1660 case 0271:
1661 case 0272:
1662 case 0273:
1663 break;
1664
1665 case4(0274):
1666 {
1667 uint64_t uv, um;
1668 int s;
1669
1670 if (ins->rex & REX_W)
1671 s = 64;
1672 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1673 s = 16;
1674 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1675 s = 32;
1676 else
1677 s = bits;
1678
1679 um = (uint64_t)2 << (s-1);
1680 uv = opx->offset;
1681
1682 if (uv > 127 && uv < (uint64_t)-128 &&
1683 (uv < um-128 || uv > um-1)) {
1684 /* If this wasn't explicitly byte-sized, warn as though we
1685 * had fallen through to the imm16/32/64 case.
1686 */
1687 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1688 "%s value exceeds bounds",
1689 (opx->type & BITS8) ? "signed byte" :
1690 s == 16 ? "word" :
1691 s == 32 ? "dword" :
1692 "signed dword");
1693 }
1694 if (opx->segment != NO_SEG) {
1695 data = uv;
1696 out(offset, segment, &data, OUT_ADDRESS, 1,
1697 opx->segment, opx->wrt);
1698 } else {
1699 bytes[0] = uv;
1700 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1701 NO_SEG);
1702 }
1703 offset += 1;
1704 break;
1705 }
1706
1707 case4(0300):
1708 break;
1709
1710 case 0310:
1711 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1712 *bytes = 0x67;
1713 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1714 offset += 1;
1715 } else
1716 offset += 0;
1717 break;
1718
1719 case 0311:
1720 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1721 *bytes = 0x67;
1722 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1723 offset += 1;
1724 } else
1725 offset += 0;
1726 break;
1727
1728 case 0312:
1729 break;
1730
1731 case 0313:
1732 ins->rex = 0;
1733 break;
1734
1735 case4(0314):
1736 break;
1737
1738 case 0320:
1739 case 0321:
1740 break;
1741
1742 case 0322:
1743 case 0323:
1744 break;
1745
1746 case 0324:
1747 ins->rex |= REX_W;
1748 break;
1749
1750 case 0325:
1751 break;
1752
1753 case 0326:
1754 break;
1755
1756 case 0330:
1757 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1758 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1759 offset += 1;
1760 break;
1761
1762 case 0331:
1763 break;
1764
1765 case 0332:
1766 case 0333:
1767 *bytes = c - 0332 + 0xF2;
1768 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1769 offset += 1;
1770 break;
1771
1772 case 0334:
1773 if (ins->rex & REX_R) {
1774 *bytes = 0xF0;
1775 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1776 offset += 1;
1777 }
1778 ins->rex &= ~(REX_L|REX_R);
1779 break;
1780
1781 case 0335:
1782 break;
1783
1784 case 0336:
1785 case 0337:
1786 break;
1787
1788 case 0340:
1789 if (ins->oprs[0].segment != NO_SEG)
1790 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1791 else {
1792 int64_t size = ins->oprs[0].offset;
1793 if (size > 0)
1794 out(offset, segment, NULL,
1795 OUT_RESERVE, size, NO_SEG, NO_SEG);
1796 offset += size;
1797 }
1798 break;
1799
1800 case 0341:
1801 break;
1802
1803 case 0360:
1804 break;
1805
1806 case 0361:
1807 bytes[0] = 0x66;
1808 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1809 offset += 1;
1810 break;
1811
1812 case 0364:
1813 case 0365:
1814 break;
1815
1816 case 0366:
1817 case 0367:
1818 *bytes = c - 0366 + 0x66;
1819 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1820 offset += 1;
1821 break;
1822
1823 case3(0370):
1824 break;
1825
1826 case 0373:
1827 *bytes = bits == 16 ? 3 : 5;
1828 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1829 offset += 1;
1830 break;
1831
1832 case 0374:
1833 eat = EA_XMMVSIB;
1834 break;
1835
1836 case 0375:
1837 eat = EA_YMMVSIB;
1838 break;
1839
1840 case 0376:
1841 eat = EA_ZMMVSIB;
1842 break;
1843
1844 case4(0100):
1845 case4(0110):
1846 case4(0120):
1847 case4(0130):
1848 case4(0200):
1849 case4(0204):
1850 case4(0210):
1851 case4(0214):
1852 case4(0220):
1853 case4(0224):
1854 case4(0230):
1855 case4(0234):
1856 {
1857 ea ea_data;
1858 int rfield;
1859 opflags_t rflags;
1860 uint8_t *p;
1861 int32_t s;
1862 struct operand *opy = &ins->oprs[op2];
1863
1864 if (c <= 0177) {
1865 /* pick rfield from operand b (opx) */
1866 rflags = regflag(opx);
1867 rfield = nasm_regvals[opx->basereg];
1868 } else {
1869 /* rfield is constant */
1870 rflags = 0;
1871 rfield = c & 7;
1872 }
1873
1874 if (process_ea(opy, &ea_data, bits,
1875 rfield, rflags, ins) != eat)
1876 errfunc(ERR_NONFATAL, "invalid effective address");
1877
1878 p = bytes;
1879 *p++ = ea_data.modrm;
1880 if (ea_data.sib_present)
1881 *p++ = ea_data.sib;
1882
1883 s = p - bytes;
1884 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1885
1886 /*
1887 * Make sure the address gets the right offset in case
1888 * the line breaks in the .lst file (BR 1197827)
1889 */
1890 offset += s;
1891 s = 0;
1892
1893 if (ea_data.bytes) {
1894 /* use compressed displacement, if available */
1895 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1896 s += ea_data.bytes;
1897 if (ea_data.rip) {
1898 if (opy->segment == segment) {
1899 data -= insn_end;
1900 if (overflow_signed(data, ea_data.bytes))
1901 warn_overflow(ERR_PASS2, ea_data.bytes);
1902 out(offset, segment, &data, OUT_ADDRESS,
1903 ea_data.bytes, NO_SEG, NO_SEG);
1904 } else {
1905 /* overflow check in output/linker? */
1906 out(offset, segment, &data, OUT_REL4ADR,
1907 insn_end - offset, opy->segment, opy->wrt);
1908 }
1909 } else {
1910 int asize = ins->addr_size >> 3;
1911 int atype = ea_data.bytes;
1912
1913 if (overflow_general(data, asize) ||
1914 signed_bits(data, ins->addr_size) !=
1915 signed_bits(data, ea_data.bytes << 3))
1916 warn_overflow(ERR_PASS2, ea_data.bytes);
1917
1918 if (asize > ea_data.bytes) {
1919 /*
1920 * If the address isn't the full width of
1921 * the address size, treat is as signed...
1922 */
1923 atype = -atype;
1924 }
1925
1926 out(offset, segment, &data, OUT_ADDRESS,
1927 atype, opy->segment, opy->wrt);
1928 }
1929 }
1930 offset += s;
1931 }
1932 break;
1933
1934 default:
1935 errfunc(ERR_PANIC, "internal instruction table corrupt"
1936 ": instruction code \\%o (0x%02X) given", c, c);
1937 break;
1938 }
1939 }
1940 }
1941
1942 static opflags_t regflag(const operand * o)
1943 {
1944 if (!is_register(o->basereg))
1945 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1946 return nasm_reg_flags[o->basereg];
1947 }
1948
1949 static int32_t regval(const operand * o)
1950 {
1951 if (!is_register(o->basereg))
1952 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1953 return nasm_regvals[o->basereg];
1954 }
1955
1956 static int op_rexflags(const operand * o, int mask)
1957 {
1958 opflags_t flags;
1959 int val;
1960
1961 if (!is_register(o->basereg))
1962 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1963
1964 flags = nasm_reg_flags[o->basereg];
1965 val = nasm_regvals[o->basereg];
1966
1967 return rexflags(val, flags, mask);
1968 }
1969
1970 static int rexflags(int val, opflags_t flags, int mask)
1971 {
1972 int rex = 0;
1973
1974 if (val >= 0 && (val & 8))
1975 rex |= REX_B|REX_X|REX_R;
1976 if (flags & BITS64)
1977 rex |= REX_W;
1978 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1979 rex |= REX_H;
1980 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1981 rex |= REX_P;
1982
1983 return rex & mask;
1984 }
1985
1986 static int evexflags(int val, decoflags_t deco,
1987 int mask, uint8_t byte)
1988 {
1989 int evex = 0;
1990
1991 switch (byte) {
1992 case 0:
1993 if (val >= 0 && (val & 16))
1994 evex |= (EVEX_P0RP | EVEX_P0X);
1995 break;
1996 case 2:
1997 if (val >= 0 && (val & 16))
1998 evex |= EVEX_P2VP;
1999 if (deco & Z)
2000 evex |= EVEX_P2Z;
2001 if (deco & OPMASK_MASK)
2002 evex |= deco & EVEX_P2AAA;
2003 break;
2004 }
2005 return evex & mask;
2006 }
2007
2008 static int op_evexflags(const operand * o, int mask, uint8_t byte)
2009 {
2010 int val;
2011
2012 val = nasm_regvals[o->basereg];
2013
2014 return evexflags(val, o->decoflags, mask, byte);
2015 }
2016
2017 static enum match_result find_match(const struct itemplate **tempp,
2018 insn *instruction,
2019 int32_t segment, int64_t offset, int bits)
2020 {
2021 const struct itemplate *temp;
2022 enum match_result m, merr;
2023 opflags_t xsizeflags[MAX_OPERANDS];
2024 bool opsizemissing = false;
2025 int8_t broadcast = instruction->evex_brerop;
2026 int i;
2027
2028 /* broadcasting uses a different data element size */
2029 for (i = 0; i < instruction->operands; i++)
2030 if (i == broadcast)
2031 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2032 else
2033 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2034
2035 merr = MERR_INVALOP;
2036
2037 for (temp = nasm_instructions[instruction->opcode];
2038 temp->opcode != I_none; temp++) {
2039 m = matches(temp, instruction, bits);
2040 if (m == MOK_JUMP) {
2041 if (jmp_match(segment, offset, bits, instruction, temp))
2042 m = MOK_GOOD;
2043 else
2044 m = MERR_INVALOP;
2045 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2046 /*
2047 * Missing operand size and a candidate for fuzzy matching...
2048 */
2049 for (i = 0; i < temp->operands; i++)
2050 if (i == broadcast)
2051 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2052 else
2053 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2054 opsizemissing = true;
2055 }
2056 if (m > merr)
2057 merr = m;
2058 if (merr == MOK_GOOD)
2059 goto done;
2060 }
2061
2062 /* No match, but see if we can get a fuzzy operand size match... */
2063 if (!opsizemissing)
2064 goto done;
2065
2066 for (i = 0; i < instruction->operands; i++) {
2067 /*
2068 * We ignore extrinsic operand sizes on registers, so we should
2069 * never try to fuzzy-match on them. This also resolves the case
2070 * when we have e.g. "xmmrm128" in two different positions.
2071 */
2072 if (is_class(REGISTER, instruction->oprs[i].type))
2073 continue;
2074
2075 /* This tests if xsizeflags[i] has more than one bit set */
2076 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2077 goto done; /* No luck */
2078
2079 if (i == broadcast) {
2080 instruction->oprs[i].decoflags |= xsizeflags[i];
2081 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2082 BITS32 : BITS64);
2083 } else {
2084 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2085 }
2086 }
2087
2088 /* Try matching again... */
2089 for (temp = nasm_instructions[instruction->opcode];
2090 temp->opcode != I_none; temp++) {
2091 m = matches(temp, instruction, bits);
2092 if (m == MOK_JUMP) {
2093 if (jmp_match(segment, offset, bits, instruction, temp))
2094 m = MOK_GOOD;
2095 else
2096 m = MERR_INVALOP;
2097 }
2098 if (m > merr)
2099 merr = m;
2100 if (merr == MOK_GOOD)
2101 goto done;
2102 }
2103
2104 done:
2105 *tempp = temp;
2106 return merr;
2107 }
2108
2109 static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
2110 {
2111 opflags_t opsize = opflags & SIZE_MASK;
2112 uint8_t brcast_num;
2113
2114 /*
2115 * Due to discontinuity between BITS64 and BITS128 (BITS80),
2116 * this cannot be a simple arithmetic calculation.
2117 */
2118 if (brsize > BITS64)
2119 errfunc(ERR_FATAL,
2120 "size of broadcasting element is greater than 64 bits");
2121
2122 switch (opsize) {
2123 case BITS64:
2124 brcast_num = BITS64 / brsize;
2125 break;
2126 default:
2127 brcast_num = (opsize / BITS128) * (BITS64 / brsize) * 2;
2128 break;
2129 }
2130
2131 return brcast_num;
2132 }
2133
2134 static enum match_result matches(const struct itemplate *itemp,
2135 insn *instruction, int bits)
2136 {
2137 opflags_t size[MAX_OPERANDS], asize;
2138 bool opsizemissing = false;
2139 int i, oprs;
2140
2141 /*
2142 * Check the opcode
2143 */
2144 if (itemp->opcode != instruction->opcode)
2145 return MERR_INVALOP;
2146
2147 /*
2148 * Count the operands
2149 */
2150 if (itemp->operands != instruction->operands)
2151 return MERR_INVALOP;
2152
2153 /*
2154 * Is it legal?
2155 */
2156 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2157 return MERR_INVALOP;
2158
2159 /*
2160 * {evex} available?
2161 */
2162 switch (instruction->prefixes[PPS_VEX]) {
2163 case P_EVEX:
2164 if (!itemp_has(itemp, IF_EVEX))
2165 return MERR_ENCMISMATCH;
2166 break;
2167 case P_VEX3:
2168 case P_VEX2:
2169 if (!itemp_has(itemp, IF_VEX))
2170 return MERR_ENCMISMATCH;
2171 break;
2172 default:
2173 break;
2174 }
2175
2176 /*
2177 * Check that no spurious colons or TOs are present
2178 */
2179 for (i = 0; i < itemp->operands; i++)
2180 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2181 return MERR_INVALOP;
2182
2183 /*
2184 * Process size flags
2185 */
2186 switch (itemp_smask(itemp)) {
2187 case IF_GENBIT(IF_SB):
2188 asize = BITS8;
2189 break;
2190 case IF_GENBIT(IF_SW):
2191 asize = BITS16;
2192 break;
2193 case IF_GENBIT(IF_SD):
2194 asize = BITS32;
2195 break;
2196 case IF_GENBIT(IF_SQ):
2197 asize = BITS64;
2198 break;
2199 case IF_GENBIT(IF_SO):
2200 asize = BITS128;
2201 break;
2202 case IF_GENBIT(IF_SY):
2203 asize = BITS256;
2204 break;
2205 case IF_GENBIT(IF_SZ):
2206 asize = BITS512;
2207 break;
2208 case IF_GENBIT(IF_SIZE):
2209 switch (bits) {
2210 case 16:
2211 asize = BITS16;
2212 break;
2213 case 32:
2214 asize = BITS32;
2215 break;
2216 case 64:
2217 asize = BITS64;
2218 break;
2219 default:
2220 asize = 0;
2221 break;
2222 }
2223 break;
2224 default:
2225 asize = 0;
2226 break;
2227 }
2228
2229 if (itemp_armask(itemp)) {
2230 /* S- flags only apply to a specific operand */
2231 i = itemp_arg(itemp);
2232 memset(size, 0, sizeof size);
2233 size[i] = asize;
2234 } else {
2235 /* S- flags apply to all operands */
2236 for (i = 0; i < MAX_OPERANDS; i++)
2237 size[i] = asize;
2238 }
2239
2240 /*
2241 * Check that the operand flags all match up,
2242 * it's a bit tricky so lets be verbose:
2243 *
2244 * 1) Find out the size of operand. If instruction
2245 * doesn't have one specified -- we're trying to
2246 * guess it either from template (IF_S* flag) or
2247 * from code bits.
2248 *
2249 * 2) If template operand do not match the instruction OR
2250 * template has an operand size specified AND this size differ
2251 * from which instruction has (perhaps we got it from code bits)
2252 * we are:
2253 * a) Check that only size of instruction and operand is differ
2254 * other characteristics do match
2255 * b) Perhaps it's a register specified in instruction so
2256 * for such a case we just mark that operand as "size
2257 * missing" and this will turn on fuzzy operand size
2258 * logic facility (handled by a caller)
2259 */
2260 for (i = 0; i < itemp->operands; i++) {
2261 opflags_t type = instruction->oprs[i].type;
2262 decoflags_t deco = instruction->oprs[i].decoflags;
2263 bool is_broadcast = deco & BRDCAST_MASK;
2264 uint8_t brcast_num = 0;
2265 opflags_t template_opsize, insn_opsize;
2266
2267 if (!(type & SIZE_MASK))
2268 type |= size[i];
2269
2270 insn_opsize = type & SIZE_MASK;
2271 if (!is_broadcast) {
2272 template_opsize = itemp->opd[i] & SIZE_MASK;
2273 } else {
2274 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2275 /*
2276 * when broadcasting, the element size depends on
2277 * the instruction type. decorator flag should match.
2278 */
2279
2280 if (deco_brsize) {
2281 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2282 /* calculate the proper number : {1to<brcast_num>} */
2283 brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
2284 } else {
2285 template_opsize = 0;
2286 }
2287 }
2288
2289 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2290 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2291 return MERR_INVALOP;
2292 } else if (template_opsize) {
2293 if (template_opsize != insn_opsize) {
2294 if (insn_opsize) {
2295 return MERR_INVALOP;
2296 } else if (!is_class(REGISTER, type)) {
2297 /*
2298 * Note: we don't honor extrinsic operand sizes for registers,
2299 * so "missing operand size" for a register should be
2300 * considered a wildcard match rather than an error.
2301 */
2302 opsizemissing = true;
2303 }
2304 } else if (is_broadcast &&
2305 (brcast_num !=
2306 (2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2307 /*
2308 * broadcasting opsize matches but the number of repeated memory
2309 * element does not match.
2310 * if 64b double precision float is broadcasted to ymm (256b),
2311 * broadcasting decorator must be {1to4}.
2312 */
2313 return MERR_BRNUMMISMATCH;
2314 }
2315 }
2316 }
2317
2318 if (opsizemissing)
2319 return MERR_OPSIZEMISSING;
2320
2321 /*
2322 * Check operand sizes
2323 */
2324 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2325 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2326 for (i = 0; i < oprs; i++) {
2327 asize = itemp->opd[i] & SIZE_MASK;
2328 if (asize) {
2329 for (i = 0; i < oprs; i++)
2330 size[i] = asize;
2331 break;
2332 }
2333 }
2334 } else {
2335 oprs = itemp->operands;
2336 }
2337
2338 for (i = 0; i < itemp->operands; i++) {
2339 if (!(itemp->opd[i] & SIZE_MASK) &&
2340 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2341 return MERR_OPSIZEMISMATCH;
2342 }
2343
2344 /*
2345 * Check template is okay at the set cpu level
2346 */
2347 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2348 return MERR_BADCPU;
2349
2350 /*
2351 * Verify the appropriate long mode flag.
2352 */
2353 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2354 return MERR_BADMODE;
2355
2356 /*
2357 * If we have a HLE prefix, look for the NOHLE flag
2358 */
2359 if (itemp_has(itemp, IF_NOHLE) &&
2360 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2361 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2362 return MERR_BADHLE;
2363
2364 /*
2365 * Check if special handling needed for Jumps
2366 */
2367 if ((itemp->code[0] & ~1) == 0370)
2368 return MOK_JUMP;
2369
2370 /*
2371 * Check if BND prefix is allowed.
2372 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2373 */
2374 if (!itemp_has(itemp, IF_BND) &&
2375 (has_prefix(instruction, PPS_REP, P_BND) ||
2376 has_prefix(instruction, PPS_REP, P_NOBND)))
2377 return MERR_BADBND;
2378 else if (itemp_has(itemp, IF_BND) &&
2379 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2380 has_prefix(instruction, PPS_REP, P_REPNZ)))
2381 return MERR_BADREPNE;
2382
2383 return MOK_GOOD;
2384 }
2385
2386 /*
2387 * Check if ModR/M.mod should/can be 01.
2388 * - EAF_BYTEOFFS is set
2389 * - offset can fit in a byte when EVEX is not used
2390 * - offset can be compressed when EVEX is used
2391 */
2392 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2393 (o >= -128 && o <= 127 && \
2394 seg == NO_SEG && !forw_ref && \
2395 !(input->eaflags & EAF_WORDOFFS) && \
2396 !(ins->rex & REX_EV)) || \
2397 (ins->rex & REX_EV && \
2398 is_disp8n(input, ins, &output->disp8)))
2399
2400 static enum ea_type process_ea(operand *input, ea *output, int bits,
2401 int rfield, opflags_t rflags, insn *ins)
2402 {
2403 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2404 int addrbits = ins->addr_size;
2405 int eaflags = input->eaflags;
2406
2407 output->type = EA_SCALAR;
2408 output->rip = false;
2409 output->disp8 = 0;
2410
2411 /* REX flags for the rfield operand */
2412 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2413 /* EVEX.R' flag for the REG operand */
2414 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2415
2416 if (is_class(REGISTER, input->type)) {
2417 /*
2418 * It's a direct register.
2419 */
2420 if (!is_register(input->basereg))
2421 goto err;
2422
2423 if (!is_reg_class(REG_EA, input->basereg))
2424 goto err;
2425
2426 /* broadcasting is not available with a direct register operand. */
2427 if (input->decoflags & BRDCAST_MASK) {
2428 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2429 goto err;
2430 }
2431
2432 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2433 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2434 output->sib_present = false; /* no SIB necessary */
2435 output->bytes = 0; /* no offset necessary either */
2436 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2437 } else {
2438 /*
2439 * It's a memory reference.
2440 */
2441
2442 /* Embedded rounding or SAE is not available with a mem ref operand. */
2443 if (input->decoflags & (ER | SAE)) {
2444 nasm_error(ERR_NONFATAL,
2445 "Embedded rounding is available only with reg-reg op.");
2446 return -1;
2447 }
2448
2449 if (input->basereg == -1 &&
2450 (input->indexreg == -1 || input->scale == 0)) {
2451 /*
2452 * It's a pure offset.
2453 */
2454 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2455 input->segment == NO_SEG) {
2456 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2457 input->type &= ~IP_REL;
2458 input->type |= MEMORY;
2459 }
2460
2461 if (bits == 64 &&
2462 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2463 nasm_error(ERR_NONFATAL, "RIP-relative addressing is prohibited for mib.");
2464 return -1;
2465 }
2466
2467 if (eaflags & EAF_BYTEOFFS ||
2468 (eaflags & EAF_WORDOFFS &&
2469 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2470 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2471 }
2472
2473 if (bits == 64 && (~input->type & IP_REL)) {
2474 output->sib_present = true;
2475 output->sib = GEN_SIB(0, 4, 5);
2476 output->bytes = 4;
2477 output->modrm = GEN_MODRM(0, rfield, 4);
2478 output->rip = false;
2479 } else {
2480 output->sib_present = false;
2481 output->bytes = (addrbits != 16 ? 4 : 2);
2482 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2483 output->rip = bits == 64;
2484 }
2485 } else {
2486 /*
2487 * It's an indirection.
2488 */
2489 int i = input->indexreg, b = input->basereg, s = input->scale;
2490 int32_t seg = input->segment;
2491 int hb = input->hintbase, ht = input->hinttype;
2492 int t, it, bt; /* register numbers */
2493 opflags_t x, ix, bx; /* register flags */
2494
2495 if (s == 0)
2496 i = -1; /* make this easy, at least */
2497
2498 if (is_register(i)) {
2499 it = nasm_regvals[i];
2500 ix = nasm_reg_flags[i];
2501 } else {
2502 it = -1;
2503 ix = 0;
2504 }
2505
2506 if (is_register(b)) {
2507 bt = nasm_regvals[b];
2508 bx = nasm_reg_flags[b];
2509 } else {
2510 bt = -1;
2511 bx = 0;
2512 }
2513
2514 /* if either one are a vector register... */
2515 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2516 opflags_t sok = BITS32 | BITS64;
2517 int32_t o = input->offset;
2518 int mod, scale, index, base;
2519
2520 /*
2521 * For a vector SIB, one has to be a vector and the other,
2522 * if present, a GPR. The vector must be the index operand.
2523 */
2524 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2525 if (s == 0)
2526 s = 1;
2527 else if (s != 1)
2528 goto err;
2529
2530 t = bt, bt = it, it = t;
2531 x = bx, bx = ix, ix = x;
2532 }
2533
2534 if (bt != -1) {
2535 if (REG_GPR & ~bx)
2536 goto err;
2537 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2538 sok &= bx;
2539 else
2540 goto err;
2541 }
2542
2543 /*
2544 * While we're here, ensure the user didn't specify
2545 * WORD or QWORD
2546 */
2547 if (input->disp_size == 16 || input->disp_size == 64)
2548 goto err;
2549
2550 if (addrbits == 16 ||
2551 (addrbits == 32 && !(sok & BITS32)) ||
2552 (addrbits == 64 && !(sok & BITS64)))
2553 goto err;
2554
2555 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2556 : ((ix & YMMREG & ~REG_EA)
2557 ? EA_YMMVSIB : EA_XMMVSIB));
2558
2559 output->rex |= rexflags(it, ix, REX_X);
2560 output->rex |= rexflags(bt, bx, REX_B);
2561 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2562
2563 index = it & 7; /* it is known to be != -1 */
2564
2565 switch (s) {
2566 case 1:
2567 scale = 0;
2568 break;
2569 case 2:
2570 scale = 1;
2571 break;
2572 case 4:
2573 scale = 2;
2574 break;
2575 case 8:
2576 scale = 3;
2577 break;
2578 default: /* then what the smeg is it? */
2579 goto err; /* panic */
2580 }
2581
2582 if (bt == -1) {
2583 base = 5;
2584 mod = 0;
2585 } else {
2586 base = (bt & 7);
2587 if (base != REG_NUM_EBP && o == 0 &&
2588 seg == NO_SEG && !forw_ref &&
2589 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2590 mod = 0;
2591 else if (IS_MOD_01())
2592 mod = 1;
2593 else
2594 mod = 2;
2595 }
2596
2597 output->sib_present = true;
2598 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2599 output->modrm = GEN_MODRM(mod, rfield, 4);
2600 output->sib = GEN_SIB(scale, index, base);
2601 } else if ((ix|bx) & (BITS32|BITS64)) {
2602 /*
2603 * it must be a 32/64-bit memory reference. Firstly we have
2604 * to check that all registers involved are type E/Rxx.
2605 */
2606 opflags_t sok = BITS32 | BITS64;
2607 int32_t o = input->offset;
2608
2609 if (it != -1) {
2610 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2611 sok &= ix;
2612 else
2613 goto err;
2614 }
2615
2616 if (bt != -1) {
2617 if (REG_GPR & ~bx)
2618 goto err; /* Invalid register */
2619 if (~sok & bx & SIZE_MASK)
2620 goto err; /* Invalid size */
2621 sok &= bx;
2622 }
2623
2624 /*
2625 * While we're here, ensure the user didn't specify
2626 * WORD or QWORD
2627 */
2628 if (input->disp_size == 16 || input->disp_size == 64)
2629 goto err;
2630
2631 if (addrbits == 16 ||
2632 (addrbits == 32 && !(sok & BITS32)) ||
2633 (addrbits == 64 && !(sok & BITS64)))
2634 goto err;
2635
2636 /* now reorganize base/index */
2637 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2638 ((hb == b && ht == EAH_NOTBASE) ||
2639 (hb == i && ht == EAH_MAKEBASE))) {
2640 /* swap if hints say so */
2641 t = bt, bt = it, it = t;
2642 x = bx, bx = ix, ix = x;
2643 }
2644
2645 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2646 /* make single reg base, unless hint */
2647 bt = it, bx = ix, it = -1, ix = 0;
2648 }
2649 if (eaflags & EAF_MIB) {
2650 /* only for mib operands */
2651 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2652 /*
2653 * make a single reg index [reg*1].
2654 * gas uses this form for an explicit index register.
2655 */
2656 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2657 }
2658 if ((ht == EAH_SUMMED) && bt == -1) {
2659 /* separate once summed index into [base, index] */
2660 bt = it, bx = ix, s--;
2661 }
2662 } else {
2663 if (((s == 2 && it != REG_NUM_ESP &&
2664 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2665 s == 3 || s == 5 || s == 9) && bt == -1) {
2666 /* convert 3*EAX to EAX+2*EAX */
2667 bt = it, bx = ix, s--;
2668 }
2669 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2670 (eaflags & EAF_TIMESTWO) &&
2671 (hb == b && ht == EAH_NOTBASE)) {
2672 /*
2673 * convert [NOSPLIT EAX*1]
2674 * to sib format with 0x0 displacement - [EAX*1+0].
2675 */
2676 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2677 }
2678 }
2679 if (s == 1 && it == REG_NUM_ESP) {
2680 /* swap ESP into base if scale is 1 */
2681 t = it, it = bt, bt = t;
2682 x = ix, ix = bx, bx = x;
2683 }
2684 if (it == REG_NUM_ESP ||
2685 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2686 goto err; /* wrong, for various reasons */
2687
2688 output->rex |= rexflags(it, ix, REX_X);
2689 output->rex |= rexflags(bt, bx, REX_B);
2690
2691 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2692 /* no SIB needed */
2693 int mod, rm;
2694
2695 if (bt == -1) {
2696 rm = 5;
2697 mod = 0;
2698 } else {
2699 rm = (bt & 7);
2700 if (rm != REG_NUM_EBP && o == 0 &&
2701 seg == NO_SEG && !forw_ref &&
2702 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2703 mod = 0;
2704 else if (IS_MOD_01())
2705 mod = 1;
2706 else
2707 mod = 2;
2708 }
2709
2710 output->sib_present = false;
2711 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2712 output->modrm = GEN_MODRM(mod, rfield, rm);
2713 } else {
2714 /* we need a SIB */
2715 int mod, scale, index, base;
2716
2717 if (it == -1)
2718 index = 4, s = 1;
2719 else
2720 index = (it & 7);
2721
2722 switch (s) {
2723 case 1:
2724 scale = 0;
2725 break;
2726 case 2:
2727 scale = 1;
2728 break;
2729 case 4:
2730 scale = 2;
2731 break;
2732 case 8:
2733 scale = 3;
2734 break;
2735 default: /* then what the smeg is it? */
2736 goto err; /* panic */
2737 }
2738
2739 if (bt == -1) {
2740 base = 5;
2741 mod = 0;
2742 } else {
2743 base = (bt & 7);
2744 if (base != REG_NUM_EBP && o == 0 &&
2745 seg == NO_SEG && !forw_ref &&
2746 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2747 mod = 0;
2748 else if (IS_MOD_01())
2749 mod = 1;
2750 else
2751 mod = 2;
2752 }
2753
2754 output->sib_present = true;
2755 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2756 output->modrm = GEN_MODRM(mod, rfield, 4);
2757 output->sib = GEN_SIB(scale, index, base);
2758 }
2759 } else { /* it's 16-bit */
2760 int mod, rm;
2761 int16_t o = input->offset;
2762
2763 /* check for 64-bit long mode */
2764 if (addrbits == 64)
2765 goto err;
2766
2767 /* check all registers are BX, BP, SI or DI */
2768 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2769 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2770 goto err;
2771
2772 /* ensure the user didn't specify DWORD/QWORD */
2773 if (input->disp_size == 32 || input->disp_size == 64)
2774 goto err;
2775
2776 if (s != 1 && i != -1)
2777 goto err; /* no can do, in 16-bit EA */
2778 if (b == -1 && i != -1) {
2779 int tmp = b;
2780 b = i;
2781 i = tmp;
2782 } /* swap */
2783 if ((b == R_SI || b == R_DI) && i != -1) {
2784 int tmp = b;
2785 b = i;
2786 i = tmp;
2787 }
2788 /* have BX/BP as base, SI/DI index */
2789 if (b == i)
2790 goto err; /* shouldn't ever happen, in theory */
2791 if (i != -1 && b != -1 &&
2792 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2793 goto err; /* invalid combinations */
2794 if (b == -1) /* pure offset: handled above */
2795 goto err; /* so if it gets to here, panic! */
2796
2797 rm = -1;
2798 if (i != -1)
2799 switch (i * 256 + b) {
2800 case R_SI * 256 + R_BX:
2801 rm = 0;
2802 break;
2803 case R_DI * 256 + R_BX:
2804 rm = 1;
2805 break;
2806 case R_SI * 256 + R_BP:
2807 rm = 2;
2808 break;
2809 case R_DI * 256 + R_BP:
2810 rm = 3;
2811 break;
2812 } else
2813 switch (b) {
2814 case R_SI:
2815 rm = 4;
2816 break;
2817 case R_DI:
2818 rm = 5;
2819 break;
2820 case R_BP:
2821 rm = 6;
2822 break;
2823 case R_BX:
2824 rm = 7;
2825 break;
2826 }
2827 if (rm == -1) /* can't happen, in theory */
2828 goto err; /* so panic if it does */
2829
2830 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2831 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2832 mod = 0;
2833 else if (IS_MOD_01())
2834 mod = 1;
2835 else
2836 mod = 2;
2837
2838 output->sib_present = false; /* no SIB - it's 16-bit */
2839 output->bytes = mod; /* bytes of offset needed */
2840 output->modrm = GEN_MODRM(mod, rfield, rm);
2841 }
2842 }
2843 }
2844
2845 output->size = 1 + output->sib_present + output->bytes;
2846 return output->type;
2847
2848 err:
2849 return output->type = EA_INVALID;
2850 }
2851
2852 static void add_asp(insn *ins, int addrbits)
2853 {
2854 int j, valid;
2855 int defdisp;
2856
2857 valid = (addrbits == 64) ? 64|32 : 32|16;
2858
2859 switch (ins->prefixes[PPS_ASIZE]) {
2860 case P_A16:
2861 valid &= 16;
2862 break;
2863 case P_A32:
2864 valid &= 32;
2865 break;
2866 case P_A64:
2867 valid &= 64;
2868 break;
2869 case P_ASP:
2870 valid &= (addrbits == 32) ? 16 : 32;
2871 break;
2872 default:
2873 break;
2874 }
2875
2876 for (j = 0; j < ins->operands; j++) {
2877 if (is_class(MEMORY, ins->oprs[j].type)) {
2878 opflags_t i, b;
2879
2880 /* Verify as Register */
2881 if (!is_register(ins->oprs[j].indexreg))
2882 i = 0;
2883 else
2884 i = nasm_reg_flags[ins->oprs[j].indexreg];
2885
2886 /* Verify as Register */
2887 if (!is_register(ins->oprs[j].basereg))
2888 b = 0;
2889 else
2890 b = nasm_reg_flags[ins->oprs[j].basereg];
2891
2892 if (ins->oprs[j].scale == 0)
2893 i = 0;
2894
2895 if (!i && !b) {
2896 int ds = ins->oprs[j].disp_size;
2897 if ((addrbits != 64 && ds > 8) ||
2898 (addrbits == 64 && ds == 16))
2899 valid &= ds;
2900 } else {
2901 if (!(REG16 & ~b))
2902 valid &= 16;
2903 if (!(REG32 & ~b))
2904 valid &= 32;
2905 if (!(REG64 & ~b))
2906 valid &= 64;
2907
2908 if (!(REG16 & ~i))
2909 valid &= 16;
2910 if (!(REG32 & ~i))
2911 valid &= 32;
2912 if (!(REG64 & ~i))
2913 valid &= 64;
2914 }
2915 }
2916 }
2917
2918 if (valid & addrbits) {
2919 ins->addr_size = addrbits;
2920 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2921 /* Add an address size prefix */
2922 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2923 ins->addr_size = (addrbits == 32) ? 16 : 32;
2924 } else {
2925 /* Impossible... */
2926 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2927 ins->addr_size = addrbits; /* Error recovery */
2928 }
2929
2930 defdisp = ins->addr_size == 16 ? 16 : 32;
2931
2932 for (j = 0; j < ins->operands; j++) {
2933 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2934 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2935 /*
2936 * mem_offs sizes must match the address size; if not,
2937 * strip the MEM_OFFS bit and match only EA instructions
2938 */
2939 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2940 }
2941 }
2942 }
The Netwide Assembler