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Accept implicit memory size for VMREAD/VMWRITE
[nasm.git] / disasm.c
blobf3d4d2a354fe5d8a5e3940107ba4c720e34aeba1
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22 #include "tables.h"
23 #include "regdis.h"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
52 uint8_t vex_v;
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
55 };
56
57 #define getu8(x) (*(uint8_t *)(x))
58 #if X86_MEMORY
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
63 #else
64 static uint16_t getu16(uint8_t *data)
65 {
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
67 }
68 static uint32_t getu32(uint8_t *data)
69 {
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
71 }
72 static uint64_t getu64(uint8_t *data)
73 {
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
75 }
76 #endif
77
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
82
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
85 {
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
88
89 regflags |= REGISTER;
90
91 if (!(REG_AL & ~regflags))
92 return R_AL;
93 if (!(REG_AX & ~regflags))
94 return R_AX;
95 if (!(REG_EAX & ~regflags))
96 return R_EAX;
97 if (!(REG_RAX & ~regflags))
98 return R_RAX;
99 if (!(REG_DL & ~regflags))
100 return R_DL;
101 if (!(REG_DX & ~regflags))
102 return R_DX;
103 if (!(REG_EDX & ~regflags))
104 return R_EDX;
105 if (!(REG_RDX & ~regflags))
106 return R_RDX;
107 if (!(REG_CL & ~regflags))
108 return R_CL;
109 if (!(REG_CX & ~regflags))
110 return R_CX;
111 if (!(REG_ECX & ~regflags))
112 return R_ECX;
113 if (!(REG_RCX & ~regflags))
114 return R_RCX;
115 if (!(FPU0 & ~regflags))
116 return R_ST0;
117 if (!(XMM0 & ~regflags))
118 return R_XMM0;
119 if (!(YMM0 & ~regflags))
120 return R_YMM0;
121 if (!(REG_CS & ~regflags))
122 return (regval == 1) ? R_CS : 0;
123 if (!(REG_DESS & ~regflags))
124 return (regval == 0 || regval == 2
125 || regval == 3 ? nasm_rd_sreg[regval] : 0);
126 if (!(REG_FSGS & ~regflags))
127 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_SEG67 & ~regflags))
129 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
130
131 /* All the entries below look up regval in an 16-entry array */
132 if (regval < 0 || regval > 15)
133 return 0;
134
135 if (!(REG8 & ~regflags)) {
136 if (rex & REX_P)
137 return nasm_rd_reg8_rex[regval];
138 else
139 return nasm_rd_reg8[regval];
140 }
141 if (!(REG16 & ~regflags))
142 return nasm_rd_reg16[regval];
143 if (!(REG32 & ~regflags))
144 return nasm_rd_reg32[regval];
145 if (!(REG64 & ~regflags))
146 return nasm_rd_reg64[regval];
147 if (!(REG_SREG & ~regflags))
148 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
149 if (!(REG_CREG & ~regflags))
150 return nasm_rd_creg[regval];
151 if (!(REG_DREG & ~regflags))
152 return nasm_rd_dreg[regval];
153 if (!(REG_TREG & ~regflags)) {
154 if (rex & REX_P)
155 return 0; /* TR registers are ill-defined with rex */
156 return nasm_rd_treg[regval];
157 }
158 if (!(FPUREG & ~regflags))
159 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
160 if (!(MMXREG & ~regflags))
161 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
162 if (!(XMMREG & ~regflags))
163 return nasm_rd_xmmreg[regval];
164 if (!(YMMREG & ~regflags))
165 return nasm_rd_ymmreg[regval];
166
167 return 0;
168 }
169
170 /*
171 * Process a DREX suffix
172 */
173 static uint8_t *do_drex(uint8_t *data, insn *ins)
174 {
175 uint8_t drex = *data++;
176 operand *dst = &ins->oprs[ins->drexdst];
177
178 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
179 return NULL; /* OC0 mismatch */
180 ins->rex = (ins->rex & ~7) | (drex & 7);
181
182 dst->segment = SEG_RMREG;
183 dst->basereg = drex >> 4;
184 return data;
185 }
186
187
188 /*
189 * Process an effective address (ModRM) specification.
190 */
191 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
192 int segsize, operand * op, insn *ins)
193 {
194 int mod, rm, scale, index, base;
195 int rex;
196 uint8_t sib = 0;
197
198 mod = (modrm >> 6) & 03;
199 rm = modrm & 07;
200
201 if (mod != 3 && rm == 4 && asize != 16)
202 sib = *data++;
203
204 if (ins->rex & REX_D) {
205 data = do_drex(data, ins);
206 if (!data)
207 return NULL;
208 }
209 rex = ins->rex;
210
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
214 return data;
215 }
216
217 op->disp_size = 0;
218 op->eaflags = 0;
219
220 if (asize == 16) {
221 /*
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
226 */
227 op->indexreg = op->basereg = -1;
228 op->scale = 1; /* always, in 16 bits */
229 switch (rm) {
230 case 0:
231 op->basereg = R_BX;
232 op->indexreg = R_SI;
233 break;
234 case 1:
235 op->basereg = R_BX;
236 op->indexreg = R_DI;
237 break;
238 case 2:
239 op->basereg = R_BP;
240 op->indexreg = R_SI;
241 break;
242 case 3:
243 op->basereg = R_BP;
244 op->indexreg = R_DI;
245 break;
246 case 4:
247 op->basereg = R_SI;
248 break;
249 case 5:
250 op->basereg = R_DI;
251 break;
252 case 6:
253 op->basereg = R_BP;
254 break;
255 case 7:
256 op->basereg = R_BX;
257 break;
258 }
259 if (rm == 6 && mod == 0) { /* special case */
260 op->basereg = -1;
261 if (segsize != 16)
262 op->disp_size = 16;
263 mod = 2; /* fake disp16 */
264 }
265 switch (mod) {
266 case 0:
267 op->segment |= SEG_NODISP;
268 break;
269 case 1:
270 op->segment |= SEG_DISP8;
271 op->offset = (int8_t)*data++;
272 break;
273 case 2:
274 op->segment |= SEG_DISP16;
275 op->offset = *data++;
276 op->offset |= ((unsigned)*data++) << 8;
277 break;
278 }
279 return data;
280 } else {
281 /*
282 * Once again, <mod> specifies displacement size (this time
283 * none, byte or *dword*), while <rm> specifies the base
284 * register. Again, [EBP] is missing, replaced by a pure
285 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
286 * and RIP-relative addressing in 64-bit mode.
287 *
288 * However, rm=4
289 * indicates not a single base register, but instead the
290 * presence of a SIB byte...
291 */
292 int a64 = asize == 64;
293
294 op->indexreg = -1;
295
296 if (a64)
297 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
298 else
299 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
300
301 if (rm == 5 && mod == 0) {
302 if (segsize == 64) {
303 op->eaflags |= EAF_REL;
304 op->segment |= SEG_RELATIVE;
305 mod = 2; /* fake disp32 */
306 }
307
308 if (asize != 64)
309 op->disp_size = asize;
310
311 op->basereg = -1;
312 mod = 2; /* fake disp32 */
313 }
314
315 if (rm == 4) { /* process SIB */
316 scale = (sib >> 6) & 03;
317 index = (sib >> 3) & 07;
318 base = sib & 07;
319
320 op->scale = 1 << scale;
321
322 if (index == 4 && !(rex & REX_X))
323 op->indexreg = -1; /* ESP/RSP cannot be an index */
324 else if (a64)
325 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
326 else
327 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
328
329 if (base == 5 && mod == 0) {
330 op->basereg = -1;
331 mod = 2; /* Fake disp32 */
332 } else if (a64)
333 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
334 else
335 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
336
337 if (segsize == 16)
338 op->disp_size = 32;
339 }
340
341 switch (mod) {
342 case 0:
343 op->segment |= SEG_NODISP;
344 break;
345 case 1:
346 op->segment |= SEG_DISP8;
347 op->offset = gets8(data);
348 data++;
349 break;
350 case 2:
351 op->segment |= SEG_DISP32;
352 op->offset = gets32(data);
353 data += 4;
354 break;
355 }
356 return data;
357 }
358 }
359
360 /*
361 * Determine whether the instruction template in t corresponds to the data
362 * stream in data. Return the number of bytes matched if so.
363 */
364 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
365
366 static int matches(const struct itemplate *t, uint8_t *data,
367 const struct prefix_info *prefix, int segsize, insn *ins)
368 {
369 uint8_t *r = (uint8_t *)(t->code);
370 uint8_t *origdata = data;
371 bool a_used = false, o_used = false;
372 enum prefixes drep = 0;
373 uint8_t lock = prefix->lock;
374 int osize = prefix->osize;
375 int asize = prefix->asize;
376 int i, c;
377 struct operand *opx;
378 int s_field_for = -1; /* No 144/154 series code encountered */
379 bool vex_ok = false;
380 int regmask = (segsize == 64) ? 15 : 7;
381
382 for (i = 0; i < MAX_OPERANDS; i++) {
383 ins->oprs[i].segment = ins->oprs[i].disp_size =
384 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
385 }
386 ins->condition = -1;
387 ins->rex = prefix->rex;
388 memset(ins->prefixes, 0, sizeof ins->prefixes);
389
390 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
391 return false;
392
393 if (prefix->rep == 0xF2)
394 drep = P_REPNE;
395 else if (prefix->rep == 0xF3)
396 drep = P_REP;
397
398 while ((c = *r++) != 0) {
399 opx = &ins->oprs[c & 3];
400
401 switch (c) {
402 case 01:
403 case 02:
404 case 03:
405 while (c--)
406 if (*r++ != *data++)
407 return false;
408 break;
409
410 case 04:
411 switch (*data++) {
412 case 0x07:
413 ins->oprs[0].basereg = 0;
414 break;
415 case 0x17:
416 ins->oprs[0].basereg = 2;
417 break;
418 case 0x1F:
419 ins->oprs[0].basereg = 3;
420 break;
421 default:
422 return false;
423 }
424 break;
425
426 case 05:
427 switch (*data++) {
428 case 0xA1:
429 ins->oprs[0].basereg = 4;
430 break;
431 case 0xA9:
432 ins->oprs[0].basereg = 5;
433 break;
434 default:
435 return false;
436 }
437 break;
438
439 case 06:
440 switch (*data++) {
441 case 0x06:
442 ins->oprs[0].basereg = 0;
443 break;
444 case 0x0E:
445 ins->oprs[0].basereg = 1;
446 break;
447 case 0x16:
448 ins->oprs[0].basereg = 2;
449 break;
450 case 0x1E:
451 ins->oprs[0].basereg = 3;
452 break;
453 default:
454 return false;
455 }
456 break;
457
458 case 07:
459 switch (*data++) {
460 case 0xA0:
461 ins->oprs[0].basereg = 4;
462 break;
463 case 0xA8:
464 ins->oprs[0].basereg = 5;
465 break;
466 default:
467 return false;
468 }
469 break;
470
471 case4(010):
472 {
473 int t = *r++, d = *data++;
474 if (d < t || d > t + 7)
475 return false;
476 else {
477 opx->basereg = (d-t)+
478 (ins->rex & REX_B ? 8 : 0);
479 opx->segment |= SEG_RMREG;
480 }
481 break;
482 }
483
484 case4(014):
485 opx->offset = (int8_t)*data++;
486 opx->segment |= SEG_SIGNED;
487 break;
488
489 case4(020):
490 opx->offset = *data++;
491 break;
492
493 case4(024):
494 opx->offset = *data++;
495 break;
496
497 case4(030):
498 opx->offset = getu16(data);
499 data += 2;
500 break;
501
502 case4(034):
503 if (osize == 32) {
504 opx->offset = getu32(data);
505 data += 4;
506 } else {
507 opx->offset = getu16(data);
508 data += 2;
509 }
510 if (segsize != asize)
511 opx->disp_size = asize;
512 break;
513
514 case4(040):
515 opx->offset = getu32(data);
516 data += 4;
517 break;
518
519 case4(044):
520 switch (asize) {
521 case 16:
522 opx->offset = getu16(data);
523 data += 2;
524 if (segsize != 16)
525 opx->disp_size = 16;
526 break;
527 case 32:
528 opx->offset = getu32(data);
529 data += 4;
530 if (segsize == 16)
531 opx->disp_size = 32;
532 break;
533 case 64:
534 opx->offset = getu64(data);
535 opx->disp_size = 64;
536 data += 8;
537 break;
538 }
539 break;
540
541 case4(050):
542 opx->offset = gets8(data++);
543 opx->segment |= SEG_RELATIVE;
544 break;
545
546 case4(054):
547 opx->offset = getu64(data);
548 data += 8;
549 break;
550
551 case4(060):
552 opx->offset = gets16(data);
553 data += 2;
554 opx->segment |= SEG_RELATIVE;
555 opx->segment &= ~SEG_32BIT;
556 break;
557
558 case4(064):
559 opx->segment |= SEG_RELATIVE;
560 if (osize == 16) {
561 opx->offset = gets16(data);
562 data += 2;
563 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
564 } else if (osize == 32) {
565 opx->offset = gets32(data);
566 data += 4;
567 opx->segment &= ~SEG_64BIT;
568 opx->segment |= SEG_32BIT;
569 }
570 if (segsize != osize) {
571 opx->type =
572 (opx->type & ~SIZE_MASK)
573 | ((osize == 16) ? BITS16 : BITS32);
574 }
575 break;
576
577 case4(070):
578 opx->offset = gets32(data);
579 data += 4;
580 opx->segment |= SEG_32BIT | SEG_RELATIVE;
581 break;
582
583 case4(0100):
584 case4(0110):
585 case4(0120):
586 case4(0130):
587 {
588 int modrm = *data++;
589 opx->segment |= SEG_RMREG;
590 data = do_ea(data, modrm, asize, segsize,
591 &ins->oprs[(c >> 3) & 3], ins);
592 if (!data)
593 return false;
594 opx->basereg = ((modrm >> 3)&7)+
595 (ins->rex & REX_R ? 8 : 0);
596 break;
597 }
598
599 case4(0140):
600 if (s_field_for == (c & 3)) {
601 opx->offset = gets8(data);
602 data++;
603 } else {
604 opx->offset = getu16(data);
605 data += 2;
606 }
607 break;
608
609 case4(0144):
610 case4(0154):
611 s_field_for = (*data & 0x02) ? c & 3 : -1;
612 if ((*data++ & ~0x02) != *r++)
613 return false;
614 break;
615
616 case4(0150):
617 if (s_field_for == (c & 3)) {
618 opx->offset = gets8(data);
619 data++;
620 } else {
621 opx->offset = getu32(data);
622 data += 4;
623 }
624 break;
625
626 case4(0160):
627 ins->rex |= REX_D;
628 ins->drexdst = c & 3;
629 break;
630
631 case4(0164):
632 ins->rex |= REX_D|REX_OC;
633 ins->drexdst = c & 3;
634 break;
635
636 case 0171:
637 data = do_drex(data, ins);
638 if (!data)
639 return false;
640 break;
641
642 case 0172:
643 {
644 uint8_t ximm = *data++;
645 c = *r++;
646 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
647 ins->oprs[c >> 3].segment |= SEG_RMREG;
648 ins->oprs[c & 7].offset = ximm & 15;
649 }
650 break;
651
652 case 0173:
653 {
654 uint8_t ximm = *data++;
655 c = *r++;
656
657 if ((c ^ ximm) & 15)
658 return false;
659
660 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
661 ins->oprs[c >> 4].segment |= SEG_RMREG;
662 }
663 break;
664
665 case 0174:
666 {
667 uint8_t ximm = *data++;
668 c = *r++;
669
670 ins->oprs[c].basereg = (ximm >> 4) & regmask;
671 ins->oprs[c].segment |= SEG_RMREG;
672 }
673 break;
674
675 case4(0200):
676 case4(0204):
677 case4(0210):
678 case4(0214):
679 case4(0220):
680 case4(0224):
681 case4(0230):
682 case4(0234):
683 {
684 int modrm = *data++;
685 if (((modrm >> 3) & 07) != (c & 07))
686 return false; /* spare field doesn't match up */
687 data = do_ea(data, modrm, asize, segsize,
688 &ins->oprs[(c >> 3) & 07], ins);
689 if (!data)
690 return false;
691 break;
692 }
693
694 case4(0260):
695 {
696 int vexm = *r++;
697 int vexwlp = *r++;
698 ins->rex |= REX_V;
699 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
700 return false;
701
702 if ((vexm & 0x1f) != prefix->vex_m)
703 return false;
704
705 switch (vexwlp & 030) {
706 case 000:
707 if (prefix->rex & REX_W)
708 return false;
709 break;
710 case 010:
711 if (!(prefix->rex & REX_W))
712 return false;
713 ins->rex &= ~REX_W;
714 break;
715 case 020: /* VEX.W is a don't care */
716 ins->rex &= ~REX_W;
717 break;
718 case 030:
719 break;
720 }
721
722 if ((vexwlp & 007) != prefix->vex_lp)
723 return false;
724
725 opx->segment |= SEG_RMREG;
726 opx->basereg = prefix->vex_v;
727 vex_ok = true;
728 break;
729 }
730
731 case 0270:
732 {
733 int vexm = *r++;
734 int vexwlp = *r++;
735 ins->rex |= REX_V;
736 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
737 return false;
738
739 if ((vexm & 0x1f) != prefix->vex_m)
740 return false;
741
742 switch (vexwlp & 030) {
743 case 000:
744 if (ins->rex & REX_W)
745 return false;
746 break;
747 case 010:
748 if (!(ins->rex & REX_W))
749 return false;
750 break;
751 default:
752 break; /* Need to do anything special here? */
753 }
754
755 if ((vexwlp & 007) != prefix->vex_lp)
756 return false;
757
758 if (prefix->vex_v != 0)
759 return false;
760
761 vex_ok = true;
762 break;
763 }
764
765 case 0310:
766 if (asize != 16)
767 return false;
768 else
769 a_used = true;
770 break;
771
772 case 0311:
773 if (asize == 16)
774 return false;
775 else
776 a_used = true;
777 break;
778
779 case 0312:
780 if (asize != segsize)
781 return false;
782 else
783 a_used = true;
784 break;
785
786 case 0313:
787 if (asize != 64)
788 return false;
789 else
790 a_used = true;
791 break;
792
793 case 0314:
794 if (prefix->rex & REX_B)
795 return false;
796 break;
797
798 case 0315:
799 if (prefix->rex & REX_X)
800 return false;
801 break;
802
803 case 0316:
804 if (prefix->rex & REX_R)
805 return false;
806 break;
807
808 case 0317:
809 if (prefix->rex & REX_W)
810 return false;
811 break;
812
813 case 0320:
814 if (osize != 16)
815 return false;
816 else
817 o_used = true;
818 break;
819
820 case 0321:
821 if (osize != 32)
822 return false;
823 else
824 o_used = true;
825 break;
826
827 case 0322:
828 if (osize != (segsize == 16) ? 16 : 32)
829 return false;
830 else
831 o_used = true;
832 break;
833
834 case 0323:
835 ins->rex |= REX_W; /* 64-bit only instruction */
836 osize = 64;
837 o_used = true;
838 break;
839
840 case 0324:
841 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
842 return false;
843 o_used = true;
844 break;
845
846 case 0330:
847 {
848 int t = *r++, d = *data++;
849 if (d < t || d > t + 15)
850 return false;
851 else
852 ins->condition = d - t;
853 break;
854 }
855
856 case 0331:
857 if (prefix->rep)
858 return false;
859 break;
860
861 case 0332:
862 if (prefix->rep != 0xF2)
863 return false;
864 drep = 0;
865 break;
866
867 case 0333:
868 if (prefix->rep != 0xF3)
869 return false;
870 drep = 0;
871 break;
872
873 case 0334:
874 if (lock) {
875 ins->rex |= REX_R;
876 lock = 0;
877 }
878 break;
879
880 case 0335:
881 if (drep == P_REP)
882 drep = P_REPE;
883 break;
884
885 case 0336:
886 case 0337:
887 break;
888
889 case 0340:
890 return false;
891
892 case 0360:
893 if (prefix->osp || prefix->rep)
894 return false;
895 break;
896
897 case 0361:
898 if (!prefix->osp || prefix->rep)
899 return false;
900 o_used = true;
901 break;
902
903 case 0362:
904 if (prefix->osp || prefix->rep != 0xf2)
905 return false;
906 drep = 0;
907 break;
908
909 case 0363:
910 if (prefix->osp || prefix->rep != 0xf3)
911 return false;
912 drep = 0;
913 break;
914
915 case 0364:
916 if (prefix->osp)
917 return false;
918 break;
919
920 case 0365:
921 if (prefix->asp)
922 return false;
923 break;
924
925 case 0366:
926 if (!prefix->osp)
927 return false;
928 o_used = true;
929 break;
930
931 case 0367:
932 if (!prefix->asp)
933 return false;
934 a_used = true;
935 break;
936
937 default:
938 return false; /* Unknown code */
939 }
940 }
941
942 if (!vex_ok && (ins->rex & REX_V))
943 return false;
944
945 /* REX cannot be combined with DREX or VEX */
946 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
947 return false;
948
949 /*
950 * Check for unused rep or a/o prefixes.
951 */
952 for (i = 0; i < t->operands; i++) {
953 if (ins->oprs[i].segment != SEG_RMREG)
954 a_used = true;
955 }
956
957 if (lock) {
958 if (ins->prefixes[PPS_LREP])
959 return false;
960 ins->prefixes[PPS_LREP] = P_LOCK;
961 }
962 if (drep) {
963 if (ins->prefixes[PPS_LREP])
964 return false;
965 ins->prefixes[PPS_LREP] = drep;
966 }
967 if (!o_used) {
968 if (osize != ((segsize == 16) ? 16 : 32)) {
969 enum prefixes pfx = 0;
970
971 switch (osize) {
972 case 16:
973 pfx = P_O16;
974 break;
975 case 32:
976 pfx = P_O32;
977 break;
978 case 64:
979 pfx = P_O64;
980 break;
981 }
982
983 if (ins->prefixes[PPS_OSIZE])
984 return false;
985 ins->prefixes[PPS_OSIZE] = pfx;
986 }
987 }
988 if (!a_used && asize != segsize) {
989 if (ins->prefixes[PPS_ASIZE])
990 return false;
991 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
992 }
993
994 /* Fix: check for redundant REX prefixes */
995
996 return data - origdata;
997 }
998
999 /* Condition names for disassembly, sorted by x86 code */
1000 static const char * const condition_name[16] = {
1001 "o", "no", "c", "nc", "z", "nz", "na", "a",
1002 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
1003 };
1004
1005 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
1006 int32_t offset, int autosync, uint32_t prefer)
1007 {
1008 const struct itemplate * const *p, * const *best_p;
1009 const struct disasm_index *ix;
1010 uint8_t *dp;
1011 int length, best_length = 0;
1012 char *segover;
1013 int i, slen, colon, n;
1014 uint8_t *origdata;
1015 int works;
1016 insn tmp_ins, ins;
1017 uint32_t goodness, best;
1018 int best_pref;
1019 struct prefix_info prefix;
1020 bool end_prefix;
1021
1022 memset(&ins, 0, sizeof ins);
1023
1024 /*
1025 * Scan for prefixes.
1026 */
1027 memset(&prefix, 0, sizeof prefix);
1028 prefix.asize = segsize;
1029 prefix.osize = (segsize == 64) ? 32 : segsize;
1030 segover = NULL;
1031 origdata = data;
1032
1033 ix = itable;
1034
1035 end_prefix = false;
1036 while (!end_prefix) {
1037 switch (*data) {
1038 case 0xF2:
1039 case 0xF3:
1040 prefix.rep = *data++;
1041 break;
1042
1043 case 0xF0:
1044 prefix.lock = *data++;
1045 break;
1046
1047 case 0x2E:
1048 segover = "cs", prefix.seg = *data++;
1049 break;
1050 case 0x36:
1051 segover = "ss", prefix.seg = *data++;
1052 break;
1053 case 0x3E:
1054 segover = "ds", prefix.seg = *data++;
1055 break;
1056 case 0x26:
1057 segover = "es", prefix.seg = *data++;
1058 break;
1059 case 0x64:
1060 segover = "fs", prefix.seg = *data++;
1061 break;
1062 case 0x65:
1063 segover = "gs", prefix.seg = *data++;
1064 break;
1065
1066 case 0x66:
1067 prefix.osize = (segsize == 16) ? 32 : 16;
1068 prefix.osp = *data++;
1069 break;
1070 case 0x67:
1071 prefix.asize = (segsize == 32) ? 16 : 32;
1072 prefix.asp = *data++;
1073 break;
1074
1075 case 0xC4:
1076 case 0xC5:
1077 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1078 prefix.vex[0] = *data++;
1079 prefix.vex[1] = *data++;
1080
1081 prefix.rex = REX_V;
1082
1083 if (prefix.vex[0] == 0xc4) {
1084 prefix.vex[2] = *data++;
1085 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1086 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1087 prefix.vex_m = prefix.vex[1] & 0x1f;
1088 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1089 prefix.vex_lp = prefix.vex[2] & 7;
1090 } else {
1091 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1092 prefix.vex_m = 1;
1093 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1094 prefix.vex_lp = prefix.vex[1] & 7;
1095 }
1096
1097 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1098 }
1099 end_prefix = true;
1100 break;
1101
1102 case REX_P + 0x0:
1103 case REX_P + 0x1:
1104 case REX_P + 0x2:
1105 case REX_P + 0x3:
1106 case REX_P + 0x4:
1107 case REX_P + 0x5:
1108 case REX_P + 0x6:
1109 case REX_P + 0x7:
1110 case REX_P + 0x8:
1111 case REX_P + 0x9:
1112 case REX_P + 0xA:
1113 case REX_P + 0xB:
1114 case REX_P + 0xC:
1115 case REX_P + 0xD:
1116 case REX_P + 0xE:
1117 case REX_P + 0xF:
1118 if (segsize == 64) {
1119 prefix.rex = *data++;
1120 if (prefix.rex & REX_W)
1121 prefix.osize = 64;
1122 }
1123 end_prefix = true;
1124 break;
1125
1126 default:
1127 end_prefix = true;
1128 break;
1129 }
1130 }
1131
1132 best = -1; /* Worst possible */
1133 best_p = NULL;
1134 best_pref = INT_MAX;
1135
1136 if (!ix)
1137 return 0; /* No instruction table at all... */
1138
1139 dp = data;
1140 ix += *dp++;
1141 while (ix->n == -1) {
1142 ix = (const struct disasm_index *)ix->p + *dp++;
1143 }
1144
1145 p = (const struct itemplate * const *)ix->p;
1146 for (n = ix->n; n; n--, p++) {
1147 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1148 works = true;
1149 /*
1150 * Final check to make sure the types of r/m match up.
1151 * XXX: Need to make sure this is actually correct.
1152 */
1153 for (i = 0; i < (*p)->operands; i++) {
1154 if (!((*p)->opd[i] & SAME_AS) &&
1155 (
1156 /* If it's a mem-only EA but we have a
1157 register, die. */
1158 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1159 !(MEMORY & ~(*p)->opd[i])) ||
1160 /* If it's a reg-only EA but we have a memory
1161 ref, die. */
1162 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1163 !(REG_EA & ~(*p)->opd[i]) &&
1164 !((*p)->opd[i] & REG_SMASK)) ||
1165 /* Register type mismatch (eg FS vs REG_DESS):
1166 die. */
1167 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1168 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1169 !whichreg((*p)->opd[i],
1170 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1171 )) {
1172 works = false;
1173 break;
1174 }
1175 }
1176
1177 /*
1178 * Note: we always prefer instructions which incorporate
1179 * prefixes in the instructions themselves. This is to allow
1180 * e.g. PAUSE to be preferred to REP NOP, and deal with
1181 * MMX/SSE instructions where prefixes are used to select
1182 * between MMX and SSE register sets or outright opcode
1183 * selection.
1184 */
1185 if (works) {
1186 int i, nprefix;
1187 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1188 nprefix = 0;
1189 for (i = 0; i < MAXPREFIX; i++)
1190 if (tmp_ins.prefixes[i])
1191 nprefix++;
1192 if (nprefix < best_pref ||
1193 (nprefix == best_pref && goodness < best)) {
1194 /* This is the best one found so far */
1195 best = goodness;
1196 best_p = p;
1197 best_pref = nprefix;
1198 best_length = length;
1199 ins = tmp_ins;
1200 }
1201 }
1202 }
1203 }
1204
1205 if (!best_p)
1206 return 0; /* no instruction was matched */
1207
1208 /* Pick the best match */
1209 p = best_p;
1210 length = best_length;
1211
1212 slen = 0;
1213
1214 /* TODO: snprintf returns the value that the string would have if
1215 * the buffer were long enough, and not the actual length of
1216 * the returned string, so each instance of using the return
1217 * value of snprintf should actually be checked to assure that
1218 * the return value is "sane." Maybe a macro wrapper could
1219 * be used for that purpose.
1220 */
1221 for (i = 0; i < MAXPREFIX; i++)
1222 switch (ins.prefixes[i]) {
1223 case P_LOCK:
1224 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1225 break;
1226 case P_REP:
1227 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1228 break;
1229 case P_REPE:
1230 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1231 break;
1232 case P_REPNE:
1233 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1234 break;
1235 case P_A16:
1236 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1237 break;
1238 case P_A32:
1239 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1240 break;
1241 case P_A64:
1242 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1243 break;
1244 case P_O16:
1245 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1246 break;
1247 case P_O32:
1248 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1249 break;
1250 case P_O64:
1251 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1252 break;
1253 default:
1254 break;
1255 }
1256
1257 i = (*p)->opcode;
1258 if (i >= FIRST_COND_OPCODE)
1259 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1260 nasm_insn_names[i], condition_name[ins.condition]);
1261 else
1262 slen += snprintf(output + slen, outbufsize - slen, "%s",
1263 nasm_insn_names[i]);
1264
1265 colon = false;
1266 length += data - origdata; /* fix up for prefixes */
1267 for (i = 0; i < (*p)->operands; i++) {
1268 opflags_t t = (*p)->opd[i];
1269 const operand *o = &ins.oprs[i];
1270 int64_t offs;
1271
1272 if (t & SAME_AS) {
1273 o = &ins.oprs[t & ~SAME_AS];
1274 t = (*p)->opd[t & ~SAME_AS];
1275 }
1276
1277 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1278
1279 offs = o->offset;
1280 if (o->segment & SEG_RELATIVE) {
1281 offs += offset + length;
1282 /*
1283 * sort out wraparound
1284 */
1285 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1286 offs &= 0xffff;
1287 else if (segsize != 64)
1288 offs &= 0xffffffff;
1289
1290 /*
1291 * add sync marker, if autosync is on
1292 */
1293 if (autosync)
1294 add_sync(offs, 0L);
1295 }
1296
1297 if (t & COLON)
1298 colon = true;
1299 else
1300 colon = false;
1301
1302 if ((t & (REGISTER | FPUREG)) ||
1303 (o->segment & SEG_RMREG)) {
1304 enum reg_enum reg;
1305 reg = whichreg(t, o->basereg, ins.rex);
1306 if (t & TO)
1307 slen += snprintf(output + slen, outbufsize - slen, "to ");
1308 slen += snprintf(output + slen, outbufsize - slen, "%s",
1309 nasm_reg_names[reg-EXPR_REG_START]);
1310 } else if (!(UNITY & ~t)) {
1311 output[slen++] = '1';
1312 } else if (t & IMMEDIATE) {
1313 if (t & BITS8) {
1314 slen +=
1315 snprintf(output + slen, outbufsize - slen, "byte ");
1316 if (o->segment & SEG_SIGNED) {
1317 if (offs < 0) {
1318 offs *= -1;
1319 output[slen++] = '-';
1320 } else
1321 output[slen++] = '+';
1322 }
1323 } else if (t & BITS16) {
1324 slen +=
1325 snprintf(output + slen, outbufsize - slen, "word ");
1326 } else if (t & BITS32) {
1327 slen +=
1328 snprintf(output + slen, outbufsize - slen, "dword ");
1329 } else if (t & BITS64) {
1330 slen +=
1331 snprintf(output + slen, outbufsize - slen, "qword ");
1332 } else if (t & NEAR) {
1333 slen +=
1334 snprintf(output + slen, outbufsize - slen, "near ");
1335 } else if (t & SHORT) {
1336 slen +=
1337 snprintf(output + slen, outbufsize - slen, "short ");
1338 }
1339 slen +=
1340 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1341 offs);
1342 } else if (!(MEM_OFFS & ~t)) {
1343 slen +=
1344 snprintf(output + slen, outbufsize - slen,
1345 "[%s%s%s0x%"PRIx64"]",
1346 (segover ? segover : ""),
1347 (segover ? ":" : ""),
1348 (o->disp_size == 64 ? "qword " :
1349 o->disp_size == 32 ? "dword " :
1350 o->disp_size == 16 ? "word " : ""), offs);
1351 segover = NULL;
1352 } else if (!(REGMEM & ~t)) {
1353 int started = false;
1354 if (t & BITS8)
1355 slen +=
1356 snprintf(output + slen, outbufsize - slen, "byte ");
1357 if (t & BITS16)
1358 slen +=
1359 snprintf(output + slen, outbufsize - slen, "word ");
1360 if (t & BITS32)
1361 slen +=
1362 snprintf(output + slen, outbufsize - slen, "dword ");
1363 if (t & BITS64)
1364 slen +=
1365 snprintf(output + slen, outbufsize - slen, "qword ");
1366 if (t & BITS80)
1367 slen +=
1368 snprintf(output + slen, outbufsize - slen, "tword ");
1369 if (t & BITS128)
1370 slen +=
1371 snprintf(output + slen, outbufsize - slen, "oword ");
1372 if (t & BITS256)
1373 slen +=
1374 snprintf(output + slen, outbufsize - slen, "yword ");
1375 if (t & FAR)
1376 slen += snprintf(output + slen, outbufsize - slen, "far ");
1377 if (t & NEAR)
1378 slen +=
1379 snprintf(output + slen, outbufsize - slen, "near ");
1380 output[slen++] = '[';
1381 if (o->disp_size)
1382 slen += snprintf(output + slen, outbufsize - slen, "%s",
1383 (o->disp_size == 64 ? "qword " :
1384 o->disp_size == 32 ? "dword " :
1385 o->disp_size == 16 ? "word " :
1386 ""));
1387 if (o->eaflags & EAF_REL)
1388 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1389 if (segover) {
1390 slen +=
1391 snprintf(output + slen, outbufsize - slen, "%s:",
1392 segover);
1393 segover = NULL;
1394 }
1395 if (o->basereg != -1) {
1396 slen += snprintf(output + slen, outbufsize - slen, "%s",
1397 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1398 started = true;
1399 }
1400 if (o->indexreg != -1) {
1401 if (started)
1402 output[slen++] = '+';
1403 slen += snprintf(output + slen, outbufsize - slen, "%s",
1404 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1405 if (o->scale > 1)
1406 slen +=
1407 snprintf(output + slen, outbufsize - slen, "*%d",
1408 o->scale);
1409 started = true;
1410 }
1411
1412
1413 if (o->segment & SEG_DISP8) {
1414 const char *prefix;
1415 uint8_t offset = offs;
1416 if ((int8_t)offset < 0) {
1417 prefix = "-";
1418 offset = -offset;
1419 } else {
1420 prefix = "+";
1421 }
1422 slen +=
1423 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1424 prefix, offset);
1425 } else if (o->segment & SEG_DISP16) {
1426 const char *prefix;
1427 uint16_t offset = offs;
1428 if ((int16_t)offset < 0 && started) {
1429 offset = -offset;
1430 prefix = "-";
1431 } else {
1432 prefix = started ? "+" : "";
1433 }
1434 slen +=
1435 snprintf(output + slen, outbufsize - slen,
1436 "%s0x%"PRIx16"", prefix, offset);
1437 } else if (o->segment & SEG_DISP32) {
1438 if (prefix.asize == 64) {
1439 const char *prefix;
1440 uint64_t offset = (int64_t)(int32_t)offs;
1441 if ((int32_t)offs < 0 && started) {
1442 offset = -offset;
1443 prefix = "-";
1444 } else {
1445 prefix = started ? "+" : "";
1446 }
1447 slen +=
1448 snprintf(output + slen, outbufsize - slen,
1449 "%s0x%"PRIx64"", prefix, offset);
1450 } else {
1451 const char *prefix;
1452 uint32_t offset = offs;
1453 if ((int32_t) offset < 0 && started) {
1454 offset = -offset;
1455 prefix = "-";
1456 } else {
1457 prefix = started ? "+" : "";
1458 }
1459 slen +=
1460 snprintf(output + slen, outbufsize - slen,
1461 "%s0x%"PRIx32"", prefix, offset);
1462 }
1463 }
1464 output[slen++] = ']';
1465 } else {
1466 slen +=
1467 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1468 i);
1469 }
1470 }
1471 output[slen] = '\0';
1472 if (segover) { /* unused segment override */
1473 char *p = output;
1474 int count = slen + 1;
1475 while (count--)
1476 p[count + 3] = p[count];
1477 strncpy(output, segover, 2);
1478 output[2] = ' ';
1479 }
1480 return length;
1481 }
1482
1483 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1484 {
1485 snprintf(output, outbufsize, "db 0x%02X", *data);
1486 return 1;
1487 }
The Netwide Assembler