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outmac: move the format definitions down to the format-specific code
[nasm.git] / assemble.c
blobacaf24bf35ea7a89457fcb30e483396a147e6211
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2016 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * Bytecode specification
38 * ----------------------
39 *
40 *
41 * Codes Mnemonic Explanation
42 *
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
76 *
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
81 *
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
84 * cc 000 0mm
85 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
86 * and wlp is:
87 * 00 wwl lpp
88 * [l0] ll = 0 (.128, .lz)
89 * [l1] ll = 1 (.256)
90 * [l2] ll = 2 (.512)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
100 * [f3] pp = 2
101 * [f2] pp = 3
102 *
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
105 *
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
111 *
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
114 * 00 wwl lpp
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
118 *
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
123 *
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
125 *
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
176 */
177
178 #include "compiler.h"
179
180 #include <stdio.h>
181 #include <string.h>
182 #include <stdlib.h>
183 #include <inttypes.h>
184
185 #include "nasm.h"
186 #include "nasmlib.h"
187 #include "assemble.h"
188 #include "insns.h"
189 #include "tables.h"
190 #include "disp8.h"
191
192 enum match_result {
193 /*
194 * Matching errors. These should be sorted so that more specific
195 * errors come later in the sequence.
196 */
197 MERR_INVALOP,
198 MERR_OPSIZEMISSING,
199 MERR_OPSIZEMISMATCH,
200 MERR_BRNUMMISMATCH,
201 MERR_BADCPU,
202 MERR_BADMODE,
203 MERR_BADHLE,
204 MERR_ENCMISMATCH,
205 MERR_BADBND,
206 MERR_BADREPNE,
207 /*
208 * Matching success; the conditional ones first
209 */
210 MOK_JUMP, /* Matching OK but needs jmp_match() */
211 MOK_GOOD /* Matching unconditionally OK */
212 };
213
214 typedef struct {
215 enum ea_type type; /* what kind of EA is this? */
216 int sib_present; /* is a SIB byte necessary? */
217 int bytes; /* # of bytes of offset needed */
218 int size; /* lazy - this is sib+bytes+1 */
219 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
220 int8_t disp8; /* compressed displacement for EVEX */
221 } ea;
222
223 #define GEN_SIB(scale, index, base) \
224 (((scale) << 6) | ((index) << 3) | ((base)))
225
226 #define GEN_MODRM(mod, reg, rm) \
227 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
228
229 static iflag_t cpu; /* cpu level received from nasm.c */
230 static efunc errfunc;
231 static struct ofmt *outfmt;
232 static ListGen *list;
233
234 static int64_t calcsize(int32_t, int64_t, int, insn *,
235 const struct itemplate *);
236 static void gencode(int32_t segment, int64_t offset, int bits,
237 insn * ins, const struct itemplate *temp,
238 int64_t insn_end);
239 static enum match_result find_match(const struct itemplate **tempp,
240 insn *instruction,
241 int32_t segment, int64_t offset, int bits);
242 static enum match_result matches(const struct itemplate *, insn *, int bits);
243 static opflags_t regflag(const operand *);
244 static int32_t regval(const operand *);
245 static int rexflags(int, opflags_t, int);
246 static int op_rexflags(const operand *, int);
247 static int op_evexflags(const operand *, int, uint8_t);
248 static void add_asp(insn *, int);
249
250 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
251
252 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
253 {
254 return ins->prefixes[pos] == prefix;
255 }
256
257 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
258 {
259 if (ins->prefixes[pos])
260 errfunc(ERR_NONFATAL, "invalid %s prefix",
261 prefix_name(ins->prefixes[pos]));
262 }
263
264 static const char *size_name(int size)
265 {
266 switch (size) {
267 case 1:
268 return "byte";
269 case 2:
270 return "word";
271 case 4:
272 return "dword";
273 case 8:
274 return "qword";
275 case 10:
276 return "tword";
277 case 16:
278 return "oword";
279 case 32:
280 return "yword";
281 case 64:
282 return "zword";
283 default:
284 return "???";
285 }
286 }
287
288 static void warn_overflow(int pass, int size)
289 {
290 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
291 "%s data exceeds bounds", size_name(size));
292 }
293
294 static void warn_overflow_const(int64_t data, int size)
295 {
296 if (overflow_general(data, size))
297 warn_overflow(ERR_PASS1, size);
298 }
299
300 static void warn_overflow_opd(const struct operand *o, int size)
301 {
302 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
303 if (overflow_general(o->offset, size))
304 warn_overflow(ERR_PASS2, size);
305 }
306 }
307
308 /*
309 * Size of an address relocation, or zero if not an address
310 */
311 static int addrsize(enum out_type type, uint64_t size)
312 {
313 switch (type) {
314 case OUT_ADDRESS:
315 return abs((int)size);
316 case OUT_REL1ADR:
317 return 1;
318 case OUT_REL2ADR:
319 return 2;
320 case OUT_REL4ADR:
321 return 4;
322 case OUT_REL8ADR:
323 return 8;
324 default:
325 return 0;
326 }
327 }
328
329 /*
330 * This routine wrappers the real output format's output routine,
331 * in order to pass a copy of the data off to the listing file
332 * generator at the same time, flatten unnecessary relocations,
333 * and verify backend compatibility.
334 */
335 static void out(int64_t offset, int32_t segto, const void *data,
336 enum out_type type, uint64_t size,
337 int32_t segment, int32_t wrt)
338 {
339 static int32_t lineno = 0; /* static!!! */
340 static char *lnfname = NULL;
341 uint8_t p[8];
342 int asize = addrsize(type, size); /* Address size in bytes */
343 const int amax = outfmt->maxbits >> 3; /* Maximum address size in bytes */
344
345 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
346 /*
347 * This is a non-relocated address, and we're going to
348 * convert it into RAWDATA format.
349 */
350 uint8_t *q = p;
351
352 if (asize > 8) {
353 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
354 return;
355 }
356
357 WRITEADDR(q, *(int64_t *)data, asize);
358 data = p;
359 type = OUT_RAWDATA;
360
361 asize = 0; /* No longer an address */
362 }
363
364 list->output(offset, data, type, size);
365
366 /*
367 * this call to src_get determines when we call the
368 * debug-format-specific "linenum" function
369 * it updates lineno and lnfname to the current values
370 * returning 0 if "same as last time", -2 if lnfname
371 * changed, and the amount by which lineno changed,
372 * if it did. thus, these variables must be static
373 */
374
375 if (src_get(&lineno, &lnfname))
376 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
377
378 if (asize && asize > amax) {
379 if (type != OUT_ADDRESS || (int)size < 0) {
380 errfunc(ERR_NONFATAL,
381 "%d-bit signed relocation unsupported by output format %s\n",
382 asize << 3, outfmt->shortname);
383 } else {
384 errfunc(ERR_WARNING | ERR_WARN_ZEXTRELOC,
385 "%d-bit unsigned relocation zero-extended from %d bits\n",
386 asize << 3, outfmt->maxbits);
387 outfmt->output(segto, data, type, amax, segment, wrt);
388 size -= amax;
389 }
390 data = zero_buffer;
391 type = OUT_RAWDATA;
392 segment = wrt = NO_SEG;
393 }
394
395 outfmt->output(segto, data, type, size, segment, wrt);
396 }
397
398 static void out_imm8(int64_t offset, int32_t segment,
399 struct operand *opx, int asize)
400 {
401 if (opx->segment != NO_SEG) {
402 uint64_t data = opx->offset;
403 out(offset, segment, &data, OUT_ADDRESS, asize, opx->segment, opx->wrt);
404 } else {
405 uint8_t byte = opx->offset;
406 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
407 }
408 }
409
410 static bool jmp_match(int32_t segment, int64_t offset, int bits,
411 insn * ins, const struct itemplate *temp)
412 {
413 int64_t isize;
414 const uint8_t *code = temp->code;
415 uint8_t c = code[0];
416 bool is_byte;
417
418 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
419 return false;
420 if (!optimizing)
421 return false;
422 if (optimizing < 0 && c == 0371)
423 return false;
424
425 isize = calcsize(segment, offset, bits, ins, temp);
426
427 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
428 /* Be optimistic in pass 1 */
429 return true;
430
431 if (ins->oprs[0].segment != segment)
432 return false;
433
434 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
435 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
436
437 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
438 /* jmp short (opcode eb) cannot be used with bnd prefix. */
439 ins->prefixes[PPS_REP] = P_none;
440 errfunc(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
441 "jmp short does not init bnd regs - bnd prefix dropped.");
442 }
443
444 return is_byte;
445 }
446
447 int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
448 insn * instruction, struct ofmt *output, efunc error,
449 ListGen * listgen)
450 {
451 const struct itemplate *temp;
452 int j;
453 enum match_result m;
454 int64_t insn_end;
455 int32_t itimes;
456 int64_t start = offset;
457 int64_t wsize; /* size for DB etc. */
458
459 errfunc = error; /* to pass to other functions */
460 cpu = cp;
461 outfmt = output; /* likewise */
462 list = listgen; /* and again */
463
464 wsize = idata_bytes(instruction->opcode);
465 if (wsize == -1)
466 return 0;
467
468 if (wsize) {
469 extop *e;
470 int32_t t = instruction->times;
471 if (t < 0)
472 errfunc(ERR_PANIC,
473 "instruction->times < 0 (%ld) in assemble()", t);
474
475 while (t--) { /* repeat TIMES times */
476 list_for_each(e, instruction->eops) {
477 if (e->type == EOT_DB_NUMBER) {
478 if (wsize > 8) {
479 errfunc(ERR_NONFATAL,
480 "integer supplied to a DT, DO or DY"
481 " instruction");
482 } else {
483 out(offset, segment, &e->offset,
484 OUT_ADDRESS, wsize, e->segment, e->wrt);
485 offset += wsize;
486 }
487 } else if (e->type == EOT_DB_STRING ||
488 e->type == EOT_DB_STRING_FREE) {
489 int align;
490
491 out(offset, segment, e->stringval,
492 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
493 align = e->stringlen % wsize;
494
495 if (align) {
496 align = wsize - align;
497 out(offset, segment, zero_buffer,
498 OUT_RAWDATA, align, NO_SEG, NO_SEG);
499 }
500 offset += e->stringlen + align;
501 }
502 }
503 if (t > 0 && t == instruction->times - 1) {
504 /*
505 * Dummy call to list->output to give the offset to the
506 * listing module.
507 */
508 list->output(offset, NULL, OUT_RAWDATA, 0);
509 list->uplevel(LIST_TIMES);
510 }
511 }
512 if (instruction->times > 1)
513 list->downlevel(LIST_TIMES);
514 return offset - start;
515 }
516
517 if (instruction->opcode == I_INCBIN) {
518 const char *fname = instruction->eops->stringval;
519 FILE *fp;
520
521 fp = fopen(fname, "rb");
522 if (!fp) {
523 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
524 fname);
525 } else if (fseek(fp, 0L, SEEK_END) < 0) {
526 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
527 fname);
528 fclose(fp);
529 } else {
530 static char buf[4096];
531 size_t t = instruction->times;
532 size_t base = 0;
533 size_t len;
534
535 len = ftell(fp);
536 if (instruction->eops->next) {
537 base = instruction->eops->next->offset;
538 len -= base;
539 if (instruction->eops->next->next &&
540 len > (size_t)instruction->eops->next->next->offset)
541 len = (size_t)instruction->eops->next->next->offset;
542 }
543 /*
544 * Dummy call to list->output to give the offset to the
545 * listing module.
546 */
547 list->output(offset, NULL, OUT_RAWDATA, 0);
548 list->uplevel(LIST_INCBIN);
549 while (t--) {
550 size_t l;
551
552 fseek(fp, base, SEEK_SET);
553 l = len;
554 while (l > 0) {
555 int32_t m;
556 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
557 if (!m) {
558 /*
559 * This shouldn't happen unless the file
560 * actually changes while we are reading
561 * it.
562 */
563 error(ERR_NONFATAL,
564 "`incbin': unexpected EOF while"
565 " reading file `%s'", fname);
566 t = 0; /* Try to exit cleanly */
567 break;
568 }
569 out(offset, segment, buf, OUT_RAWDATA, m,
570 NO_SEG, NO_SEG);
571 l -= m;
572 }
573 }
574 list->downlevel(LIST_INCBIN);
575 if (instruction->times > 1) {
576 /*
577 * Dummy call to list->output to give the offset to the
578 * listing module.
579 */
580 list->output(offset, NULL, OUT_RAWDATA, 0);
581 list->uplevel(LIST_TIMES);
582 list->downlevel(LIST_TIMES);
583 }
584 fclose(fp);
585 return instruction->times * len;
586 }
587 return 0; /* if we're here, there's an error */
588 }
589
590 /* Check to see if we need an address-size prefix */
591 add_asp(instruction, bits);
592
593 m = find_match(&temp, instruction, segment, offset, bits);
594
595 if (m == MOK_GOOD) {
596 /* Matches! */
597 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
598 itimes = instruction->times;
599 if (insn_size < 0) /* shouldn't be, on pass two */
600 error(ERR_PANIC, "errors made it through from pass one");
601 else
602 while (itimes--) {
603 for (j = 0; j < MAXPREFIX; j++) {
604 uint8_t c = 0;
605 switch (instruction->prefixes[j]) {
606 case P_WAIT:
607 c = 0x9B;
608 break;
609 case P_LOCK:
610 c = 0xF0;
611 break;
612 case P_REPNE:
613 case P_REPNZ:
614 case P_XACQUIRE:
615 case P_BND:
616 c = 0xF2;
617 break;
618 case P_REPE:
619 case P_REPZ:
620 case P_REP:
621 case P_XRELEASE:
622 c = 0xF3;
623 break;
624 case R_CS:
625 if (bits == 64) {
626 error(ERR_WARNING | ERR_PASS2,
627 "cs segment base generated, but will be ignored in 64-bit mode");
628 }
629 c = 0x2E;
630 break;
631 case R_DS:
632 if (bits == 64) {
633 error(ERR_WARNING | ERR_PASS2,
634 "ds segment base generated, but will be ignored in 64-bit mode");
635 }
636 c = 0x3E;
637 break;
638 case R_ES:
639 if (bits == 64) {
640 error(ERR_WARNING | ERR_PASS2,
641 "es segment base generated, but will be ignored in 64-bit mode");
642 }
643 c = 0x26;
644 break;
645 case R_FS:
646 c = 0x64;
647 break;
648 case R_GS:
649 c = 0x65;
650 break;
651 case R_SS:
652 if (bits == 64) {
653 error(ERR_WARNING | ERR_PASS2,
654 "ss segment base generated, but will be ignored in 64-bit mode");
655 }
656 c = 0x36;
657 break;
658 case R_SEGR6:
659 case R_SEGR7:
660 error(ERR_NONFATAL,
661 "segr6 and segr7 cannot be used as prefixes");
662 break;
663 case P_A16:
664 if (bits == 64) {
665 error(ERR_NONFATAL,
666 "16-bit addressing is not supported "
667 "in 64-bit mode");
668 } else if (bits != 16)
669 c = 0x67;
670 break;
671 case P_A32:
672 if (bits != 32)
673 c = 0x67;
674 break;
675 case P_A64:
676 if (bits != 64) {
677 error(ERR_NONFATAL,
678 "64-bit addressing is only supported "
679 "in 64-bit mode");
680 }
681 break;
682 case P_ASP:
683 c = 0x67;
684 break;
685 case P_O16:
686 if (bits != 16)
687 c = 0x66;
688 break;
689 case P_O32:
690 if (bits == 16)
691 c = 0x66;
692 break;
693 case P_O64:
694 /* REX.W */
695 break;
696 case P_OSP:
697 c = 0x66;
698 break;
699 case P_EVEX:
700 case P_VEX3:
701 case P_VEX2:
702 case P_NOBND:
703 case P_none:
704 break;
705 default:
706 error(ERR_PANIC, "invalid instruction prefix");
707 }
708 if (c != 0) {
709 out(offset, segment, &c, OUT_RAWDATA, 1,
710 NO_SEG, NO_SEG);
711 offset++;
712 }
713 }
714 insn_end = offset + insn_size;
715 gencode(segment, offset, bits, instruction,
716 temp, insn_end);
717 offset += insn_size;
718 if (itimes > 0 && itimes == instruction->times - 1) {
719 /*
720 * Dummy call to list->output to give the offset to the
721 * listing module.
722 */
723 list->output(offset, NULL, OUT_RAWDATA, 0);
724 list->uplevel(LIST_TIMES);
725 }
726 }
727 if (instruction->times > 1)
728 list->downlevel(LIST_TIMES);
729 return offset - start;
730 } else {
731 /* No match */
732 switch (m) {
733 case MERR_OPSIZEMISSING:
734 error(ERR_NONFATAL, "operation size not specified");
735 break;
736 case MERR_OPSIZEMISMATCH:
737 error(ERR_NONFATAL, "mismatch in operand sizes");
738 break;
739 case MERR_BRNUMMISMATCH:
740 error(ERR_NONFATAL,
741 "mismatch in the number of broadcasting elements");
742 break;
743 case MERR_BADCPU:
744 error(ERR_NONFATAL, "no instruction for this cpu level");
745 break;
746 case MERR_BADMODE:
747 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
748 bits);
749 break;
750 case MERR_ENCMISMATCH:
751 error(ERR_NONFATAL, "specific encoding scheme not available");
752 break;
753 case MERR_BADBND:
754 error(ERR_NONFATAL, "bnd prefix is not allowed");
755 break;
756 case MERR_BADREPNE:
757 error(ERR_NONFATAL, "%s prefix is not allowed",
758 (has_prefix(instruction, PPS_REP, P_REPNE) ?
759 "repne" : "repnz"));
760 break;
761 default:
762 error(ERR_NONFATAL,
763 "invalid combination of opcode and operands");
764 break;
765 }
766 }
767 return 0;
768 }
769
770 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
771 insn * instruction, efunc error)
772 {
773 const struct itemplate *temp;
774 enum match_result m;
775
776 errfunc = error; /* to pass to other functions */
777 cpu = cp;
778
779 if (instruction->opcode == I_none)
780 return 0;
781
782 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
783 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
784 instruction->opcode == I_DT || instruction->opcode == I_DO ||
785 instruction->opcode == I_DY) {
786 extop *e;
787 int32_t isize, osize, wsize;
788
789 isize = 0;
790 wsize = idata_bytes(instruction->opcode);
791
792 list_for_each(e, instruction->eops) {
793 int32_t align;
794
795 osize = 0;
796 if (e->type == EOT_DB_NUMBER) {
797 osize = 1;
798 warn_overflow_const(e->offset, wsize);
799 } else if (e->type == EOT_DB_STRING ||
800 e->type == EOT_DB_STRING_FREE)
801 osize = e->stringlen;
802
803 align = (-osize) % wsize;
804 if (align < 0)
805 align += wsize;
806 isize += osize + align;
807 }
808 return isize * instruction->times;
809 }
810
811 if (instruction->opcode == I_INCBIN) {
812 const char *fname = instruction->eops->stringval;
813 FILE *fp;
814 int64_t val = 0;
815 size_t len;
816
817 fp = fopen(fname, "rb");
818 if (!fp)
819 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
820 fname);
821 else if (fseek(fp, 0L, SEEK_END) < 0)
822 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
823 fname);
824 else {
825 len = ftell(fp);
826 if (instruction->eops->next) {
827 len -= instruction->eops->next->offset;
828 if (instruction->eops->next->next &&
829 len > (size_t)instruction->eops->next->next->offset) {
830 len = (size_t)instruction->eops->next->next->offset;
831 }
832 }
833 val = instruction->times * len;
834 }
835 if (fp)
836 fclose(fp);
837 return val;
838 }
839
840 /* Check to see if we need an address-size prefix */
841 add_asp(instruction, bits);
842
843 m = find_match(&temp, instruction, segment, offset, bits);
844 if (m == MOK_GOOD) {
845 /* we've matched an instruction. */
846 int64_t isize;
847 int j;
848
849 isize = calcsize(segment, offset, bits, instruction, temp);
850 if (isize < 0)
851 return -1;
852 for (j = 0; j < MAXPREFIX; j++) {
853 switch (instruction->prefixes[j]) {
854 case P_A16:
855 if (bits != 16)
856 isize++;
857 break;
858 case P_A32:
859 if (bits != 32)
860 isize++;
861 break;
862 case P_O16:
863 if (bits != 16)
864 isize++;
865 break;
866 case P_O32:
867 if (bits == 16)
868 isize++;
869 break;
870 case P_A64:
871 case P_O64:
872 case P_EVEX:
873 case P_VEX3:
874 case P_VEX2:
875 case P_NOBND:
876 case P_none:
877 break;
878 default:
879 isize++;
880 break;
881 }
882 }
883 return isize * instruction->times;
884 } else {
885 return -1; /* didn't match any instruction */
886 }
887 }
888
889 static void bad_hle_warn(const insn * ins, uint8_t hleok)
890 {
891 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
892 enum whatwarn { w_none, w_lock, w_inval } ww;
893 static const enum whatwarn warn[2][4] =
894 {
895 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
896 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
897 };
898 unsigned int n;
899
900 n = (unsigned int)rep_pfx - P_XACQUIRE;
901 if (n > 1)
902 return; /* Not XACQUIRE/XRELEASE */
903
904 ww = warn[n][hleok];
905 if (!is_class(MEMORY, ins->oprs[0].type))
906 ww = w_inval; /* HLE requires operand 0 to be memory */
907
908 switch (ww) {
909 case w_none:
910 break;
911
912 case w_lock:
913 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
914 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
915 "%s with this instruction requires lock",
916 prefix_name(rep_pfx));
917 }
918 break;
919
920 case w_inval:
921 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
922 "%s invalid with this instruction",
923 prefix_name(rep_pfx));
924 break;
925 }
926 }
927
928 /* Common construct */
929 #define case3(x) case (x): case (x)+1: case (x)+2
930 #define case4(x) case3(x): case (x)+3
931
932 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
933 insn * ins, const struct itemplate *temp)
934 {
935 const uint8_t *codes = temp->code;
936 int64_t length = 0;
937 uint8_t c;
938 int rex_mask = ~0;
939 int op1, op2;
940 struct operand *opx;
941 uint8_t opex = 0;
942 enum ea_type eat;
943 uint8_t hleok = 0;
944 bool lockcheck = true;
945 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
946
947 ins->rex = 0; /* Ensure REX is reset */
948 eat = EA_SCALAR; /* Expect a scalar EA */
949 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
950
951 if (ins->prefixes[PPS_OSIZE] == P_O64)
952 ins->rex |= REX_W;
953
954 (void)segment; /* Don't warn that this parameter is unused */
955 (void)offset; /* Don't warn that this parameter is unused */
956
957 while (*codes) {
958 c = *codes++;
959 op1 = (c & 3) + ((opex & 1) << 2);
960 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
961 opx = &ins->oprs[op1];
962 opex = 0; /* For the next iteration */
963
964 switch (c) {
965 case4(01):
966 codes += c, length += c;
967 break;
968
969 case3(05):
970 opex = c;
971 break;
972
973 case4(010):
974 ins->rex |=
975 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
976 codes++, length++;
977 break;
978
979 case4(014):
980 /* this is an index reg of MIB operand */
981 mib_index = opx->basereg;
982 break;
983
984 case4(020):
985 case4(024):
986 length++;
987 break;
988
989 case4(030):
990 length += 2;
991 break;
992
993 case4(034):
994 if (opx->type & (BITS16 | BITS32 | BITS64))
995 length += (opx->type & BITS16) ? 2 : 4;
996 else
997 length += (bits == 16) ? 2 : 4;
998 break;
999
1000 case4(040):
1001 length += 4;
1002 break;
1003
1004 case4(044):
1005 length += ins->addr_size >> 3;
1006 break;
1007
1008 case4(050):
1009 length++;
1010 break;
1011
1012 case4(054):
1013 length += 8; /* MOV reg64/imm */
1014 break;
1015
1016 case4(060):
1017 length += 2;
1018 break;
1019
1020 case4(064):
1021 if (opx->type & (BITS16 | BITS32 | BITS64))
1022 length += (opx->type & BITS16) ? 2 : 4;
1023 else
1024 length += (bits == 16) ? 2 : 4;
1025 break;
1026
1027 case4(070):
1028 length += 4;
1029 break;
1030
1031 case4(074):
1032 length += 2;
1033 break;
1034
1035 case 0172:
1036 case 0173:
1037 codes++;
1038 length++;
1039 break;
1040
1041 case4(0174):
1042 length++;
1043 break;
1044
1045 case4(0240):
1046 ins->rex |= REX_EV;
1047 ins->vexreg = regval(opx);
1048 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
1049 ins->vex_cm = *codes++;
1050 ins->vex_wlp = *codes++;
1051 ins->evex_tuple = (*codes++ - 0300);
1052 break;
1053
1054 case 0250:
1055 ins->rex |= REX_EV;
1056 ins->vexreg = 0;
1057 ins->vex_cm = *codes++;
1058 ins->vex_wlp = *codes++;
1059 ins->evex_tuple = (*codes++ - 0300);
1060 break;
1061
1062 case4(0254):
1063 length += 4;
1064 break;
1065
1066 case4(0260):
1067 ins->rex |= REX_V;
1068 ins->vexreg = regval(opx);
1069 ins->vex_cm = *codes++;
1070 ins->vex_wlp = *codes++;
1071 break;
1072
1073 case 0270:
1074 ins->rex |= REX_V;
1075 ins->vexreg = 0;
1076 ins->vex_cm = *codes++;
1077 ins->vex_wlp = *codes++;
1078 break;
1079
1080 case3(0271):
1081 hleok = c & 3;
1082 break;
1083
1084 case4(0274):
1085 length++;
1086 break;
1087
1088 case4(0300):
1089 break;
1090
1091 case 0310:
1092 if (bits == 64)
1093 return -1;
1094 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1095 break;
1096
1097 case 0311:
1098 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1099 break;
1100
1101 case 0312:
1102 break;
1103
1104 case 0313:
1105 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1106 has_prefix(ins, PPS_ASIZE, P_A32))
1107 return -1;
1108 break;
1109
1110 case4(0314):
1111 break;
1112
1113 case 0320:
1114 {
1115 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1116 if (pfx == P_O16)
1117 break;
1118 if (pfx != P_none)
1119 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1120 else
1121 ins->prefixes[PPS_OSIZE] = P_O16;
1122 break;
1123 }
1124
1125 case 0321:
1126 {
1127 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1128 if (pfx == P_O32)
1129 break;
1130 if (pfx != P_none)
1131 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1132 else
1133 ins->prefixes[PPS_OSIZE] = P_O32;
1134 break;
1135 }
1136
1137 case 0322:
1138 break;
1139
1140 case 0323:
1141 rex_mask &= ~REX_W;
1142 break;
1143
1144 case 0324:
1145 ins->rex |= REX_W;
1146 break;
1147
1148 case 0325:
1149 ins->rex |= REX_NH;
1150 break;
1151
1152 case 0326:
1153 break;
1154
1155 case 0330:
1156 codes++, length++;
1157 break;
1158
1159 case 0331:
1160 break;
1161
1162 case 0332:
1163 case 0333:
1164 length++;
1165 break;
1166
1167 case 0334:
1168 ins->rex |= REX_L;
1169 break;
1170
1171 case 0335:
1172 break;
1173
1174 case 0336:
1175 if (!ins->prefixes[PPS_REP])
1176 ins->prefixes[PPS_REP] = P_REP;
1177 break;
1178
1179 case 0337:
1180 if (!ins->prefixes[PPS_REP])
1181 ins->prefixes[PPS_REP] = P_REPNE;
1182 break;
1183
1184 case 0340:
1185 if (ins->oprs[0].segment != NO_SEG)
1186 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1187 " quantity of BSS space");
1188 else
1189 length += ins->oprs[0].offset;
1190 break;
1191
1192 case 0341:
1193 if (!ins->prefixes[PPS_WAIT])
1194 ins->prefixes[PPS_WAIT] = P_WAIT;
1195 break;
1196
1197 case 0360:
1198 break;
1199
1200 case 0361:
1201 length++;
1202 break;
1203
1204 case 0364:
1205 case 0365:
1206 break;
1207
1208 case 0366:
1209 case 0367:
1210 length++;
1211 break;
1212
1213 case 0370:
1214 case 0371:
1215 break;
1216
1217 case 0373:
1218 length++;
1219 break;
1220
1221 case 0374:
1222 eat = EA_XMMVSIB;
1223 break;
1224
1225 case 0375:
1226 eat = EA_YMMVSIB;
1227 break;
1228
1229 case 0376:
1230 eat = EA_ZMMVSIB;
1231 break;
1232
1233 case4(0100):
1234 case4(0110):
1235 case4(0120):
1236 case4(0130):
1237 case4(0200):
1238 case4(0204):
1239 case4(0210):
1240 case4(0214):
1241 case4(0220):
1242 case4(0224):
1243 case4(0230):
1244 case4(0234):
1245 {
1246 ea ea_data;
1247 int rfield;
1248 opflags_t rflags;
1249 struct operand *opy = &ins->oprs[op2];
1250 struct operand *op_er_sae;
1251
1252 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1253
1254 if (c <= 0177) {
1255 /* pick rfield from operand b (opx) */
1256 rflags = regflag(opx);
1257 rfield = nasm_regvals[opx->basereg];
1258 } else {
1259 rflags = 0;
1260 rfield = c & 7;
1261 }
1262
1263 /* EVEX.b1 : evex_brerop contains the operand position */
1264 op_er_sae = (ins->evex_brerop >= 0 ?
1265 &ins->oprs[ins->evex_brerop] : NULL);
1266
1267 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1268 /* set EVEX.b */
1269 ins->evex_p[2] |= EVEX_P2B;
1270 if (op_er_sae->decoflags & ER) {
1271 /* set EVEX.RC (rounding control) */
1272 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1273 & EVEX_P2RC;
1274 }
1275 } else {
1276 /* set EVEX.L'L (vector length) */
1277 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1278 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1279 if (opy->decoflags & BRDCAST_MASK) {
1280 /* set EVEX.b */
1281 ins->evex_p[2] |= EVEX_P2B;
1282 }
1283 }
1284
1285 if (itemp_has(temp, IF_MIB)) {
1286 opy->eaflags |= EAF_MIB;
1287 /*
1288 * if a separate form of MIB (ICC style) is used,
1289 * the index reg info is merged into mem operand
1290 */
1291 if (mib_index != R_none) {
1292 opy->indexreg = mib_index;
1293 opy->scale = 1;
1294 opy->hintbase = mib_index;
1295 opy->hinttype = EAH_NOTBASE;
1296 }
1297 }
1298
1299 if (process_ea(opy, &ea_data, bits,
1300 rfield, rflags, ins) != eat) {
1301 errfunc(ERR_NONFATAL, "invalid effective address");
1302 return -1;
1303 } else {
1304 ins->rex |= ea_data.rex;
1305 length += ea_data.size;
1306 }
1307 }
1308 break;
1309
1310 default:
1311 errfunc(ERR_PANIC, "internal instruction table corrupt"
1312 ": instruction code \\%o (0x%02X) given", c, c);
1313 break;
1314 }
1315 }
1316
1317 ins->rex &= rex_mask;
1318
1319 if (ins->rex & REX_NH) {
1320 if (ins->rex & REX_H) {
1321 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1322 return -1;
1323 }
1324 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1325 }
1326
1327 switch (ins->prefixes[PPS_VEX]) {
1328 case P_EVEX:
1329 if (!(ins->rex & REX_EV))
1330 return -1;
1331 break;
1332 case P_VEX3:
1333 case P_VEX2:
1334 if (!(ins->rex & REX_V))
1335 return -1;
1336 break;
1337 default:
1338 break;
1339 }
1340
1341 if (ins->rex & (REX_V | REX_EV)) {
1342 int bad32 = REX_R|REX_W|REX_X|REX_B;
1343
1344 if (ins->rex & REX_H) {
1345 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1346 return -1;
1347 }
1348 switch (ins->vex_wlp & 060) {
1349 case 000:
1350 case 040:
1351 ins->rex &= ~REX_W;
1352 break;
1353 case 020:
1354 ins->rex |= REX_W;
1355 bad32 &= ~REX_W;
1356 break;
1357 case 060:
1358 /* Follow REX_W */
1359 break;
1360 }
1361
1362 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1363 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1364 return -1;
1365 } else if (!(ins->rex & REX_EV) &&
1366 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1367 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1368 return -1;
1369 }
1370 if (ins->rex & REX_EV)
1371 length += 4;
1372 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1373 ins->prefixes[PPS_VEX] == P_VEX3)
1374 length += 3;
1375 else
1376 length += 2;
1377 } else if (ins->rex & REX_MASK) {
1378 if (ins->rex & REX_H) {
1379 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1380 return -1;
1381 } else if (bits == 64) {
1382 length++;
1383 } else if ((ins->rex & REX_L) &&
1384 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1385 iflag_ffs(&cpu) >= IF_X86_64) {
1386 /* LOCK-as-REX.R */
1387 assert_no_prefix(ins, PPS_LOCK);
1388 lockcheck = false; /* Already errored, no need for warning */
1389 length++;
1390 } else {
1391 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1392 return -1;
1393 }
1394 }
1395
1396 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1397 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1398 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1399 "instruction is not lockable");
1400 }
1401
1402 bad_hle_warn(ins, hleok);
1403
1404 /*
1405 * when BND prefix is set by DEFAULT directive,
1406 * BND prefix is added to every appropriate instruction line
1407 * unless it is overridden by NOBND prefix.
1408 */
1409 if (globalbnd &&
1410 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1411 ins->prefixes[PPS_REP] = P_BND;
1412
1413 return length;
1414 }
1415
1416 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1417 {
1418 if (bits == 64) {
1419 if ((ins->rex & REX_MASK) &&
1420 !(ins->rex & (REX_V | REX_EV)) &&
1421 !ins->rex_done) {
1422 int rex = (ins->rex & REX_MASK) | REX_P;
1423 out(offset, segment, &rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1424 ins->rex_done = true;
1425 return 1;
1426 }
1427 }
1428
1429 return 0;
1430 }
1431
1432 static void gencode(int32_t segment, int64_t offset, int bits,
1433 insn * ins, const struct itemplate *temp,
1434 int64_t insn_end)
1435 {
1436 uint8_t c;
1437 uint8_t bytes[4];
1438 int64_t size;
1439 int64_t data;
1440 int op1, op2;
1441 struct operand *opx;
1442 const uint8_t *codes = temp->code;
1443 uint8_t opex = 0;
1444 enum ea_type eat = EA_SCALAR;
1445
1446 ins->rex_done = false;
1447
1448 while (*codes) {
1449 c = *codes++;
1450 op1 = (c & 3) + ((opex & 1) << 2);
1451 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1452 opx = &ins->oprs[op1];
1453 opex = 0; /* For the next iteration */
1454
1455 switch (c) {
1456 case 01:
1457 case 02:
1458 case 03:
1459 case 04:
1460 offset += emit_rex(ins, segment, offset, bits);
1461 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1462 codes += c;
1463 offset += c;
1464 break;
1465
1466 case 05:
1467 case 06:
1468 case 07:
1469 opex = c;
1470 break;
1471
1472 case4(010):
1473 offset += emit_rex(ins, segment, offset, bits);
1474 bytes[0] = *codes++ + (regval(opx) & 7);
1475 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1476 offset += 1;
1477 break;
1478
1479 case4(014):
1480 break;
1481
1482 case4(020):
1483 if (opx->offset < -256 || opx->offset > 255) {
1484 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1485 "byte value exceeds bounds");
1486 }
1487 out_imm8(offset, segment, opx, -1);
1488 offset += 1;
1489 break;
1490
1491 case4(024):
1492 if (opx->offset < 0 || opx->offset > 255)
1493 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1494 "unsigned byte value exceeds bounds");
1495 out_imm8(offset, segment, opx, 1);
1496 offset += 1;
1497 break;
1498
1499 case4(030):
1500 warn_overflow_opd(opx, 2);
1501 data = opx->offset;
1502 out(offset, segment, &data, OUT_ADDRESS, 2,
1503 opx->segment, opx->wrt);
1504 offset += 2;
1505 break;
1506
1507 case4(034):
1508 if (opx->type & (BITS16 | BITS32))
1509 size = (opx->type & BITS16) ? 2 : 4;
1510 else
1511 size = (bits == 16) ? 2 : 4;
1512 warn_overflow_opd(opx, size);
1513 data = opx->offset;
1514 out(offset, segment, &data, OUT_ADDRESS, size,
1515 opx->segment, opx->wrt);
1516 offset += size;
1517 break;
1518
1519 case4(040):
1520 warn_overflow_opd(opx, 4);
1521 data = opx->offset;
1522 out(offset, segment, &data, OUT_ADDRESS, 4,
1523 opx->segment, opx->wrt);
1524 offset += 4;
1525 break;
1526
1527 case4(044):
1528 data = opx->offset;
1529 size = ins->addr_size >> 3;
1530 warn_overflow_opd(opx, size);
1531 out(offset, segment, &data, OUT_ADDRESS, size,
1532 opx->segment, opx->wrt);
1533 offset += size;
1534 break;
1535
1536 case4(050):
1537 if (opx->segment != segment) {
1538 data = opx->offset;
1539 out(offset, segment, &data,
1540 OUT_REL1ADR, insn_end - offset,
1541 opx->segment, opx->wrt);
1542 } else {
1543 data = opx->offset - insn_end;
1544 if (data > 127 || data < -128)
1545 errfunc(ERR_NONFATAL, "short jump is out of range");
1546 out(offset, segment, &data,
1547 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1548 }
1549 offset += 1;
1550 break;
1551
1552 case4(054):
1553 data = (int64_t)opx->offset;
1554 out(offset, segment, &data, OUT_ADDRESS, 8,
1555 opx->segment, opx->wrt);
1556 offset += 8;
1557 break;
1558
1559 case4(060):
1560 if (opx->segment != segment) {
1561 data = opx->offset;
1562 out(offset, segment, &data,
1563 OUT_REL2ADR, insn_end - offset,
1564 opx->segment, opx->wrt);
1565 } else {
1566 data = opx->offset - insn_end;
1567 out(offset, segment, &data,
1568 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1569 }
1570 offset += 2;
1571 break;
1572
1573 case4(064):
1574 if (opx->type & (BITS16 | BITS32 | BITS64))
1575 size = (opx->type & BITS16) ? 2 : 4;
1576 else
1577 size = (bits == 16) ? 2 : 4;
1578 if (opx->segment != segment) {
1579 data = opx->offset;
1580 out(offset, segment, &data,
1581 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1582 insn_end - offset, opx->segment, opx->wrt);
1583 } else {
1584 data = opx->offset - insn_end;
1585 out(offset, segment, &data,
1586 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1587 }
1588 offset += size;
1589 break;
1590
1591 case4(070):
1592 if (opx->segment != segment) {
1593 data = opx->offset;
1594 out(offset, segment, &data,
1595 OUT_REL4ADR, insn_end - offset,
1596 opx->segment, opx->wrt);
1597 } else {
1598 data = opx->offset - insn_end;
1599 out(offset, segment, &data,
1600 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1601 }
1602 offset += 4;
1603 break;
1604
1605 case4(074):
1606 if (opx->segment == NO_SEG)
1607 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1608 " relocatable");
1609 data = 0;
1610 out(offset, segment, &data, OUT_ADDRESS, 2,
1611 outfmt->segbase(1 + opx->segment),
1612 opx->wrt);
1613 offset += 2;
1614 break;
1615
1616 case 0172:
1617 c = *codes++;
1618 opx = &ins->oprs[c >> 3];
1619 bytes[0] = nasm_regvals[opx->basereg] << 4;
1620 opx = &ins->oprs[c & 7];
1621 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1622 errfunc(ERR_NONFATAL,
1623 "non-absolute expression not permitted as argument %d",
1624 c & 7);
1625 } else {
1626 if (opx->offset & ~15) {
1627 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1628 "four-bit argument exceeds bounds");
1629 }
1630 bytes[0] |= opx->offset & 15;
1631 }
1632 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1633 offset++;
1634 break;
1635
1636 case 0173:
1637 c = *codes++;
1638 opx = &ins->oprs[c >> 4];
1639 bytes[0] = nasm_regvals[opx->basereg] << 4;
1640 bytes[0] |= c & 15;
1641 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1642 offset++;
1643 break;
1644
1645 case4(0174):
1646 bytes[0] = nasm_regvals[opx->basereg] << 4;
1647 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1648 offset++;
1649 break;
1650
1651 case4(0254):
1652 data = opx->offset;
1653 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1654 (int32_t)data != (int64_t)data) {
1655 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1656 "signed dword immediate exceeds bounds");
1657 }
1658 out(offset, segment, &data, OUT_ADDRESS, -4,
1659 opx->segment, opx->wrt);
1660 offset += 4;
1661 break;
1662
1663 case4(0240):
1664 case 0250:
1665 codes += 3;
1666 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1667 EVEX_P2Z | EVEX_P2AAA, 2);
1668 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1669 bytes[0] = 0x62;
1670 /* EVEX.X can be set by either REX or EVEX for different reasons */
1671 bytes[1] = ((((ins->rex & 7) << 5) |
1672 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1673 (ins->vex_cm & 3);
1674 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1675 ((~ins->vexreg & 15) << 3) |
1676 (1 << 2) | (ins->vex_wlp & 3);
1677 bytes[3] = ins->evex_p[2];
1678 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1679 offset += 4;
1680 break;
1681
1682 case4(0260):
1683 case 0270:
1684 codes += 2;
1685 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1686 ins->prefixes[PPS_VEX] == P_VEX3) {
1687 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1688 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1689 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1690 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1691 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1692 offset += 3;
1693 } else {
1694 bytes[0] = 0xc5;
1695 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1696 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1697 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1698 offset += 2;
1699 }
1700 break;
1701
1702 case 0271:
1703 case 0272:
1704 case 0273:
1705 break;
1706
1707 case4(0274):
1708 {
1709 uint64_t uv, um;
1710 int s;
1711
1712 if (ins->rex & REX_W)
1713 s = 64;
1714 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1715 s = 16;
1716 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1717 s = 32;
1718 else
1719 s = bits;
1720
1721 um = (uint64_t)2 << (s-1);
1722 uv = opx->offset;
1723
1724 if (uv > 127 && uv < (uint64_t)-128 &&
1725 (uv < um-128 || uv > um-1)) {
1726 /* If this wasn't explicitly byte-sized, warn as though we
1727 * had fallen through to the imm16/32/64 case.
1728 */
1729 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1730 "%s value exceeds bounds",
1731 (opx->type & BITS8) ? "signed byte" :
1732 s == 16 ? "word" :
1733 s == 32 ? "dword" :
1734 "signed dword");
1735 }
1736 if (opx->segment != NO_SEG) {
1737 data = uv;
1738 out(offset, segment, &data, OUT_ADDRESS, 1,
1739 opx->segment, opx->wrt);
1740 } else {
1741 bytes[0] = uv;
1742 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1743 NO_SEG);
1744 }
1745 offset += 1;
1746 break;
1747 }
1748
1749 case4(0300):
1750 break;
1751
1752 case 0310:
1753 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1754 *bytes = 0x67;
1755 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1756 offset += 1;
1757 } else
1758 offset += 0;
1759 break;
1760
1761 case 0311:
1762 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1763 *bytes = 0x67;
1764 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1765 offset += 1;
1766 } else
1767 offset += 0;
1768 break;
1769
1770 case 0312:
1771 break;
1772
1773 case 0313:
1774 ins->rex = 0;
1775 break;
1776
1777 case4(0314):
1778 break;
1779
1780 case 0320:
1781 case 0321:
1782 break;
1783
1784 case 0322:
1785 case 0323:
1786 break;
1787
1788 case 0324:
1789 ins->rex |= REX_W;
1790 break;
1791
1792 case 0325:
1793 break;
1794
1795 case 0326:
1796 break;
1797
1798 case 0330:
1799 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1800 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1801 offset += 1;
1802 break;
1803
1804 case 0331:
1805 break;
1806
1807 case 0332:
1808 case 0333:
1809 *bytes = c - 0332 + 0xF2;
1810 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1811 offset += 1;
1812 break;
1813
1814 case 0334:
1815 if (ins->rex & REX_R) {
1816 *bytes = 0xF0;
1817 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1818 offset += 1;
1819 }
1820 ins->rex &= ~(REX_L|REX_R);
1821 break;
1822
1823 case 0335:
1824 break;
1825
1826 case 0336:
1827 case 0337:
1828 break;
1829
1830 case 0340:
1831 if (ins->oprs[0].segment != NO_SEG)
1832 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1833 else {
1834 int64_t size = ins->oprs[0].offset;
1835 if (size > 0)
1836 out(offset, segment, NULL,
1837 OUT_RESERVE, size, NO_SEG, NO_SEG);
1838 offset += size;
1839 }
1840 break;
1841
1842 case 0341:
1843 break;
1844
1845 case 0360:
1846 break;
1847
1848 case 0361:
1849 bytes[0] = 0x66;
1850 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1851 offset += 1;
1852 break;
1853
1854 case 0364:
1855 case 0365:
1856 break;
1857
1858 case 0366:
1859 case 0367:
1860 *bytes = c - 0366 + 0x66;
1861 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1862 offset += 1;
1863 break;
1864
1865 case3(0370):
1866 break;
1867
1868 case 0373:
1869 *bytes = bits == 16 ? 3 : 5;
1870 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1871 offset += 1;
1872 break;
1873
1874 case 0374:
1875 eat = EA_XMMVSIB;
1876 break;
1877
1878 case 0375:
1879 eat = EA_YMMVSIB;
1880 break;
1881
1882 case 0376:
1883 eat = EA_ZMMVSIB;
1884 break;
1885
1886 case4(0100):
1887 case4(0110):
1888 case4(0120):
1889 case4(0130):
1890 case4(0200):
1891 case4(0204):
1892 case4(0210):
1893 case4(0214):
1894 case4(0220):
1895 case4(0224):
1896 case4(0230):
1897 case4(0234):
1898 {
1899 ea ea_data;
1900 int rfield;
1901 opflags_t rflags;
1902 uint8_t *p;
1903 int32_t s;
1904 struct operand *opy = &ins->oprs[op2];
1905
1906 if (c <= 0177) {
1907 /* pick rfield from operand b (opx) */
1908 rflags = regflag(opx);
1909 rfield = nasm_regvals[opx->basereg];
1910 } else {
1911 /* rfield is constant */
1912 rflags = 0;
1913 rfield = c & 7;
1914 }
1915
1916 if (process_ea(opy, &ea_data, bits,
1917 rfield, rflags, ins) != eat)
1918 errfunc(ERR_NONFATAL, "invalid effective address");
1919
1920 p = bytes;
1921 *p++ = ea_data.modrm;
1922 if (ea_data.sib_present)
1923 *p++ = ea_data.sib;
1924
1925 s = p - bytes;
1926 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1927
1928 /*
1929 * Make sure the address gets the right offset in case
1930 * the line breaks in the .lst file (BR 1197827)
1931 */
1932 offset += s;
1933 s = 0;
1934
1935 if (ea_data.bytes) {
1936 /* use compressed displacement, if available */
1937 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1938 s += ea_data.bytes;
1939 if (ea_data.rip) {
1940 if (opy->segment == segment) {
1941 data -= insn_end;
1942 if (overflow_signed(data, ea_data.bytes))
1943 warn_overflow(ERR_PASS2, ea_data.bytes);
1944 out(offset, segment, &data, OUT_ADDRESS,
1945 ea_data.bytes, NO_SEG, NO_SEG);
1946 } else {
1947 /* overflow check in output/linker? */
1948 out(offset, segment, &data, OUT_REL4ADR,
1949 insn_end - offset, opy->segment, opy->wrt);
1950 }
1951 } else {
1952 int asize = ins->addr_size >> 3;
1953 int atype = ea_data.bytes;
1954
1955 if (overflow_general(data, asize) ||
1956 signed_bits(data, ins->addr_size) !=
1957 signed_bits(data, ea_data.bytes << 3))
1958 warn_overflow(ERR_PASS2, ea_data.bytes);
1959
1960 if (asize > ea_data.bytes) {
1961 /*
1962 * If the address isn't the full width of
1963 * the address size, treat is as signed...
1964 */
1965 atype = -atype;
1966 }
1967
1968 out(offset, segment, &data, OUT_ADDRESS,
1969 atype, opy->segment, opy->wrt);
1970 }
1971 }
1972 offset += s;
1973 }
1974 break;
1975
1976 default:
1977 errfunc(ERR_PANIC, "internal instruction table corrupt"
1978 ": instruction code \\%o (0x%02X) given", c, c);
1979 break;
1980 }
1981 }
1982 }
1983
1984 static opflags_t regflag(const operand * o)
1985 {
1986 if (!is_register(o->basereg))
1987 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1988 return nasm_reg_flags[o->basereg];
1989 }
1990
1991 static int32_t regval(const operand * o)
1992 {
1993 if (!is_register(o->basereg))
1994 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1995 return nasm_regvals[o->basereg];
1996 }
1997
1998 static int op_rexflags(const operand * o, int mask)
1999 {
2000 opflags_t flags;
2001 int val;
2002
2003 if (!is_register(o->basereg))
2004 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
2005
2006 flags = nasm_reg_flags[o->basereg];
2007 val = nasm_regvals[o->basereg];
2008
2009 return rexflags(val, flags, mask);
2010 }
2011
2012 static int rexflags(int val, opflags_t flags, int mask)
2013 {
2014 int rex = 0;
2015
2016 if (val >= 0 && (val & 8))
2017 rex |= REX_B|REX_X|REX_R;
2018 if (flags & BITS64)
2019 rex |= REX_W;
2020 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
2021 rex |= REX_H;
2022 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
2023 rex |= REX_P;
2024
2025 return rex & mask;
2026 }
2027
2028 static int evexflags(int val, decoflags_t deco,
2029 int mask, uint8_t byte)
2030 {
2031 int evex = 0;
2032
2033 switch (byte) {
2034 case 0:
2035 if (val >= 0 && (val & 16))
2036 evex |= (EVEX_P0RP | EVEX_P0X);
2037 break;
2038 case 2:
2039 if (val >= 0 && (val & 16))
2040 evex |= EVEX_P2VP;
2041 if (deco & Z)
2042 evex |= EVEX_P2Z;
2043 if (deco & OPMASK_MASK)
2044 evex |= deco & EVEX_P2AAA;
2045 break;
2046 }
2047 return evex & mask;
2048 }
2049
2050 static int op_evexflags(const operand * o, int mask, uint8_t byte)
2051 {
2052 int val;
2053
2054 val = nasm_regvals[o->basereg];
2055
2056 return evexflags(val, o->decoflags, mask, byte);
2057 }
2058
2059 static enum match_result find_match(const struct itemplate **tempp,
2060 insn *instruction,
2061 int32_t segment, int64_t offset, int bits)
2062 {
2063 const struct itemplate *temp;
2064 enum match_result m, merr;
2065 opflags_t xsizeflags[MAX_OPERANDS];
2066 bool opsizemissing = false;
2067 int8_t broadcast = instruction->evex_brerop;
2068 int i;
2069
2070 /* broadcasting uses a different data element size */
2071 for (i = 0; i < instruction->operands; i++)
2072 if (i == broadcast)
2073 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2074 else
2075 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2076
2077 merr = MERR_INVALOP;
2078
2079 for (temp = nasm_instructions[instruction->opcode];
2080 temp->opcode != I_none; temp++) {
2081 m = matches(temp, instruction, bits);
2082 if (m == MOK_JUMP) {
2083 if (jmp_match(segment, offset, bits, instruction, temp))
2084 m = MOK_GOOD;
2085 else
2086 m = MERR_INVALOP;
2087 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2088 /*
2089 * Missing operand size and a candidate for fuzzy matching...
2090 */
2091 for (i = 0; i < temp->operands; i++)
2092 if (i == broadcast)
2093 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2094 else
2095 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2096 opsizemissing = true;
2097 }
2098 if (m > merr)
2099 merr = m;
2100 if (merr == MOK_GOOD)
2101 goto done;
2102 }
2103
2104 /* No match, but see if we can get a fuzzy operand size match... */
2105 if (!opsizemissing)
2106 goto done;
2107
2108 for (i = 0; i < instruction->operands; i++) {
2109 /*
2110 * We ignore extrinsic operand sizes on registers, so we should
2111 * never try to fuzzy-match on them. This also resolves the case
2112 * when we have e.g. "xmmrm128" in two different positions.
2113 */
2114 if (is_class(REGISTER, instruction->oprs[i].type))
2115 continue;
2116
2117 /* This tests if xsizeflags[i] has more than one bit set */
2118 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2119 goto done; /* No luck */
2120
2121 if (i == broadcast) {
2122 instruction->oprs[i].decoflags |= xsizeflags[i];
2123 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2124 BITS32 : BITS64);
2125 } else {
2126 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2127 }
2128 }
2129
2130 /* Try matching again... */
2131 for (temp = nasm_instructions[instruction->opcode];
2132 temp->opcode != I_none; temp++) {
2133 m = matches(temp, instruction, bits);
2134 if (m == MOK_JUMP) {
2135 if (jmp_match(segment, offset, bits, instruction, temp))
2136 m = MOK_GOOD;
2137 else
2138 m = MERR_INVALOP;
2139 }
2140 if (m > merr)
2141 merr = m;
2142 if (merr == MOK_GOOD)
2143 goto done;
2144 }
2145
2146 done:
2147 *tempp = temp;
2148 return merr;
2149 }
2150
2151 static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
2152 {
2153 opflags_t opsize = opflags & SIZE_MASK;
2154 uint8_t brcast_num;
2155
2156 /*
2157 * Due to discontinuity between BITS64 and BITS128 (BITS80),
2158 * this cannot be a simple arithmetic calculation.
2159 */
2160 if (brsize > BITS64)
2161 errfunc(ERR_FATAL,
2162 "size of broadcasting element is greater than 64 bits");
2163
2164 switch (opsize) {
2165 case BITS64:
2166 brcast_num = BITS64 / brsize;
2167 break;
2168 default:
2169 brcast_num = (opsize / BITS128) * (BITS64 / brsize) * 2;
2170 break;
2171 }
2172
2173 return brcast_num;
2174 }
2175
2176 static enum match_result matches(const struct itemplate *itemp,
2177 insn *instruction, int bits)
2178 {
2179 opflags_t size[MAX_OPERANDS], asize;
2180 bool opsizemissing = false;
2181 int i, oprs;
2182
2183 /*
2184 * Check the opcode
2185 */
2186 if (itemp->opcode != instruction->opcode)
2187 return MERR_INVALOP;
2188
2189 /*
2190 * Count the operands
2191 */
2192 if (itemp->operands != instruction->operands)
2193 return MERR_INVALOP;
2194
2195 /*
2196 * Is it legal?
2197 */
2198 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2199 return MERR_INVALOP;
2200
2201 /*
2202 * {evex} available?
2203 */
2204 switch (instruction->prefixes[PPS_VEX]) {
2205 case P_EVEX:
2206 if (!itemp_has(itemp, IF_EVEX))
2207 return MERR_ENCMISMATCH;
2208 break;
2209 case P_VEX3:
2210 case P_VEX2:
2211 if (!itemp_has(itemp, IF_VEX))
2212 return MERR_ENCMISMATCH;
2213 break;
2214 default:
2215 break;
2216 }
2217
2218 /*
2219 * Check that no spurious colons or TOs are present
2220 */
2221 for (i = 0; i < itemp->operands; i++)
2222 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2223 return MERR_INVALOP;
2224
2225 /*
2226 * Process size flags
2227 */
2228 switch (itemp_smask(itemp)) {
2229 case IF_GENBIT(IF_SB):
2230 asize = BITS8;
2231 break;
2232 case IF_GENBIT(IF_SW):
2233 asize = BITS16;
2234 break;
2235 case IF_GENBIT(IF_SD):
2236 asize = BITS32;
2237 break;
2238 case IF_GENBIT(IF_SQ):
2239 asize = BITS64;
2240 break;
2241 case IF_GENBIT(IF_SO):
2242 asize = BITS128;
2243 break;
2244 case IF_GENBIT(IF_SY):
2245 asize = BITS256;
2246 break;
2247 case IF_GENBIT(IF_SZ):
2248 asize = BITS512;
2249 break;
2250 case IF_GENBIT(IF_SIZE):
2251 switch (bits) {
2252 case 16:
2253 asize = BITS16;
2254 break;
2255 case 32:
2256 asize = BITS32;
2257 break;
2258 case 64:
2259 asize = BITS64;
2260 break;
2261 default:
2262 asize = 0;
2263 break;
2264 }
2265 break;
2266 default:
2267 asize = 0;
2268 break;
2269 }
2270
2271 if (itemp_armask(itemp)) {
2272 /* S- flags only apply to a specific operand */
2273 i = itemp_arg(itemp);
2274 memset(size, 0, sizeof size);
2275 size[i] = asize;
2276 } else {
2277 /* S- flags apply to all operands */
2278 for (i = 0; i < MAX_OPERANDS; i++)
2279 size[i] = asize;
2280 }
2281
2282 /*
2283 * Check that the operand flags all match up,
2284 * it's a bit tricky so lets be verbose:
2285 *
2286 * 1) Find out the size of operand. If instruction
2287 * doesn't have one specified -- we're trying to
2288 * guess it either from template (IF_S* flag) or
2289 * from code bits.
2290 *
2291 * 2) If template operand do not match the instruction OR
2292 * template has an operand size specified AND this size differ
2293 * from which instruction has (perhaps we got it from code bits)
2294 * we are:
2295 * a) Check that only size of instruction and operand is differ
2296 * other characteristics do match
2297 * b) Perhaps it's a register specified in instruction so
2298 * for such a case we just mark that operand as "size
2299 * missing" and this will turn on fuzzy operand size
2300 * logic facility (handled by a caller)
2301 */
2302 for (i = 0; i < itemp->operands; i++) {
2303 opflags_t type = instruction->oprs[i].type;
2304 decoflags_t deco = instruction->oprs[i].decoflags;
2305 bool is_broadcast = deco & BRDCAST_MASK;
2306 uint8_t brcast_num = 0;
2307 opflags_t template_opsize, insn_opsize;
2308
2309 if (!(type & SIZE_MASK))
2310 type |= size[i];
2311
2312 insn_opsize = type & SIZE_MASK;
2313 if (!is_broadcast) {
2314 template_opsize = itemp->opd[i] & SIZE_MASK;
2315 } else {
2316 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2317 /*
2318 * when broadcasting, the element size depends on
2319 * the instruction type. decorator flag should match.
2320 */
2321
2322 if (deco_brsize) {
2323 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2324 /* calculate the proper number : {1to<brcast_num>} */
2325 brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
2326 } else {
2327 template_opsize = 0;
2328 }
2329 }
2330
2331 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2332 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2333 return MERR_INVALOP;
2334 } else if (template_opsize) {
2335 if (template_opsize != insn_opsize) {
2336 if (insn_opsize) {
2337 return MERR_INVALOP;
2338 } else if (!is_class(REGISTER, type)) {
2339 /*
2340 * Note: we don't honor extrinsic operand sizes for registers,
2341 * so "missing operand size" for a register should be
2342 * considered a wildcard match rather than an error.
2343 */
2344 opsizemissing = true;
2345 }
2346 } else if (is_broadcast &&
2347 (brcast_num !=
2348 (2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2349 /*
2350 * broadcasting opsize matches but the number of repeated memory
2351 * element does not match.
2352 * if 64b double precision float is broadcasted to ymm (256b),
2353 * broadcasting decorator must be {1to4}.
2354 */
2355 return MERR_BRNUMMISMATCH;
2356 }
2357 }
2358 }
2359
2360 if (opsizemissing)
2361 return MERR_OPSIZEMISSING;
2362
2363 /*
2364 * Check operand sizes
2365 */
2366 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2367 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2368 for (i = 0; i < oprs; i++) {
2369 asize = itemp->opd[i] & SIZE_MASK;
2370 if (asize) {
2371 for (i = 0; i < oprs; i++)
2372 size[i] = asize;
2373 break;
2374 }
2375 }
2376 } else {
2377 oprs = itemp->operands;
2378 }
2379
2380 for (i = 0; i < itemp->operands; i++) {
2381 if (!(itemp->opd[i] & SIZE_MASK) &&
2382 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2383 return MERR_OPSIZEMISMATCH;
2384 }
2385
2386 /*
2387 * Check template is okay at the set cpu level
2388 */
2389 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2390 return MERR_BADCPU;
2391
2392 /*
2393 * Verify the appropriate long mode flag.
2394 */
2395 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2396 return MERR_BADMODE;
2397
2398 /*
2399 * If we have a HLE prefix, look for the NOHLE flag
2400 */
2401 if (itemp_has(itemp, IF_NOHLE) &&
2402 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2403 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2404 return MERR_BADHLE;
2405
2406 /*
2407 * Check if special handling needed for Jumps
2408 */
2409 if ((itemp->code[0] & ~1) == 0370)
2410 return MOK_JUMP;
2411
2412 /*
2413 * Check if BND prefix is allowed.
2414 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2415 */
2416 if (!itemp_has(itemp, IF_BND) &&
2417 (has_prefix(instruction, PPS_REP, P_BND) ||
2418 has_prefix(instruction, PPS_REP, P_NOBND)))
2419 return MERR_BADBND;
2420 else if (itemp_has(itemp, IF_BND) &&
2421 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2422 has_prefix(instruction, PPS_REP, P_REPNZ)))
2423 return MERR_BADREPNE;
2424
2425 return MOK_GOOD;
2426 }
2427
2428 /*
2429 * Check if ModR/M.mod should/can be 01.
2430 * - EAF_BYTEOFFS is set
2431 * - offset can fit in a byte when EVEX is not used
2432 * - offset can be compressed when EVEX is used
2433 */
2434 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2435 (o >= -128 && o <= 127 && \
2436 seg == NO_SEG && !forw_ref && \
2437 !(input->eaflags & EAF_WORDOFFS) && \
2438 !(ins->rex & REX_EV)) || \
2439 (ins->rex & REX_EV && \
2440 is_disp8n(input, ins, &output->disp8)))
2441
2442 static enum ea_type process_ea(operand *input, ea *output, int bits,
2443 int rfield, opflags_t rflags, insn *ins)
2444 {
2445 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2446 int addrbits = ins->addr_size;
2447 int eaflags = input->eaflags;
2448
2449 output->type = EA_SCALAR;
2450 output->rip = false;
2451 output->disp8 = 0;
2452
2453 /* REX flags for the rfield operand */
2454 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2455 /* EVEX.R' flag for the REG operand */
2456 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2457
2458 if (is_class(REGISTER, input->type)) {
2459 /*
2460 * It's a direct register.
2461 */
2462 if (!is_register(input->basereg))
2463 goto err;
2464
2465 if (!is_reg_class(REG_EA, input->basereg))
2466 goto err;
2467
2468 /* broadcasting is not available with a direct register operand. */
2469 if (input->decoflags & BRDCAST_MASK) {
2470 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2471 goto err;
2472 }
2473
2474 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2475 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2476 output->sib_present = false; /* no SIB necessary */
2477 output->bytes = 0; /* no offset necessary either */
2478 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2479 } else {
2480 /*
2481 * It's a memory reference.
2482 */
2483
2484 /* Embedded rounding or SAE is not available with a mem ref operand. */
2485 if (input->decoflags & (ER | SAE)) {
2486 nasm_error(ERR_NONFATAL,
2487 "Embedded rounding is available only with reg-reg op.");
2488 return -1;
2489 }
2490
2491 if (input->basereg == -1 &&
2492 (input->indexreg == -1 || input->scale == 0)) {
2493 /*
2494 * It's a pure offset.
2495 */
2496 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2497 input->segment == NO_SEG) {
2498 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2499 input->type &= ~IP_REL;
2500 input->type |= MEMORY;
2501 }
2502
2503 if (bits == 64 &&
2504 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2505 nasm_error(ERR_NONFATAL, "RIP-relative addressing is prohibited for mib.");
2506 return -1;
2507 }
2508
2509 if (eaflags & EAF_BYTEOFFS ||
2510 (eaflags & EAF_WORDOFFS &&
2511 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2512 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2513 }
2514
2515 if (bits == 64 && (~input->type & IP_REL)) {
2516 output->sib_present = true;
2517 output->sib = GEN_SIB(0, 4, 5);
2518 output->bytes = 4;
2519 output->modrm = GEN_MODRM(0, rfield, 4);
2520 output->rip = false;
2521 } else {
2522 output->sib_present = false;
2523 output->bytes = (addrbits != 16 ? 4 : 2);
2524 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2525 output->rip = bits == 64;
2526 }
2527 } else {
2528 /*
2529 * It's an indirection.
2530 */
2531 int i = input->indexreg, b = input->basereg, s = input->scale;
2532 int32_t seg = input->segment;
2533 int hb = input->hintbase, ht = input->hinttype;
2534 int t, it, bt; /* register numbers */
2535 opflags_t x, ix, bx; /* register flags */
2536
2537 if (s == 0)
2538 i = -1; /* make this easy, at least */
2539
2540 if (is_register(i)) {
2541 it = nasm_regvals[i];
2542 ix = nasm_reg_flags[i];
2543 } else {
2544 it = -1;
2545 ix = 0;
2546 }
2547
2548 if (is_register(b)) {
2549 bt = nasm_regvals[b];
2550 bx = nasm_reg_flags[b];
2551 } else {
2552 bt = -1;
2553 bx = 0;
2554 }
2555
2556 /* if either one are a vector register... */
2557 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2558 opflags_t sok = BITS32 | BITS64;
2559 int32_t o = input->offset;
2560 int mod, scale, index, base;
2561
2562 /*
2563 * For a vector SIB, one has to be a vector and the other,
2564 * if present, a GPR. The vector must be the index operand.
2565 */
2566 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2567 if (s == 0)
2568 s = 1;
2569 else if (s != 1)
2570 goto err;
2571
2572 t = bt, bt = it, it = t;
2573 x = bx, bx = ix, ix = x;
2574 }
2575
2576 if (bt != -1) {
2577 if (REG_GPR & ~bx)
2578 goto err;
2579 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2580 sok &= bx;
2581 else
2582 goto err;
2583 }
2584
2585 /*
2586 * While we're here, ensure the user didn't specify
2587 * WORD or QWORD
2588 */
2589 if (input->disp_size == 16 || input->disp_size == 64)
2590 goto err;
2591
2592 if (addrbits == 16 ||
2593 (addrbits == 32 && !(sok & BITS32)) ||
2594 (addrbits == 64 && !(sok & BITS64)))
2595 goto err;
2596
2597 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2598 : ((ix & YMMREG & ~REG_EA)
2599 ? EA_YMMVSIB : EA_XMMVSIB));
2600
2601 output->rex |= rexflags(it, ix, REX_X);
2602 output->rex |= rexflags(bt, bx, REX_B);
2603 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2604
2605 index = it & 7; /* it is known to be != -1 */
2606
2607 switch (s) {
2608 case 1:
2609 scale = 0;
2610 break;
2611 case 2:
2612 scale = 1;
2613 break;
2614 case 4:
2615 scale = 2;
2616 break;
2617 case 8:
2618 scale = 3;
2619 break;
2620 default: /* then what the smeg is it? */
2621 goto err; /* panic */
2622 }
2623
2624 if (bt == -1) {
2625 base = 5;
2626 mod = 0;
2627 } else {
2628 base = (bt & 7);
2629 if (base != REG_NUM_EBP && o == 0 &&
2630 seg == NO_SEG && !forw_ref &&
2631 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2632 mod = 0;
2633 else if (IS_MOD_01())
2634 mod = 1;
2635 else
2636 mod = 2;
2637 }
2638
2639 output->sib_present = true;
2640 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2641 output->modrm = GEN_MODRM(mod, rfield, 4);
2642 output->sib = GEN_SIB(scale, index, base);
2643 } else if ((ix|bx) & (BITS32|BITS64)) {
2644 /*
2645 * it must be a 32/64-bit memory reference. Firstly we have
2646 * to check that all registers involved are type E/Rxx.
2647 */
2648 opflags_t sok = BITS32 | BITS64;
2649 int32_t o = input->offset;
2650
2651 if (it != -1) {
2652 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2653 sok &= ix;
2654 else
2655 goto err;
2656 }
2657
2658 if (bt != -1) {
2659 if (REG_GPR & ~bx)
2660 goto err; /* Invalid register */
2661 if (~sok & bx & SIZE_MASK)
2662 goto err; /* Invalid size */
2663 sok &= bx;
2664 }
2665
2666 /*
2667 * While we're here, ensure the user didn't specify
2668 * WORD or QWORD
2669 */
2670 if (input->disp_size == 16 || input->disp_size == 64)
2671 goto err;
2672
2673 if (addrbits == 16 ||
2674 (addrbits == 32 && !(sok & BITS32)) ||
2675 (addrbits == 64 && !(sok & BITS64)))
2676 goto err;
2677
2678 /* now reorganize base/index */
2679 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2680 ((hb == b && ht == EAH_NOTBASE) ||
2681 (hb == i && ht == EAH_MAKEBASE))) {
2682 /* swap if hints say so */
2683 t = bt, bt = it, it = t;
2684 x = bx, bx = ix, ix = x;
2685 }
2686
2687 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2688 /* make single reg base, unless hint */
2689 bt = it, bx = ix, it = -1, ix = 0;
2690 }
2691 if (eaflags & EAF_MIB) {
2692 /* only for mib operands */
2693 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2694 /*
2695 * make a single reg index [reg*1].
2696 * gas uses this form for an explicit index register.
2697 */
2698 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2699 }
2700 if ((ht == EAH_SUMMED) && bt == -1) {
2701 /* separate once summed index into [base, index] */
2702 bt = it, bx = ix, s--;
2703 }
2704 } else {
2705 if (((s == 2 && it != REG_NUM_ESP &&
2706 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2707 s == 3 || s == 5 || s == 9) && bt == -1) {
2708 /* convert 3*EAX to EAX+2*EAX */
2709 bt = it, bx = ix, s--;
2710 }
2711 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2712 (eaflags & EAF_TIMESTWO) &&
2713 (hb == b && ht == EAH_NOTBASE)) {
2714 /*
2715 * convert [NOSPLIT EAX*1]
2716 * to sib format with 0x0 displacement - [EAX*1+0].
2717 */
2718 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2719 }
2720 }
2721 if (s == 1 && it == REG_NUM_ESP) {
2722 /* swap ESP into base if scale is 1 */
2723 t = it, it = bt, bt = t;
2724 x = ix, ix = bx, bx = x;
2725 }
2726 if (it == REG_NUM_ESP ||
2727 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2728 goto err; /* wrong, for various reasons */
2729
2730 output->rex |= rexflags(it, ix, REX_X);
2731 output->rex |= rexflags(bt, bx, REX_B);
2732
2733 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2734 /* no SIB needed */
2735 int mod, rm;
2736
2737 if (bt == -1) {
2738 rm = 5;
2739 mod = 0;
2740 } else {
2741 rm = (bt & 7);
2742 if (rm != REG_NUM_EBP && o == 0 &&
2743 seg == NO_SEG && !forw_ref &&
2744 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2745 mod = 0;
2746 else if (IS_MOD_01())
2747 mod = 1;
2748 else
2749 mod = 2;
2750 }
2751
2752 output->sib_present = false;
2753 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2754 output->modrm = GEN_MODRM(mod, rfield, rm);
2755 } else {
2756 /* we need a SIB */
2757 int mod, scale, index, base;
2758
2759 if (it == -1)
2760 index = 4, s = 1;
2761 else
2762 index = (it & 7);
2763
2764 switch (s) {
2765 case 1:
2766 scale = 0;
2767 break;
2768 case 2:
2769 scale = 1;
2770 break;
2771 case 4:
2772 scale = 2;
2773 break;
2774 case 8:
2775 scale = 3;
2776 break;
2777 default: /* then what the smeg is it? */
2778 goto err; /* panic */
2779 }
2780
2781 if (bt == -1) {
2782 base = 5;
2783 mod = 0;
2784 } else {
2785 base = (bt & 7);
2786 if (base != REG_NUM_EBP && o == 0 &&
2787 seg == NO_SEG && !forw_ref &&
2788 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2789 mod = 0;
2790 else if (IS_MOD_01())
2791 mod = 1;
2792 else
2793 mod = 2;
2794 }
2795
2796 output->sib_present = true;
2797 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2798 output->modrm = GEN_MODRM(mod, rfield, 4);
2799 output->sib = GEN_SIB(scale, index, base);
2800 }
2801 } else { /* it's 16-bit */
2802 int mod, rm;
2803 int16_t o = input->offset;
2804
2805 /* check for 64-bit long mode */
2806 if (addrbits == 64)
2807 goto err;
2808
2809 /* check all registers are BX, BP, SI or DI */
2810 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2811 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2812 goto err;
2813
2814 /* ensure the user didn't specify DWORD/QWORD */
2815 if (input->disp_size == 32 || input->disp_size == 64)
2816 goto err;
2817
2818 if (s != 1 && i != -1)
2819 goto err; /* no can do, in 16-bit EA */
2820 if (b == -1 && i != -1) {
2821 int tmp = b;
2822 b = i;
2823 i = tmp;
2824 } /* swap */
2825 if ((b == R_SI || b == R_DI) && i != -1) {
2826 int tmp = b;
2827 b = i;
2828 i = tmp;
2829 }
2830 /* have BX/BP as base, SI/DI index */
2831 if (b == i)
2832 goto err; /* shouldn't ever happen, in theory */
2833 if (i != -1 && b != -1 &&
2834 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2835 goto err; /* invalid combinations */
2836 if (b == -1) /* pure offset: handled above */
2837 goto err; /* so if it gets to here, panic! */
2838
2839 rm = -1;
2840 if (i != -1)
2841 switch (i * 256 + b) {
2842 case R_SI * 256 + R_BX:
2843 rm = 0;
2844 break;
2845 case R_DI * 256 + R_BX:
2846 rm = 1;
2847 break;
2848 case R_SI * 256 + R_BP:
2849 rm = 2;
2850 break;
2851 case R_DI * 256 + R_BP:
2852 rm = 3;
2853 break;
2854 } else
2855 switch (b) {
2856 case R_SI:
2857 rm = 4;
2858 break;
2859 case R_DI:
2860 rm = 5;
2861 break;
2862 case R_BP:
2863 rm = 6;
2864 break;
2865 case R_BX:
2866 rm = 7;
2867 break;
2868 }
2869 if (rm == -1) /* can't happen, in theory */
2870 goto err; /* so panic if it does */
2871
2872 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2873 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2874 mod = 0;
2875 else if (IS_MOD_01())
2876 mod = 1;
2877 else
2878 mod = 2;
2879
2880 output->sib_present = false; /* no SIB - it's 16-bit */
2881 output->bytes = mod; /* bytes of offset needed */
2882 output->modrm = GEN_MODRM(mod, rfield, rm);
2883 }
2884 }
2885 }
2886
2887 output->size = 1 + output->sib_present + output->bytes;
2888 return output->type;
2889
2890 err:
2891 return output->type = EA_INVALID;
2892 }
2893
2894 static void add_asp(insn *ins, int addrbits)
2895 {
2896 int j, valid;
2897 int defdisp;
2898
2899 valid = (addrbits == 64) ? 64|32 : 32|16;
2900
2901 switch (ins->prefixes[PPS_ASIZE]) {
2902 case P_A16:
2903 valid &= 16;
2904 break;
2905 case P_A32:
2906 valid &= 32;
2907 break;
2908 case P_A64:
2909 valid &= 64;
2910 break;
2911 case P_ASP:
2912 valid &= (addrbits == 32) ? 16 : 32;
2913 break;
2914 default:
2915 break;
2916 }
2917
2918 for (j = 0; j < ins->operands; j++) {
2919 if (is_class(MEMORY, ins->oprs[j].type)) {
2920 opflags_t i, b;
2921
2922 /* Verify as Register */
2923 if (!is_register(ins->oprs[j].indexreg))
2924 i = 0;
2925 else
2926 i = nasm_reg_flags[ins->oprs[j].indexreg];
2927
2928 /* Verify as Register */
2929 if (!is_register(ins->oprs[j].basereg))
2930 b = 0;
2931 else
2932 b = nasm_reg_flags[ins->oprs[j].basereg];
2933
2934 if (ins->oprs[j].scale == 0)
2935 i = 0;
2936
2937 if (!i && !b) {
2938 int ds = ins->oprs[j].disp_size;
2939 if ((addrbits != 64 && ds > 8) ||
2940 (addrbits == 64 && ds == 16))
2941 valid &= ds;
2942 } else {
2943 if (!(REG16 & ~b))
2944 valid &= 16;
2945 if (!(REG32 & ~b))
2946 valid &= 32;
2947 if (!(REG64 & ~b))
2948 valid &= 64;
2949
2950 if (!(REG16 & ~i))
2951 valid &= 16;
2952 if (!(REG32 & ~i))
2953 valid &= 32;
2954 if (!(REG64 & ~i))
2955 valid &= 64;
2956 }
2957 }
2958 }
2959
2960 if (valid & addrbits) {
2961 ins->addr_size = addrbits;
2962 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2963 /* Add an address size prefix */
2964 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2965 ins->addr_size = (addrbits == 32) ? 16 : 32;
2966 } else {
2967 /* Impossible... */
2968 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2969 ins->addr_size = addrbits; /* Error recovery */
2970 }
2971
2972 defdisp = ins->addr_size == 16 ? 16 : 32;
2973
2974 for (j = 0; j < ins->operands; j++) {
2975 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2976 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2977 /*
2978 * mem_offs sizes must match the address size; if not,
2979 * strip the MEM_OFFS bit and match only EA instructions
2980 */
2981 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2982 }
2983 }
2984 }
The Netwide Assembler