kernel/2.6.29.6-aldebaran-rt/sound/pci/echoaudio/mona_dsp.c

   1 /****************************************************************************
   2
   3    Copyright Echo Digital Audio Corporation (c) 1998 - 2004
   4    All rights reserved
   5    www.echoaudio.com
   6
   7    This file is part of Echo Digital Audio's generic driver library.
   8
   9    Echo Digital Audio's generic driver library is free software;
  10    you can redistribute it and/or modify it under the terms of
  11    the GNU General Public License as published by the Free Software
  12    Foundation.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  22    MA  02111-1307, USA.
  23
  24    *************************************************************************
  25
  26  Translation from C++ and adaptation for use in ALSA-Driver
  27  were made by Giuliano Pochini <pochini@shiny.it>
  28
  29 ****************************************************************************/
  30
  31
  32 static int write_control_reg(struct echoaudio *chip, u32 value, char force);
  33 static int set_input_clock(struct echoaudio *chip, u16 clock);
  34 static int set_professional_spdif(struct echoaudio *chip, char prof);
  35 static int set_digital_mode(struct echoaudio *chip, u8 mode);
  36 static int load_asic_generic(struct echoaudio *chip, u32 cmd,
  37                              const struct firmware *asic);
  38 static int check_asic_status(struct echoaudio *chip);
  39
  40
  41 static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
  42 {
  43         int err;
  44
  45         DE_INIT(("init_hw() - Mona\n"));
  46         if (snd_BUG_ON((subdevice_id & 0xfff0) != MONA))
  47                 return -ENODEV;
  48
  49         if ((err = init_dsp_comm_page(chip))) {
  50                 DE_INIT(("init_hw - could not initialize DSP comm page\n"));
  51                 return err;
  52         }
  53
  54         chip->device_id = device_id;
  55         chip->subdevice_id = subdevice_id;
  56         chip->bad_board = TRUE;
  57         chip->input_clock_types =
  58                 ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF |
  59                 ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT;
  60         chip->digital_modes =
  61                 ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA |
  62                 ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL |
  63                 ECHOCAPS_HAS_DIGITAL_MODE_ADAT;
  64
  65         /* Mona comes in both '301 and '361 flavors */
  66         if (chip->device_id == DEVICE_ID_56361)
  67                 chip->dsp_code_to_load = &card_fw[FW_MONA_361_DSP];
  68         else
  69                 chip->dsp_code_to_load = &card_fw[FW_MONA_301_DSP];
  70
  71         chip->digital_mode = DIGITAL_MODE_SPDIF_RCA;
  72         chip->professional_spdif = FALSE;
  73         chip->digital_in_automute = TRUE;
  74
  75         if ((err = load_firmware(chip)) < 0)
  76                 return err;
  77         chip->bad_board = FALSE;
  78
  79         if ((err = init_line_levels(chip)) < 0)
  80                 return err;
  81
  82         err = set_digital_mode(chip, DIGITAL_MODE_SPDIF_RCA);
  83         if (err < 0)
  84                 return err;
  85         err = set_professional_spdif(chip, TRUE);
  86
  87         DE_INIT(("init_hw done\n"));
  88         return err;
  89 }
  90
  91
  92
  93 static u32 detect_input_clocks(const struct echoaudio *chip)
  94 {
  95         u32 clocks_from_dsp, clock_bits;
  96
  97         /* Map the DSP clock detect bits to the generic driver clock
  98            detect bits */
  99         clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
 100
 101         clock_bits = ECHO_CLOCK_BIT_INTERNAL;
 102
 103         if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF)
 104                 clock_bits |= ECHO_CLOCK_BIT_SPDIF;
 105
 106         if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT)
 107                 clock_bits |= ECHO_CLOCK_BIT_ADAT;
 108
 109         if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD)
 110                 clock_bits |= ECHO_CLOCK_BIT_WORD;
 111
 112         return clock_bits;
 113 }
 114
 115
 116
 117 /* Mona has an ASIC on the PCI card and another ASIC in the external box;
 118 both need to be loaded. */
 119 static int load_asic(struct echoaudio *chip)
 120 {
 121         u32 control_reg;
 122         int err;
 123         const struct firmware *asic;
 124
 125         if (chip->asic_loaded)
 126                 return 0;
 127
 128         mdelay(10);
 129
 130         if (chip->device_id == DEVICE_ID_56361)
 131                 asic = &card_fw[FW_MONA_361_1_ASIC48];
 132         else
 133                 asic = &card_fw[FW_MONA_301_1_ASIC48];
 134
 135         err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, asic);
 136         if (err < 0)
 137                 return err;
 138
 139         chip->asic_code = asic;
 140         mdelay(10);
 141
 142         /* Do the external one */
 143         err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_EXTERNAL_ASIC,
 144                                 &card_fw[FW_MONA_2_ASIC]);
 145         if (err < 0)
 146                 return err;
 147
 148         mdelay(10);
 149         err = check_asic_status(chip);
 150
 151         /* Set up the control register if the load succeeded -
 152            48 kHz, internal clock, S/PDIF RCA mode */
 153         if (!err) {
 154                 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
 155                 err = write_control_reg(chip, control_reg, TRUE);
 156         }
 157
 158         return err;
 159 }
 160
 161
 162
 163 /* Depending on what digital mode you want, Mona needs different ASICs
 164 loaded.  This function checks the ASIC needed for the new mode and sees
 165 if it matches the one already loaded. */
 166 static int switch_asic(struct echoaudio *chip, char double_speed)
 167 {
 168         const struct firmware *asic;
 169         int err;
 170
 171         /* Check the clock detect bits to see if this is
 172         a single-speed clock or a double-speed clock; load
 173         a new ASIC if necessary. */
 174         if (chip->device_id == DEVICE_ID_56361) {
 175                 if (double_speed)
 176                         asic = &card_fw[FW_MONA_361_1_ASIC96];
 177                 else
 178                         asic = &card_fw[FW_MONA_361_1_ASIC48];
 179         } else {
 180                 if (double_speed)
 181                         asic = &card_fw[FW_MONA_301_1_ASIC96];
 182                 else
 183                         asic = &card_fw[FW_MONA_301_1_ASIC48];
 184         }
 185
 186         if (asic != chip->asic_code) {
 187                 /* Load the desired ASIC */
 188                 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
 189                                         asic);
 190                 if (err < 0)
 191                         return err;
 192                 chip->asic_code = asic;
 193         }
 194
 195         return 0;
 196 }
 197
 198
 199
 200 static int set_sample_rate(struct echoaudio *chip, u32 rate)
 201 {
 202         u32 control_reg, clock;
 203         const struct firmware *asic;
 204         char force_write;
 205
 206         /* Only set the clock for internal mode. */
 207         if (chip->input_clock != ECHO_CLOCK_INTERNAL) {
 208                 DE_ACT(("set_sample_rate: Cannot set sample rate - "
 209                         "clock not set to CLK_CLOCKININTERNAL\n"));
 210                 /* Save the rate anyhow */
 211                 chip->comm_page->sample_rate = cpu_to_le32(rate);
 212                 chip->sample_rate = rate;
 213                 return 0;
 214         }
 215
 216         /* Now, check to see if the required ASIC is loaded */
 217         if (rate >= 88200) {
 218                 if (chip->digital_mode == DIGITAL_MODE_ADAT)
 219                         return -EINVAL;
 220                 if (chip->device_id == DEVICE_ID_56361)
 221                         asic = &card_fw[FW_MONA_361_1_ASIC96];
 222                 else
 223                         asic = &card_fw[FW_MONA_301_1_ASIC96];
 224         } else {
 225                 if (chip->device_id == DEVICE_ID_56361)
 226                         asic = &card_fw[FW_MONA_361_1_ASIC48];
 227                 else
 228                         asic = &card_fw[FW_MONA_301_1_ASIC48];
 229         }
 230
 231         force_write = 0;
 232         if (asic != chip->asic_code) {
 233                 int err;
 234                 /* Load the desired ASIC (load_asic_generic() can sleep) */
 235                 spin_unlock_irq(&chip->lock);
 236                 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC,
 237                                         asic);
 238                 spin_lock_irq(&chip->lock);
 239
 240                 if (err < 0)
 241                         return err;
 242                 chip->asic_code = asic;
 243                 force_write = 1;
 244         }
 245
 246         /* Compute the new control register value */
 247         clock = 0;
 248         control_reg = le32_to_cpu(chip->comm_page->control_register);
 249         control_reg &= GML_CLOCK_CLEAR_MASK;
 250         control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
 251
 252         switch (rate) {
 253         case 96000:
 254                 clock = GML_96KHZ;
 255                 break;
 256         case 88200:
 257                 clock = GML_88KHZ;
 258                 break;
 259         case 48000:
 260                 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1;
 261                 break;
 262         case 44100:
 263                 clock = GML_44KHZ;
 264                 /* Professional mode */
 265                 if (control_reg & GML_SPDIF_PRO_MODE)
 266                         clock |= GML_SPDIF_SAMPLE_RATE0;
 267                 break;
 268         case 32000:
 269                 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 |
 270                         GML_SPDIF_SAMPLE_RATE1;
 271                 break;
 272         case 22050:
 273                 clock = GML_22KHZ;
 274                 break;
 275         case 16000:
 276                 clock = GML_16KHZ;
 277                 break;
 278         case 11025:
 279                 clock = GML_11KHZ;
 280                 break;
 281         case 8000:
 282                 clock = GML_8KHZ;
 283                 break;
 284         default:
 285                 DE_ACT(("set_sample_rate: %d invalid!\n", rate));
 286                 return -EINVAL;
 287         }
 288
 289         control_reg |= clock;
 290
 291         chip->comm_page->sample_rate = cpu_to_le32(rate);       /* ignored by the DSP */
 292         chip->sample_rate = rate;
 293         DE_ACT(("set_sample_rate: %d clock %d\n", rate, clock));
 294
 295         return write_control_reg(chip, control_reg, force_write);
 296 }
 297
 298
 299
 300 static int set_input_clock(struct echoaudio *chip, u16 clock)
 301 {
 302         u32 control_reg, clocks_from_dsp;
 303         int err;
 304
 305         DE_ACT(("set_input_clock:\n"));
 306
 307         /* Prevent two simultaneous calls to switch_asic() */
 308         if (atomic_read(&chip->opencount))
 309                 return -EAGAIN;
 310
 311         /* Mask off the clock select bits */
 312         control_reg = le32_to_cpu(chip->comm_page->control_register) &
 313                 GML_CLOCK_CLEAR_MASK;
 314         clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
 315
 316         switch (clock) {
 317         case ECHO_CLOCK_INTERNAL:
 318                 DE_ACT(("Set Mona clock to INTERNAL\n"));
 319                 chip->input_clock = ECHO_CLOCK_INTERNAL;
 320                 return set_sample_rate(chip, chip->sample_rate);
 321         case ECHO_CLOCK_SPDIF:
 322                 if (chip->digital_mode == DIGITAL_MODE_ADAT)
 323                         return -EAGAIN;
 324                 spin_unlock_irq(&chip->lock);
 325                 err = switch_asic(chip, clocks_from_dsp &
 326                                   GML_CLOCK_DETECT_BIT_SPDIF96);
 327                 spin_lock_irq(&chip->lock);
 328                 if (err < 0)
 329                         return err;
 330                 DE_ACT(("Set Mona clock to SPDIF\n"));
 331                 control_reg |= GML_SPDIF_CLOCK;
 332                 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96)
 333                         control_reg |= GML_DOUBLE_SPEED_MODE;
 334                 else
 335                         control_reg &= ~GML_DOUBLE_SPEED_MODE;
 336                 break;
 337         case ECHO_CLOCK_WORD:
 338                 DE_ACT(("Set Mona clock to WORD\n"));
 339                 spin_unlock_irq(&chip->lock);
 340                 err = switch_asic(chip, clocks_from_dsp &
 341                                   GML_CLOCK_DETECT_BIT_WORD96);
 342                 spin_lock_irq(&chip->lock);
 343                 if (err < 0)
 344                         return err;
 345                 control_reg |= GML_WORD_CLOCK;
 346                 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96)
 347                         control_reg |= GML_DOUBLE_SPEED_MODE;
 348                 else
 349                         control_reg &= ~GML_DOUBLE_SPEED_MODE;
 350                 break;
 351         case ECHO_CLOCK_ADAT:
 352                 DE_ACT(("Set Mona clock to ADAT\n"));
 353                 if (chip->digital_mode != DIGITAL_MODE_ADAT)
 354                         return -EAGAIN;
 355                 control_reg |= GML_ADAT_CLOCK;
 356                 control_reg &= ~GML_DOUBLE_SPEED_MODE;
 357                 break;
 358         default:
 359                 DE_ACT(("Input clock 0x%x not supported for Mona\n", clock));
 360                 return -EINVAL;
 361         }
 362
 363         chip->input_clock = clock;
 364         return write_control_reg(chip, control_reg, TRUE);
 365 }
 366
 367
 368
 369 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode)
 370 {
 371         u32 control_reg;
 372         int err, incompatible_clock;
 373
 374         /* Set clock to "internal" if it's not compatible with the new mode */
 375         incompatible_clock = FALSE;
 376         switch (mode) {
 377         case DIGITAL_MODE_SPDIF_OPTICAL:
 378         case DIGITAL_MODE_SPDIF_RCA:
 379                 if (chip->input_clock == ECHO_CLOCK_ADAT)
 380                         incompatible_clock = TRUE;
 381                 break;
 382         case DIGITAL_MODE_ADAT:
 383                 if (chip->input_clock == ECHO_CLOCK_SPDIF)
 384                         incompatible_clock = TRUE;
 385                 break;
 386         default:
 387                 DE_ACT(("Digital mode not supported: %d\n", mode));
 388                 return -EINVAL;
 389         }
 390
 391         spin_lock_irq(&chip->lock);
 392
 393         if (incompatible_clock) {       /* Switch to 48KHz, internal */
 394                 chip->sample_rate = 48000;
 395                 set_input_clock(chip, ECHO_CLOCK_INTERNAL);
 396         }
 397
 398         /* Clear the current digital mode */
 399         control_reg = le32_to_cpu(chip->comm_page->control_register);
 400         control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
 401
 402         /* Tweak the control reg */
 403         switch (mode) {
 404         case DIGITAL_MODE_SPDIF_OPTICAL:
 405                 control_reg |= GML_SPDIF_OPTICAL_MODE;
 406                 break;
 407         case DIGITAL_MODE_SPDIF_RCA:
 408                 /* GML_SPDIF_OPTICAL_MODE bit cleared */
 409                 break;
 410         case DIGITAL_MODE_ADAT:
 411                 /* If the current ASIC is the 96KHz ASIC, switch the ASIC
 412                    and set to 48 KHz */
 413                 if (chip->asic_code == &card_fw[FW_MONA_361_1_ASIC96] ||
 414                     chip->asic_code == &card_fw[FW_MONA_301_1_ASIC96]) {
 415                         set_sample_rate(chip, 48000);
 416                 }
 417                 control_reg |= GML_ADAT_MODE;
 418                 control_reg &= ~GML_DOUBLE_SPEED_MODE;
 419                 break;
 420         }
 421
 422         err = write_control_reg(chip, control_reg, FALSE);
 423         spin_unlock_irq(&chip->lock);
 424         if (err < 0)
 425                 return err;
 426         chip->digital_mode = mode;
 427
 428         DE_ACT(("set_digital_mode to %d\n", mode));
 429         return incompatible_clock;
 430 }