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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / staging / winbond / wbhal_s.h
blob276d2b12632f2e43d8e9b6ab232d50cf0623e734
1 #ifndef __WINBOND_WBHAL_S_H
2 #define __WINBOND_WBHAL_S_H
3
4 #include <linux/types.h>
5
6 #include "common.h"
7
8 //[20040722 WK]
9 #define HAL_LED_SET_MASK 0x001c //20060901 Extend
10 #define HAL_LED_SET_SHIFT 2
11
12 //supported RF type
13 #define RF_MAXIM_2825 0
14 #define RF_MAXIM_2827 1
15 #define RF_MAXIM_2828 2
16 #define RF_MAXIM_2829 3
17 #define RF_MAXIM_V1 15
18 #define RF_AIROHA_2230 16
19 #define RF_AIROHA_7230 17
20 #define RF_AIROHA_2230S 18 // 20060420 Add this
21 // #define RF_RFMD_2959 32 // 20060626 Remove all about RFMD
22 #define RF_WB_242 33
23 #define RF_WB_242_1 34 // 20060619.5 Add
24 #define RF_DECIDE_BY_INF 255
25
26 //----------------------------------------------------------------
27 // The follow define connect to upper layer
28 // User must modify for connection between HAL and upper layer
29 //----------------------------------------------------------------
30
31
32
33
34 /////////////////////////////////////////////////////////////////////////////////////////////////////
35 //================================================================================================
36 // Common define
37 //================================================================================================
38 #define HAL_USB_MODE_BURST( _H ) (_H->SoftwareSet & 0x20 ) // Bit 5 20060901 Modify
39
40 // Scan interval
41 #define SCAN_MAX_CHNL_TIME (50)
42
43 // For TxL2 Frame typr recognise
44 #define FRAME_TYPE_802_3_DATA 0
45 #define FRAME_TYPE_802_11_MANAGEMENT 1
46 #define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2
47 #define FRAME_TYPE_802_11_CONTROL 3
48 #define FRAME_TYPE_802_11_DATA 4
49 #define FRAME_TYPE_PROMISCUOUS 5
50
51 // The follow definition is used for convert the frame--------------------
52 #define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset
53 #define DOT_3_TYPE_OFFSET 12
54 #define DOT_11_MAC_HEADER_SIZE 24
55 #define DOT_11_SNAP_SIZE 6
56 #define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame. Type encapsulatuin.
57 #define DEFAULT_SIFSTIME 10
58 #define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment
59 #define DEFAULT_MSDU_LIFE_TIME 0xffff
60
61 #define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144+48)
62 #define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72+24)
63 #define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16+4+6)
64 #define Tsym 4
65
66 // Frame Type of Bits (2, 3)---------------------------------------------
67 #define MAC_TYPE_MANAGEMENT 0x00
68 #define MAC_TYPE_CONTROL 0x04
69 #define MAC_TYPE_DATA 0x08
70 #define MASK_FRAGMENT_NUMBER 0x000F
71 #define SEQUENCE_NUMBER_SHIFT 4
72
73 #define HAL_WOL_TYPE_WAKEUP_FRAME 0x01
74 #define HAL_WOL_TYPE_MAGIC_PACKET 0x02
75
76 // 20040106 ADDED
77 #define HAL_KEYTYPE_WEP40 0
78 #define HAL_KEYTYPE_WEP104 1
79 #define HAL_KEYTYPE_TKIP 2 // 128 bit key
80 #define HAL_KEYTYPE_AES_CCMP 3 // 128 bit key
81
82 // For VM state
83 enum {
84 VM_STOP = 0,
85 VM_RUNNING,
86 VM_COMPLETED
87 };
88
89 // Be used for 802.11 mac header
90 typedef struct _MAC_FRAME_CONTROL {
91 u8 mac_frame_info; // this is a combination of the protovl version, type and subtype
92 u8 to_ds:1;
93 u8 from_ds:1;
94 u8 more_frag:1;
95 u8 retry:1;
96 u8 pwr_mgt:1;
97 u8 more_data:1;
98 u8 WEP:1;
99 u8 order:1;
100 } MAC_FRAME_CONTROL, *PMAC_FRAME_CONTROL;
101
102 //-----------------------------------------------------
103 // Normal Key table format
104 //-----------------------------------------------------
105 // The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX
106 #define MAX_KEY_TABLE 24 // 24 entry for storing key data
107 #define GROUP_KEY_START_INDEX 4
108 #define MAPPING_KEY_START_INDEX 8
109 typedef struct _KEY_TABLE
110 {
111 u32 DW0_Valid:1;
112 u32 DW0_NullKey:1;
113 u32 DW0_Security_Mode:2;//0:WEP 40 bit 1:WEP 104 bit 2:TKIP 128 bit 3:CCMP 128 bit
114 u32 DW0_WEPON:1;
115 u32 DW0_RESERVED:11;
116 u32 DW0_Address1:16;
117
118 u32 DW1_Address2;
119
120 u32 DW2_RxSequenceCount1;
121
122 u32 DW3_RxSequenceCount2:16;
123 u32 DW3_RESERVED:16;
124
125 u32 DW4_TxSequenceCount1;
126
127 u32 DW5_TxSequenceCount2:16;
128 u32 DW5_RESERVED:16;
129
130 } KEY_TABLE, *PKEY_TABLE;
131
132 //--------------------------------------------------------
133 // Descriptor
134 //--------------------------------------------------------
135 #define MAX_DESCRIPTOR_BUFFER_INDEX 8 // Have to multiple of 2
136 //#define FLAG_ERROR_TX_MASK cpu_to_le32(0x000000bf) //20061009 marked by anson's endian
137 #define FLAG_ERROR_TX_MASK 0x000000bf //20061009 anson's endian
138 //#define FLAG_ERROR_RX_MASK 0x00000c3f
139 //#define FLAG_ERROR_RX_MASK cpu_to_le32(0x0000083f) //20061009 marked by anson's endian
140 //Don't care replay error,
141 //it is handled by S/W
142 #define FLAG_ERROR_RX_MASK 0x0000083f //20060926 anson's endian
143
144 #define FLAG_BAND_RX_MASK 0x10000000 //Bit 28
145
146 typedef struct _R00_DESCRIPTOR
147 {
148 union
149 {
150 u32 value;
151 #ifdef _BIG_ENDIAN_ //20060926 anson's endian
152 struct
153 {
154 u32 R00_packet_or_buffer_status:1;
155 u32 R00_packet_in_fifo:1;
156 u32 R00_RESERVED:2;
157 u32 R00_receive_byte_count:12;
158 u32 R00_receive_time_index:16;
159 };
160 #else
161 struct
162 {
163 u32 R00_receive_time_index:16;
164 u32 R00_receive_byte_count:12;
165 u32 R00_RESERVED:2;
166 u32 R00_packet_in_fifo:1;
167 u32 R00_packet_or_buffer_status:1;
168 };
169 #endif
170 };
171 } R00_DESCRIPTOR, *PR00_DESCRIPTOR;
172
173 typedef struct _T00_DESCRIPTOR
174 {
175 union
176 {
177 u32 value;
178 #ifdef _BIG_ENDIAN_ //20061009 anson's endian
179 struct
180 {
181 u32 T00_first_mpdu:1; // for hardware use
182 u32 T00_last_mpdu:1; // for hardware use
183 u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
184 u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
185 u32 T00_RESERVED_ID:2;//3 bit ID reserved
186 u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
187 u32 T00_RESERVED:4;
188 u32 T00_header_length:6;
189 u32 T00_frame_length:12;
190 };
191 #else
192 struct
193 {
194 u32 T00_frame_length:12;
195 u32 T00_header_length:6;
196 u32 T00_RESERVED:4;
197 u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c
198 u32 T00_RESERVED_ID:2;//3 bit ID reserved
199 u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
200 u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used
201 u32 T00_last_mpdu:1; // for hardware use
202 u32 T00_first_mpdu:1; // for hardware use
203 };
204 #endif
205 };
206 } T00_DESCRIPTOR, *PT00_DESCRIPTOR;
207
208 typedef struct _R01_DESCRIPTOR
209 {
210 union
211 {
212 u32 value;
213 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
214 struct
215 {
216 u32 R01_RESERVED:3;
217 u32 R01_mod_type:1;
218 u32 R01_pre_type:1;
219 u32 R01_data_rate:3;
220 u32 R01_AGC_state:8;
221 u32 R01_LNA_state:2;
222 u32 R01_decryption_method:2;
223 u32 R01_mic_error:1;
224 u32 R01_replay:1;
225 u32 R01_broadcast_frame:1;
226 u32 R01_multicast_frame:1;
227 u32 R01_directed_frame:1;
228 u32 R01_receive_frame_antenna_selection:1;
229 u32 R01_frame_receive_during_atim_window:1;
230 u32 R01_protocol_version_error:1;
231 u32 R01_authentication_frame_icv_error:1;
232 u32 R01_null_key_to_authentication_frame:1;
233 u32 R01_icv_error:1;
234 u32 R01_crc_error:1;
235 };
236 #else
237 struct
238 {
239 u32 R01_crc_error:1;
240 u32 R01_icv_error:1;
241 u32 R01_null_key_to_authentication_frame:1;
242 u32 R01_authentication_frame_icv_error:1;
243 u32 R01_protocol_version_error:1;
244 u32 R01_frame_receive_during_atim_window:1;
245 u32 R01_receive_frame_antenna_selection:1;
246 u32 R01_directed_frame:1;
247 u32 R01_multicast_frame:1;
248 u32 R01_broadcast_frame:1;
249 u32 R01_replay:1;
250 u32 R01_mic_error:1;
251 u32 R01_decryption_method:2;
252 u32 R01_LNA_state:2;
253 u32 R01_AGC_state:8;
254 u32 R01_data_rate:3;
255 u32 R01_pre_type:1;
256 u32 R01_mod_type:1;
257 u32 R01_RESERVED:3;
258 };
259 #endif
260 };
261 } R01_DESCRIPTOR, *PR01_DESCRIPTOR;
262
263 typedef struct _T01_DESCRIPTOR
264 {
265 union
266 {
267 u32 value;
268 #ifdef _BIG_ENDIAN_ //20061009 anson's endian
269 struct
270 {
271 u32 T01_rts_cts_duration:16;
272 u32 T01_fall_back_rate:3;
273 u32 T01_add_rts:1;
274 u32 T01_add_cts:1;
275 u32 T01_modulation_type:1;
276 u32 T01_plcp_header_length:1;
277 u32 T01_transmit_rate:3;
278 u32 T01_wep_id:2;
279 u32 T01_add_challenge_text:1;
280 u32 T01_inhibit_crc:1;
281 u32 T01_loop_back_wep_mode:1;
282 u32 T01_retry_abort_ebable:1;
283 };
284 #else
285 struct
286 {
287 u32 T01_retry_abort_ebable:1;
288 u32 T01_loop_back_wep_mode:1;
289 u32 T01_inhibit_crc:1;
290 u32 T01_add_challenge_text:1;
291 u32 T01_wep_id:2;
292 u32 T01_transmit_rate:3;
293 u32 T01_plcp_header_length:1;
294 u32 T01_modulation_type:1;
295 u32 T01_add_cts:1;
296 u32 T01_add_rts:1;
297 u32 T01_fall_back_rate:3;
298 u32 T01_rts_cts_duration:16;
299 };
300 #endif
301 };
302 } T01_DESCRIPTOR, *PT01_DESCRIPTOR;
303
304 typedef struct _T02_DESCRIPTOR
305 {
306 union
307 {
308 u32 value;
309 #ifdef _BIG_ENDIAN_ //20061009 add by anson's endian
310 struct
311 {
312 u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
313 u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
314 u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
315 u32 T02_Tx_PktID:4;
316 u32 T02_MPDU_Cnt:4;
317 u32 T02_RTS_Cnt:4;
318 u32 T02_RESERVED:7;
319 u32 T02_transmit_complete:1;
320 u32 T02_transmit_abort_due_to_TBTT:1;
321 u32 T02_effective_transmission_rate:1;
322 u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
323 u32 T02_discard_due_to_null_wep_key:1;
324 u32 T02_RESERVED_1:1;
325 u32 T02_out_of_MaxTxMSDULiftTime:1;
326 u32 T02_transmit_abort:1;
327 u32 T02_transmit_fail:1;
328 };
329 #else
330 struct
331 {
332 u32 T02_transmit_fail:1;
333 u32 T02_transmit_abort:1;
334 u32 T02_out_of_MaxTxMSDULiftTime:1;
335 u32 T02_RESERVED_1:1;
336 u32 T02_discard_due_to_null_wep_key:1;
337 u32 T02_transmit_without_encryption_due_to_wep_on_false:1;
338 u32 T02_effective_transmission_rate:1;
339 u32 T02_transmit_abort_due_to_TBTT:1;
340 u32 T02_transmit_complete:1;
341 u32 T02_RESERVED:7;
342 u32 T02_RTS_Cnt:4;
343 u32 T02_MPDU_Cnt:4;
344 u32 T02_Tx_PktID:4;
345 u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting
346 u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
347 u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting
348 };
349 #endif
350 };
351 } T02_DESCRIPTOR, *PT02_DESCRIPTOR;
352
353 typedef struct _DESCRIPTOR { // Skip length = 8 DWORD
354 // ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition
355 u8 Descriptor_ID;
356 //----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------
357 u8 RESERVED[3];
358
359 u16 FragmentThreshold;
360 u8 InternalUsed;//Only can be used by operation of descriptor definition
361 u8 Type;// 0: 802.3 1:802.11 data frame 2:802.11 management frame
362
363 u8 PreambleMode;// 0: short 1:long
364 u8 TxRate;
365 u8 FragmentCount;
366 u8 EapFix; // For speed up key install
367
368 // For R00 and T00 ----------------------------------------------
369 union
370 {
371 R00_DESCRIPTOR R00;
372 T00_DESCRIPTOR T00;
373 };
374
375 // For R01 and T01 ----------------------------------------------
376 union
377 {
378 R01_DESCRIPTOR R01;
379 T01_DESCRIPTOR T01;
380 };
381
382 // For R02 and T02 ----------------------------------------------
383 union
384 {
385 u32 R02;
386 T02_DESCRIPTOR T02;
387 };
388
389 // For R03 and T03 ----------------------------------------------
390 // For software used
391 union
392 {
393 u32 R03;
394 u32 T03;
395 struct
396 {
397 u8 buffer_number;
398 u8 buffer_start_index;
399 u16 buffer_total_size;
400 };
401 };
402
403 // For storing the buffer
404 u16 buffer_size[ MAX_DESCRIPTOR_BUFFER_INDEX ];
405 void* buffer_address[ MAX_DESCRIPTOR_BUFFER_INDEX ];//931130.4.q
406
407 } DESCRIPTOR, *PDESCRIPTOR;
408
409
410 #define DEFAULT_NULL_PACKET_COUNT 180000 //20060828.1 Add. 180 seconds
411
412 #define MAX_TXVGA_EEPROM 9 //How many word(u16) of EEPROM will be used for TxVGA
413 #define MAX_RF_PARAMETER 32
414
415 typedef struct _TXVGA_FOR_50 {
416 u8 ChanNo;
417 u8 TxVgaValue;
418 } TXVGA_FOR_50;
419
420
421 //=====================================================================
422 // Device related include
423 //=====================================================================
424
425 #include "wbusb_s.h"
426 #include "wb35reg_s.h"
427 #include "wb35tx_s.h"
428 #include "wb35rx_s.h"
429
430
431 // For Hal using ==================================================================
432 typedef struct _HW_DATA_T
433 {
434 // For compatible with 33
435 u32 revision;
436 u32 BB3c_cal; // The value for Tx calibration comes from EEPROM
437 u32 BB54_cal; // The value for Rx calibration comes from EEPROM
438
439
440 // For surprise remove
441 u32 SurpriseRemove; // 0: Normal 1: Surprise remove
442 u8 InitialResource;
443 u8 IsKeyPreSet;
444 u8 CalOneTime; // 20060630.1
445
446 u8 VCO_trim;
447
448 // For Fix 1'st DMA bug
449 u32 FragCount;
450 u32 DMAFix; //V1_DMA_FIX The variable can be removed if driver want to save mem space for V2.
451
452 //===============================================
453 // Definition for MAC address
454 //===============================================
455 u8 PermanentMacAddress[ETH_LENGTH_OF_ADDRESS + 2]; // The Enthernet addr that are stored in EEPROM. + 2 to 8-byte alignment
456 u8 CurrentMacAddress[ETH_LENGTH_OF_ADDRESS + 2]; // The Enthernet addr that are in used. + 2 to 8-byte alignment
457
458 //=====================================================================
459 // Definition for 802.11
460 //=====================================================================
461 u8 *bssid_pointer; // Used by hal_get_bssid for return value
462 u8 bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer
463 u8 ssid[32];// maximum ssid length is 32 byte
464
465 u16 AID;
466 u8 ssid_length;
467 u8 Channel;
468
469 u16 ListenInterval;
470 u16 CapabilityInformation;
471
472 u16 BeaconPeriod;
473 u16 ProbeDelay;
474
475 u8 bss_type;// 0: IBSS_NET or 1:ESS_NET
476 u8 preamble;// 0: short preamble, 1: long preamble
477 u8 slot_time_select;// 9 or 20 value
478 u8 phy_type;// Phy select
479
480 u32 phy_para[MAX_RF_PARAMETER];
481 u32 phy_number;
482
483 u32 CurrentRadioSw; // 20060320.2 0:On 1:Off
484 u32 CurrentRadioHw; // 20060825 0:On 1:Off
485
486 u8 *power_save_point; // Used by hal_get_power_save_mode for return value
487 u8 cwmin;
488 u8 desired_power_save;
489 u8 dtim;// Is running dtim
490 u8 mapping_key_replace_index;//In Key table, the next index be replaced 931130.4.r
491
492 u16 MaxReceiveLifeTime;
493 u16 FragmentThreshold;
494 u16 FragmentThreshold_tmp;
495 u16 cwmax;
496
497 u8 Key_slot[MAX_KEY_TABLE][8]; //Ownership record for key slot. For Alignment
498 u32 Key_content[MAX_KEY_TABLE][12]; // 10DW for each entry + 2 for burst command( Off and On valid bit)
499 u8 CurrentDefaultKeyIndex;
500 u32 CurrentDefaultKeyLength;
501
502 //========================================================================
503 // Variable for each module
504 //========================================================================
505 WBUSB WbUsb; // Need WbUsb.h
506 struct wb35_reg reg; // Need Wb35Reg.h
507 WB35TX Wb35Tx; // Need Wb35Tx.h
508 WB35RX Wb35Rx; // Need Wb35Rx.h
509
510 struct timer_list LEDTimer;// For LED
511
512 u32 LEDpoint;// For LED
513
514 u32 dto_tx_retry_count; // LA20040210_DTO kevin
515 u32 dto_tx_frag_count; // LA20040210_DTO kevin
516 u32 rx_ok_count[13]; // index=0: total rx ok
517 //u32 rx_ok_bytes[13]; // index=0, total rx ok bytes
518 u32 rx_err_count[13]; // index=0: total rx err
519
520 //for Tx debug
521 u32 tx_TBTT_start_count;
522 u32 tx_ETR_count;
523 u32 tx_WepOn_false_count;
524 u32 tx_Null_key_count;
525 u32 tx_retry_count[8];
526
527 u8 PowerIndexFromEEPROM; // For 2412MHz
528 u8 power_index;
529 u8 IsWaitJoinComplete; // TRUE: set join request
530 u8 band;
531
532 u16 SoftwareSet;
533 u16 Reserved_s;
534
535 u32 IsInitOK; // 0: Driver starting 1: Driver init OK
536
537 // For Phy calibration
538 s32 iq_rsdl_gain_tx_d2;
539 s32 iq_rsdl_phase_tx_d2;
540 u32 txvga_setting_for_cal; // 20060703.1 Add
541
542 u8 TxVgaSettingInEEPROM[ (((MAX_TXVGA_EEPROM*2)+3) & ~0x03) ]; // 20060621 For backup EEPROM value
543 u8 TxVgaFor24[16]; // Max is 14, 2 for alignment
544 TXVGA_FOR_50 TxVgaFor50[36]; // 35 channels in 5G. 35x2 = 70 byte. 2 for alignments
545
546 u16 Scan_Interval;
547 u16 RESERVED6;
548
549 // LED control
550 u32 LED_control;
551 // LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0]
552 // Gray_Led
553 // For Led gray setting
554 // Led
555 // 0: normal control, LED behavior will decide by EEPROM setting
556 // 1: Turn off specific LED
557 // 2: Always on specific LED
558 // 3: slow blinking specific LED
559 // 4: fast blinking specific LED
560 // 5: WPS led control is set. Led0 is Red, Led1 id Green
561 // Led[1] is parameter for WPS LED mode
562 // // 1:InProgress 2: Error 3: Session overlap 4: Success 20061108 control
563
564 u32 LED_LinkOn; //Turn LED on control
565 u32 LED_Scanning; // Let LED in scan process control
566 u32 LED_Blinking; // Temp variable for shining
567 u32 RxByteCountLast;
568 u32 TxByteCountLast;
569
570 atomic_t SurpriseRemoveCount;
571
572 // For global timer
573 u32 time_count;//TICK_TIME_100ms 1 = 100ms
574
575 // For error recover
576 u32 HwStop;
577
578 // 20060828.1 for avoid AP disconnect
579 u32 NullPacketCount;
580
581 } hw_data_t, *phw_data_t;
582
583 // The mapping of Rx and Tx descriptor field
584 typedef struct _HAL_RATE
585 {
586 // DSSS
587 u32 RESERVED_0;
588 u32 NumRate2MS;
589 u32 NumRate55MS;
590 u32 NumRate11MS;
591
592 u32 RESERVED_1[4];
593
594 u32 NumRate1M;
595 u32 NumRate2ML;
596 u32 NumRate55ML;
597 u32 NumRate11ML;
598
599 u32 RESERVED_2[4];
600
601 // OFDM
602 u32 NumRate6M;
603 u32 NumRate9M;
604 u32 NumRate12M;
605 u32 NumRate18M;
606 u32 NumRate24M;
607 u32 NumRate36M;
608 u32 NumRate48M;
609 u32 NumRate54M;
610 } HAL_RATE, *PHAL_RATE;
611
612 #endif
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