kernel/2.6.29.6-aldebaran-rt/drivers/staging/otus/hal/hpusb.h

   1 /*
   2  * Copyright (c) 2000-2005 ZyDAS Technology Corporation
   3  * Copyright (c) 2007-2008 Atheros Communications Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17 /*  Module Name : ud_defs.h                                             */
  18 /*                                                                      */
  19 /*  Abstract                                                            */
  20 /*      This module contains USB data structure definitions.            */
  21 /*                                                                      */
  22 /*  NOTES                                                               */
  23 /*      None                                                            */
  24 /*                                                                      */
  25 /************************************************************************/
  26
  27 #ifndef _HPUSB_H
  28 #define _HPUSB_H
  29
  30 #define ZM_OTUS_ENABLE_RETRY_FREQ_CHANGE
  31 #define ZM_BEACON_BUFFER_ADDRESS            0x117900
  32
  33 #define ZM_MAX_CMD_SIZE                     64
  34 #define ZM_HAL_MAX_EEPROM_REQ               510
  35 #define ZM_HAL_MAX_EEPROM_PRQ               2
  36
  37 /* For USB STREAM mode */
  38 #ifdef ZM_DISABLE_AMSDU8K_SUPPORT
  39 #define ZM_MAX_USB_IN_TRANSFER_SIZE         4096
  40 #else
  41 #define ZM_MAX_USB_IN_TRANSFER_SIZE         8192
  42 #endif
  43 #define ZM_USB_STREAM_MODE_TAG_LEN          4
  44 #define ZM_USB_STREAM_MODE_TAG              0x4e00
  45 #define ZM_USB_MAX_EPINT_BUFFER             64
  46
  47 struct zsCmdQ
  48 {
  49     u16_t src;
  50     u16_t cmdLen;
  51     u8_t* buf;
  52     u32_t cmd[ZM_MAX_CMD_SIZE/4];
  53 };
  54
  55 struct zsCommand
  56 {
  57     u16_t delayWcmdCount;
  58     u32_t delayWcmdAddr[(ZM_CMD_QUEUE_SIZE-4)/4];
  59     u32_t delayWcmdVal[(ZM_CMD_QUEUE_SIZE-4)/4];
  60 };
  61
  62 struct zsHalRxInfo
  63 {
  64     u32_t currentRSSI[7];       /* RSSI combined */
  65     u32_t currentRxEVM[14];
  66     u32_t currentRxDataMT;
  67     u32_t currentRxDataMCS;
  68     u32_t currentRxDataBW;
  69     u32_t currentRxDataSG;
  70 };
  71
  72 struct zsHpPriv
  73 {
  74     u16_t hwFrequency;
  75     u8_t  hwBw40;
  76     u8_t  hwExtOffset;
  77
  78     u8_t  disableDfsCh;
  79
  80     u32_t halCapability;
  81
  82     /* Fortunately the second loop can be disabled with a bit */
  83     /* called en_pd_dc_offset_thr                             */
  84     u8_t hwNotFirstInit;
  85
  86     /* command queue */
  87     u16_t               cmdHead;
  88     u16_t               cmdTail;
  89 #ifdef ZM_XP_USB_MULTCMD
  90     u16_t               cmdSend;  // Used for Mult send USB cmd
  91 #endif
  92     struct zsCmdQ       cmdQ[ZM_CMD_QUEUE_SIZE];
  93     u16_t               cmdPending;
  94     struct zsCommand    cmd; /* buffer for delayed commands */
  95     u8_t                ledMode[2];
  96     u32_t               ctlBusy;
  97     u32_t               extBusy;
  98
  99     /*
 100      * ANI & Radar support.
 101      */
 102     u32_t   procPhyErr;         /* Process Phy errs */
 103     u8_t hasHwPhyCounters;   /* Hardware has phy counters */
 104     u32_t   aniPeriod;          /* ani update list period */
 105     struct zsAniStats   stats;      /* various statistics */
 106     struct zsAniState   *curani;    /* cached last reference */
 107     struct zsAniState   ani[50];   /* per-channel state */
 108
 109     /*
 110      * Ani tables that change between the 5416 and 5312.
 111      * These get set at attach time.
 112      * XXX don't belong here
 113      * XXX need better explanation
 114      */
 115     s32_t     totalSizeDesired[5];
 116     s32_t     coarseHigh[5];
 117     s32_t     coarseLow[5];
 118     s32_t     firpwr[5];
 119
 120     /*
 121      * ANI related PHY register value.
 122      */
 123     u32_t regPHYDesiredSZ;
 124     u32_t regPHYFindSig;
 125     u32_t regPHYAgcCtl1;
 126     u32_t regPHYSfcorr;
 127     u32_t regPHYSfcorrLow;
 128     u32_t regPHYTiming5;
 129     u32_t regPHYCckDetect;
 130
 131     u32_t eepromImage[1024];
 132     u32_t eepromImageIndex;
 133     u32_t eepromImageRdReq;
 134
 135     u8_t  halReInit;
 136
 137     u8_t  OpFlags;
 138
 139     u8_t tPow2xCck[4];
 140     u8_t tPow2x2g[4];
 141     u8_t tPow2x2g24HeavyClipOffset;
 142     u8_t tPow2x2gHt20[8];
 143     u8_t tPow2x2gHt40[8];
 144     u8_t tPow2x5g[4];
 145     u8_t tPow2x5gHt20[8];
 146     u8_t tPow2x5gHt40[8];
 147
 148     /* hwBBHeavyClip : used compatibility           */
 149     /*             0 : dongle not support.          */
 150     /*             !0: support heavy clip.          */
 151     u8_t hwBBHeavyClip;
 152     u8_t enableBBHeavyClip; /* 0=>force disable 1=>enable */
 153     u8_t doBBHeavyClip;     /* set 1 if heavy clip need by each frequency switch */
 154     u32_t setValueHeavyClip; /* save setting value for heavy clip when completed routine */
 155
 156     /*
 157      * Rxdata RSSI, EVM, Rate etc...
 158      */
 159     struct zsHalRxInfo halRxInfo;
 160
 161     u32_t usbSendBytes;
 162     u32_t usbAcSendBytes[4];
 163
 164     u16_t aggMaxDurationBE;
 165     u32_t aggPktNum;
 166
 167     u16_t txop[4];
 168     u16_t cwmin[4];
 169     u16_t cwmax[4];
 170     u8_t  strongRSSI;
 171     u8_t  rxStrongRSSI;
 172
 173     u8_t  slotType;  //0->20us, 1=>9us
 174
 175 #ifdef ZM_OTUS_RX_STREAM_MODE
 176     u16_t usbRxRemainLen;
 177     u16_t usbRxPktLen;
 178     u16_t usbRxPadLen;
 179     u16_t usbRxTransferLen;
 180     zbuf_t  *remainBuf;
 181 #endif
 182
 183     u8_t    dot11Mode;
 184
 185     u8_t    ibssBcnEnabled;
 186     u32_t   ibssBcnInterval;
 187
 188     // For re-issue the frequency change command
 189     u32_t   latestFrequency;
 190     u8_t    latestBw40;
 191     u8_t    latestExtOffset;
 192     u8_t    freqRetryCounter;
 193
 194     u8_t    recordFreqRetryCounter;
 195     u8_t    isSiteSurvey;
 196     u8_t    coldResetNeedFreq;
 197
 198     u64_t   camRollCallTable;
 199     u8_t    currentAckRtsTpc;
 200
 201     /* #1 Save the initial value of the related RIFS register settings */
 202     //u32_t   isInitialPhy;
 203     u32_t   initDesiredSigSize;
 204     u32_t   initAGC;
 205     u32_t   initAgcControl;
 206     u32_t   initSearchStartDelay;
 207     u32_t   initRIFSSearchParams;
 208     u32_t   initFastChannelChangeControl;
 209
 210     /* Dynamic SIFS for retransmission event */
 211     u8_t    retransmissionEvent;
 212     u8_t    latestSIFS;
 213 };
 214
 215 extern u32_t zfHpLoadEEPROMFromFW(zdev_t* dev);
 216
 217
 218 typedef u8_t A_UINT8;
 219 typedef s8_t A_INT8;
 220 typedef u16_t A_UINT16;
 221 typedef u32_t A_UINT32;
 222 #define __ATTRIB_PACK
 223
 224 #pragma pack (push, 1)
 225
 226 #define AR5416_EEP_VER               0xE
 227 #define AR5416_EEP_VER_MINOR_MASK    0xFFF
 228 #define AR5416_EEP_NO_BACK_VER       0x1
 229 #define AR5416_EEP_MINOR_VER_2       0x2  // Adds modal params txFrameToPaOn, txFrametoDataStart, ht40PowerInc
 230 #define AR5416_EEP_MINOR_VER_3       0x3  // Adds modal params bswAtten, bswMargin, swSettle and base OpFlags for HT20/40 Disable
 231
 232 // 16-bit offset location start of calibration struct
 233 #define AR5416_EEP_START_LOC         256
 234 #define AR5416_NUM_5G_CAL_PIERS      8
 235 #define AR5416_NUM_2G_CAL_PIERS      4
 236 #define AR5416_NUM_5G_20_TARGET_POWERS  8
 237 #define AR5416_NUM_5G_40_TARGET_POWERS  8
 238 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
 239 #define AR5416_NUM_2G_20_TARGET_POWERS  4
 240 #define AR5416_NUM_2G_40_TARGET_POWERS  4
 241 #define AR5416_NUM_CTLS              24
 242 #define AR5416_NUM_BAND_EDGES        8
 243 #define AR5416_NUM_PD_GAINS          4
 244 #define AR5416_PD_GAINS_IN_MASK      4
 245 #define AR5416_PD_GAIN_ICEPTS        5
 246 #define AR5416_EEPROM_MODAL_SPURS    5
 247 #define AR5416_MAX_RATE_POWER        63
 248 #define AR5416_NUM_PDADC_VALUES      128
 249 #define AR5416_NUM_RATES             16
 250 #define AR5416_BCHAN_UNUSED          0xFF
 251 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
 252 #define AR5416_OPFLAGS_11A           0x01
 253 #define AR5416_OPFLAGS_11G           0x02
 254 #define AR5416_OPFLAGS_5G_HT40       0x04
 255 #define AR5416_OPFLAGS_2G_HT40       0x08
 256 #define AR5416_OPFLAGS_5G_HT20       0x10
 257 #define AR5416_OPFLAGS_2G_HT20       0x20
 258 #define AR5416_EEPMISC_BIG_ENDIAN    0x01
 259 #define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
 260 #define AR5416_MAX_CHAINS            2
 261 #define AR5416_ANT_16S               25
 262
 263 #define AR5416_NUM_ANT_CHAIN_FIELDS     7
 264 #define AR5416_NUM_ANT_COMMON_FIELDS    4
 265 #define AR5416_SIZE_ANT_CHAIN_FIELD     3
 266 #define AR5416_SIZE_ANT_COMMON_FIELD    4
 267 #define AR5416_ANT_CHAIN_MASK           0x7
 268 #define AR5416_ANT_COMMON_MASK          0xf
 269 #define AR5416_CHAIN_0_IDX              0
 270 #define AR5416_CHAIN_1_IDX              1
 271 #define AR5416_CHAIN_2_IDX              2
 272
 273
 274 /* Capabilities Enum */
 275 typedef enum {
 276     EEPCAP_COMPRESS_DIS  = 0x0001,
 277     EEPCAP_AES_DIS       = 0x0002,
 278     EEPCAP_FASTFRAME_DIS = 0x0004,
 279     EEPCAP_BURST_DIS     = 0x0008,
 280     EEPCAP_MAXQCU_M      = 0x01F0,
 281     EEPCAP_MAXQCU_S      = 4,
 282     EEPCAP_HEAVY_CLIP_EN = 0x0200,
 283     EEPCAP_KC_ENTRIES_M  = 0xF000,
 284     EEPCAP_KC_ENTRIES_S  = 12,
 285 } EEPROM_CAPABILITIES;
 286
 287 typedef enum Ar5416_Rates {
 288     rate6mb,  rate9mb,  rate12mb, rate18mb,
 289     rate24mb, rate36mb, rate48mb, rate54mb,
 290     rate1l,   rate2l,   rate2s,   rate5_5l,
 291     rate5_5s, rate11l,  rate11s,  rateXr,
 292     rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
 293     rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
 294     rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
 295     rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
 296     rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
 297     Ar5416RateSize
 298 } AR5416_RATES;
 299
 300 typedef struct eepFlags {
 301     A_UINT8  opFlags;
 302     A_UINT8  eepMisc;
 303 } __ATTRIB_PACK EEP_FLAGS;
 304
 305 #define AR5416_CHECKSUM_LOCATION (AR5416_EEP_START_LOC + 1)
 306 typedef struct BaseEepHeader {
 307     A_UINT16  length;
 308     A_UINT16  checksum;
 309     A_UINT16  version;
 310     EEP_FLAGS opCapFlags;
 311     A_UINT16  regDmn[2];
 312     A_UINT8   macAddr[6];
 313     A_UINT8   rxMask;
 314     A_UINT8   txMask;
 315     A_UINT16  rfSilent;
 316     A_UINT16  blueToothOptions;
 317     A_UINT16  deviceCap;
 318     A_UINT32  binBuildNumber;
 319     A_UINT8   deviceType;
 320     A_UINT8   futureBase[33];
 321 } __ATTRIB_PACK BASE_EEP_HEADER; // 64 B
 322
 323 typedef struct spurChanStruct {
 324     A_UINT16 spurChan;
 325     A_UINT8  spurRangeLow;
 326     A_UINT8  spurRangeHigh;
 327 } __ATTRIB_PACK SPUR_CHAN;
 328
 329 typedef struct ModalEepHeader {
 330     A_UINT32  antCtrlChain[AR5416_MAX_CHAINS];       // 12
 331     A_UINT32  antCtrlCommon;                         // 4
 332     A_INT8    antennaGainCh[AR5416_MAX_CHAINS];      // 3
 333     A_UINT8   switchSettling;                        // 1
 334     A_UINT8   txRxAttenCh[AR5416_MAX_CHAINS];        // 3
 335     A_UINT8   rxTxMarginCh[AR5416_MAX_CHAINS];       // 3
 336     A_INT8    adcDesiredSize;                        // 1
 337     A_INT8    pgaDesiredSize;                        // 1
 338     A_UINT8   xlnaGainCh[AR5416_MAX_CHAINS];         // 3
 339     A_UINT8   txEndToXpaOff;                         // 1
 340     A_UINT8   txEndToRxOn;                           // 1
 341     A_UINT8   txFrameToXpaOn;                        // 1
 342     A_UINT8   thresh62;                              // 1
 343     A_INT8    noiseFloorThreshCh[AR5416_MAX_CHAINS]; // 3
 344     A_UINT8   xpdGain;                               // 1
 345     A_UINT8   xpd;                                   // 1
 346     A_INT8    iqCalICh[AR5416_MAX_CHAINS];           // 1
 347     A_INT8    iqCalQCh[AR5416_MAX_CHAINS];           // 1
 348     A_UINT8   pdGainOverlap;                         // 1
 349     A_UINT8   ob;                                    // 1
 350     A_UINT8   db;                                    // 1
 351     A_UINT8   xpaBiasLvl;                            // 1
 352     A_UINT8   pwrDecreaseFor2Chain;                  // 1
 353     A_UINT8   pwrDecreaseFor3Chain;                  // 1 -> 48 B
 354     A_UINT8   txFrameToDataStart;                    // 1
 355     A_UINT8   txFrameToPaOn;                         // 1
 356     A_UINT8   ht40PowerIncForPdadc;                  // 1
 357     A_UINT8   bswAtten[AR5416_MAX_CHAINS];           // 3
 358     A_UINT8   bswMargin[AR5416_MAX_CHAINS];          // 3
 359     A_UINT8   swSettleHt40;                          // 1
 360     A_UINT8   futureModal[22];                       //
 361     SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS];  // 20 B
 362 } __ATTRIB_PACK MODAL_EEP_HEADER;                    // == 100 B
 363
 364 typedef struct calDataPerFreq {
 365     A_UINT8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 366     A_UINT8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 367 } __ATTRIB_PACK CAL_DATA_PER_FREQ;
 368
 369 typedef struct CalTargetPowerLegacy {
 370     A_UINT8  bChannel;
 371     A_UINT8  tPow2x[4];
 372 } __ATTRIB_PACK CAL_TARGET_POWER_LEG;
 373
 374 typedef struct CalTargetPowerHt {
 375     A_UINT8  bChannel;
 376     A_UINT8  tPow2x[8];
 377 } __ATTRIB_PACK CAL_TARGET_POWER_HT;
 378
 379 #if defined(ARCH_BIG_ENDIAN) || defined(BIG_ENDIAN)
 380 typedef struct CalCtlEdges {
 381     A_UINT8  bChannel;
 382     A_UINT8  flag   :2,
 383              tPower :6;
 384 } __ATTRIB_PACK CAL_CTL_EDGES;
 385 #else
 386 typedef struct CalCtlEdges {
 387     A_UINT8  bChannel;
 388     A_UINT8  tPower :6,
 389              flag   :2;
 390 } __ATTRIB_PACK CAL_CTL_EDGES;
 391 #endif
 392
 393 typedef struct CalCtlData {
 394     CAL_CTL_EDGES  ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
 395 } __ATTRIB_PACK CAL_CTL_DATA;
 396
 397 typedef struct ar5416Eeprom {
 398     BASE_EEP_HEADER    baseEepHeader;         // 64 B
 399     A_UINT8   custData[64];                   // 64 B
 400     MODAL_EEP_HEADER   modalHeader[2];        // 200 B
 401     A_UINT8            calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
 402     A_UINT8            calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
 403     CAL_DATA_PER_FREQ  calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
 404     CAL_DATA_PER_FREQ  calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
 405     CAL_TARGET_POWER_LEG calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
 406     CAL_TARGET_POWER_HT  calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
 407     CAL_TARGET_POWER_HT  calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
 408     CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
 409     CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
 410     CAL_TARGET_POWER_HT  calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
 411     CAL_TARGET_POWER_HT  calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
 412     A_UINT8            ctlIndex[AR5416_NUM_CTLS];
 413     CAL_CTL_DATA       ctlData[AR5416_NUM_CTLS];
 414     A_UINT8            padding;
 415 } __ATTRIB_PACK AR5416_EEPROM;
 416
 417 #pragma pack (pop)
 418
 419 typedef enum ConformanceTestLimits {
 420     FCC        = 0x10,
 421     MKK        = 0x40,
 422     ETSI       = 0x30,
 423     SD_NO_CTL  = 0xE0,
 424     NO_CTL     = 0xFF,
 425     CTL_MODE_M = 0xF,
 426     CTL_11A    = 0,
 427     CTL_11B    = 1,
 428     CTL_11G    = 2,
 429     CTL_TURBO  = 3,
 430     CTL_108G   = 4,
 431     CTL_2GHT20 = 5,
 432     CTL_5GHT20 = 6,
 433     CTL_2GHT40 = 7,
 434     CTL_5GHT40 = 8,
 435 } ATH_CTLS;
 436
 437 #endif /* #ifndef _HPUSB_H */