kernel/2.6.29.6-aldebaran-rt/drivers/staging/comedi/drivers/s626.h

   1 /*
   2   comedi/drivers/s626.h
   3   Sensoray s626 Comedi driver, header file
   4
   5   COMEDI - Linux Control and Measurement Device Interface
   6   Copyright (C) 2000 David A. Schleef <ds@schleef.org>
   7
   8   Based on Sensoray Model 626 Linux driver Version 0.2
   9   Copyright (C) 2002-2004 Sensoray Co., Inc.
  10
  11   This program is free software; you can redistribute it and/or modify
  12   it under the terms of the GNU General Public License as published by
  13   the Free Software Foundation; either version 2 of the License, or
  14   (at your option) any later version.
  15
  16   This program is distributed in the hope that it will be useful,
  17   but WITHOUT ANY WARRANTY; without even the implied warranty of
  18   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19   GNU General Public License for more details.
  20
  21   You should have received a copy of the GNU General Public License
  22   along with this program; if not, write to the Free Software
  23   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24
  25 */
  26
  27 /*
  28   Driver: s626.o (s626.ko)
  29   Description: Sensoray 626 driver
  30   Devices: Sensoray s626
  31   Authors: Gianluca Palli <gpalli@deis.unibo.it>,
  32   Updated: Thu, 12 Jul 2005
  33   Status: experimental
  34
  35   Configuration Options:
  36   analog input:
  37    none
  38
  39   analog output:
  40    none
  41
  42   digital channel:
  43    s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
  44    supported configuration options:
  45    INSN_CONFIG_DIO_QUERY
  46    COMEDI_INPUT
  47    COMEDI_OUTPUT
  48
  49   encoder:
  50    Every channel must be configured before reading.
  51
  52    Example code
  53
  54    insn.insn=INSN_CONFIG;   //configuration instruction
  55    insn.n=1;                //number of operation (must be 1)
  56    insn.data=&initialvalue; //initial value loaded into encoder
  57                             //during configuration
  58    insn.subdev=5;           //encoder subdevice
  59    insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
  60                                                         //to configure
  61
  62    comedi_do_insn(cf,&insn); //executing configuration
  63 */
  64
  65 #ifdef _DEBUG_
  66 #define DEBUG(...);        rt_printk(__VA_ARGS__);
  67 #else
  68 #define DEBUG(...)
  69 #endif
  70
  71 #if !defined(TRUE)
  72 #define TRUE    (1)
  73 #endif
  74
  75 #if !defined(FALSE)
  76 #define FALSE   (0)
  77 #endif
  78
  79 #if !defined(EXTERN)
  80 #if defined(__cplusplus)
  81 #define EXTERN extern "C"
  82 #else
  83 #define EXTERN extern
  84 #endif
  85 #endif
  86
  87 #if !defined(INLINE)
  88 #define INLINE static __inline
  89 #endif
  90
  91 /////////////////////////////////////////////////////
  92 #include<linux/slab.h>
  93
  94 #define S626_SIZE 0x0200
  95 #define SIZEOF_ADDRESS_SPACE            0x0200
  96 #define DMABUF_SIZE                     4096    // 4k pages
  97
  98 #define S626_ADC_CHANNELS       16
  99 #define S626_DAC_CHANNELS       4
 100 #define S626_ENCODER_CHANNELS   6
 101 #define S626_DIO_CHANNELS       48
 102 #define S626_DIO_BANKS          3       // Number of DIO groups.
 103 #define S626_DIO_EXTCHANS       40      // Number of
 104                                         // extended-capability
 105                                         // DIO channels.
 106
 107 #define NUM_TRIMDACS    12      // Number of valid TrimDAC channels.
 108
 109 // PCI bus interface types.
 110 #define INTEL                           1       // Intel bus type.
 111 #define MOTOROLA                        2       // Motorola bus type.
 112
 113 //////////////////////////////////////////////////////////
 114
 115 //////////////////////////////////////////////////////////
 116 #define PLATFORM                INTEL   // *** SELECT PLATFORM TYPE ***
 117 //////////////////////////////////////////////////////////
 118
 119 #define RANGE_5V                0x10    // +/-5V range
 120 #define RANGE_10V               0x00    // +/-10V range
 121
 122 #define EOPL                    0x80    // End of ADC poll list marker.
 123 #define GSEL_BIPOLAR5V          0x00F0  // LP_GSEL setting for 5V bipolar range.
 124 #define GSEL_BIPOLAR10V         0x00A0  // LP_GSEL setting for 10V bipolar range.
 125
 126 // Error codes that must be visible to this base class.
 127 #define ERR_ILLEGAL_PARM        0x00010000      // Illegal function parameter value was specified.
 128 #define ERR_I2C                 0x00020000      // I2C error.
 129 #define ERR_COUNTERSETUP        0x00200000      // Illegal setup specified for counter channel.
 130 #define ERR_DEBI_TIMEOUT        0x00400000      // DEBI transfer timed out.
 131
 132 // Organization (physical order) and size (in DWORDs) of logical DMA buffers contained by ANA_DMABUF.
 133 #define ADC_DMABUF_DWORDS       40      // ADC DMA buffer must hold 16 samples, plus pre/post garbage samples.
 134 #define DAC_WDMABUF_DWORDS      1       // DAC output DMA buffer holds a single sample.
 135
 136 // All remaining space in 4KB DMA buffer is available for the RPS1 program.
 137
 138 // Address offsets, in DWORDS, from base of DMA buffer.
 139 #define DAC_WDMABUF_OS          ADC_DMABUF_DWORDS
 140
 141 // Interrupt enab bit in ISR and IER.
 142 #define IRQ_GPIO3               0x00000040      // IRQ enable for GPIO3.
 143 #define IRQ_RPS1                0x10000000
 144 #define ISR_AFOU                0x00000800      // Audio fifo
 145                                                 // under/overflow
 146                                                 // detected.
 147 #define IRQ_COINT1A             0x0400  // conter 1A overflow
 148                                                 // interrupt mask
 149 #define IRQ_COINT1B             0x0800  // conter 1B overflow
 150                                                 // interrupt mask
 151 #define IRQ_COINT2A             0x1000  // conter 2A overflow
 152                                                 // interrupt mask
 153 #define IRQ_COINT2B             0x2000  // conter 2B overflow
 154                                                 // interrupt mask
 155 #define IRQ_COINT3A             0x4000  // conter 3A overflow
 156                                                 // interrupt mask
 157 #define IRQ_COINT3B             0x8000  // conter 3B overflow
 158                                                 // interrupt mask
 159
 160 // RPS command codes.
 161 #define RPS_CLRSIGNAL           0x00000000      // CLEAR SIGNAL
 162 #define RPS_SETSIGNAL           0x10000000      // SET SIGNAL
 163 #define RPS_NOP                 0x00000000      // NOP
 164 #define RPS_PAUSE               0x20000000      // PAUSE
 165 #define RPS_UPLOAD              0x40000000      // UPLOAD
 166 #define RPS_JUMP                0x80000000      // JUMP
 167 #define RPS_LDREG               0x90000100      // LDREG (1 uint32_t only)
 168 #define RPS_STREG               0xA0000100      // STREG (1 uint32_t only)
 169 #define RPS_STOP                0x50000000      // STOP
 170 #define RPS_IRQ                 0x60000000      // IRQ
 171
 172 #define RPS_LOGICAL_OR          0x08000000      // Logical OR conditionals.
 173 #define RPS_INVERT              0x04000000      // Test for negated semaphores.
 174 #define RPS_DEBI                0x00000002      // DEBI done
 175
 176 #define RPS_SIG0                0x00200000      // RPS semaphore 0 (used by ADC).
 177 #define RPS_SIG1                0x00400000      // RPS semaphore 1 (used by DAC).
 178 #define RPS_SIG2                0x00800000      // RPS semaphore 2 (not used).
 179 #define RPS_GPIO2               0x00080000      // RPS GPIO2
 180 #define RPS_GPIO3               0x00100000      // RPS GPIO3
 181
 182 #define RPS_SIGADC              RPS_SIG0        // Trigger/status for ADC's RPS program.
 183 #define RPS_SIGDAC              RPS_SIG1        // Trigger/status for DAC's RPS program.
 184
 185 // RPS clock parameters.
 186 #define RPSCLK_SCALAR           8       // This is apparent ratio of PCI/RPS clks (undocumented!!).
 187 #define RPSCLK_PER_US           ( 33 / RPSCLK_SCALAR )  // Number of RPS clocks in one microsecond.
 188
 189 // Event counter source addresses.
 190 #define SBA_RPS_A0              0x27    // Time of RPS0 busy, in PCI clocks.
 191
 192 // GPIO constants.
 193 #define GPIO_BASE               0x10004000      // GPIO 0,2,3 = inputs, GPIO3 = IRQ; GPIO1 = out.
 194 #define GPIO1_LO                0x00000000      // GPIO1 set to LOW.
 195 #define GPIO1_HI                0x00001000      // GPIO1 set to HIGH.
 196
 197 // Primary Status Register (PSR) constants.
 198 #define PSR_DEBI_E              0x00040000      // DEBI event flag.
 199 #define PSR_DEBI_S              0x00080000      // DEBI status flag.
 200 #define PSR_A2_IN               0x00008000      // Audio output DMA2 protection address reached.
 201 #define PSR_AFOU                0x00000800      // Audio FIFO under/overflow detected.
 202 #define PSR_GPIO2               0x00000020      // GPIO2 input pin: 0=AdcBusy, 1=AdcIdle.
 203 #define PSR_EC0S                0x00000001      // Event counter 0 threshold reached.
 204
 205 // Secondary Status Register (SSR) constants.
 206 #define SSR_AF2_OUT             0x00000200      // Audio 2 output FIFO under/overflow detected.
 207
 208 // Master Control Register 1 (MC1) constants.
 209 #define MC1_SOFT_RESET          0x80000000      // Invoke 7146 soft reset.
 210 #define MC1_SHUTDOWN            0x3FFF0000      // Shut down all MC1-controlled enables.
 211
 212 #define MC1_ERPS1               0x2000  // enab/disable RPS task 1.
 213 #define MC1_ERPS0               0x1000  // enab/disable RPS task 0.
 214 #define MC1_DEBI                0x0800  // enab/disable DEBI pins.
 215 #define MC1_AUDIO               0x0200  // enab/disable audio port pins.
 216 #define MC1_I2C                 0x0100  // enab/disable I2C interface.
 217 #define MC1_A2OUT               0x0008  // enab/disable transfer on A2 out.
 218 #define MC1_A2IN                0x0004  // enab/disable transfer on A2 in.
 219 #define MC1_A1IN                0x0001  // enab/disable transfer on A1 in.
 220
 221 // Master Control Register 2 (MC2) constants.
 222 #define MC2_UPLD_DEBIq          0x00020002      // Upload DEBI registers.
 223 #define MC2_UPLD_IICq           0x00010001      // Upload I2C registers.
 224 #define MC2_RPSSIG2_ONq         0x20002000      // Assert RPS_SIG2.
 225 #define MC2_RPSSIG1_ONq         0x10001000      // Assert RPS_SIG1.
 226 #define MC2_RPSSIG0_ONq         0x08000800      // Assert RPS_SIG0.
 227 #define MC2_UPLD_DEBI_MASKq     0x00000002      // Upload DEBI mask.
 228 #define MC2_UPLD_IIC_MASKq      0x00000001      // Upload I2C mask.
 229 #define MC2_RPSSIG2_MASKq       0x00002000      // RPS_SIG2 bit mask.
 230 #define MC2_RPSSIG1_MASKq       0x00001000      // RPS_SIG1 bit mask.
 231 #define MC2_RPSSIG0_MASKq       0x00000800      // RPS_SIG0 bit mask.
 232
 233 #define MC2_DELAYTRIG_4USq      MC2_RPSSIG1_ON
 234 #define MC2_DELAYBUSY_4USq      MC2_RPSSIG1_MASK
 235
 236 #define MC2_DELAYTRIG_6USq      MC2_RPSSIG2_ON
 237 #define MC2_DELAYBUSY_6USq      MC2_RPSSIG2_MASK
 238
 239 #define MC2_UPLD_DEBI           0x0002  // Upload DEBI.
 240 #define MC2_UPLD_IIC            0x0001  // Upload I2C.
 241 #define MC2_RPSSIG2             0x2000  // RPS signal 2 (not used).
 242 #define MC2_RPSSIG1             0x1000  // RPS signal 1 (DAC RPS busy).
 243 #define MC2_RPSSIG0             0x0800  // RPS signal 0 (ADC RPS busy).
 244
 245 #define MC2_ADC_RPS             MC2_RPSSIG0     // ADC RPS busy.
 246 #define MC2_DAC_RPS             MC2_RPSSIG1     // DAC RPS busy.
 247
 248 ///////////////////oldies///////////
 249 #define MC2_UPLD_DEBIQ          0x00020002      // Upload DEBI registers.
 250 #define MC2_UPLD_IICQ           0x00010001      // Upload I2C registers.
 251 ////////////////////////////////////////
 252
 253 // PCI BUS (SAA7146) REGISTER ADDRESS OFFSETS ////////////////////////
 254 #define P_PCI_BT_A              0x004C  // Audio DMA
 255                                                 // burst/threshold
 256                                                 // control.
 257 #define P_DEBICFG               0x007C  // DEBI configuration.
 258 #define P_DEBICMD               0x0080  // DEBI command.
 259 #define P_DEBIPAGE              0x0084  // DEBI page.
 260 #define P_DEBIAD                0x0088  // DEBI target address.
 261 #define P_I2CCTRL               0x008C  // I2C control.
 262 #define P_I2CSTAT               0x0090  // I2C status.
 263 #define P_BASEA2_IN             0x00AC  // Audio input 2 base
 264                                                 // physical DMAbuf
 265                                                 // address.
 266 #define P_PROTA2_IN             0x00B0  // Audio input 2
 267                                                 // physical DMAbuf
 268                                                 // protection address.
 269 #define P_PAGEA2_IN             0x00B4  // Audio input 2
 270                                                 // paging attributes.
 271 #define P_BASEA2_OUT            0x00B8  // Audio output 2 base
 272                                                 // physical DMAbuf
 273                                                 // address.
 274 #define P_PROTA2_OUT            0x00BC  // Audio output 2
 275                                                 // physical DMAbuf
 276                                                 // protection address.
 277 #define P_PAGEA2_OUT            0x00C0  // Audio output 2
 278                                                 // paging attributes.
 279 #define P_RPSPAGE0              0x00C4  // RPS0 page.
 280 #define P_RPSPAGE1              0x00C8  // RPS1 page.
 281 #define P_RPS0_TOUT             0x00D4  // RPS0 time-out.
 282 #define P_RPS1_TOUT             0x00D8  // RPS1 time-out.
 283 #define P_IER                   0x00DC  // Interrupt enable.
 284 #define P_GPIO                  0x00E0  // General-purpose I/O.
 285 #define P_EC1SSR                0x00E4  // Event counter set 1
 286                                                 // source select.
 287 #define P_ECT1R                 0x00EC  // Event counter
 288                                                 // threshold set 1.
 289 #define P_ACON1                 0x00F4  // Audio control 1.
 290 #define P_ACON2                 0x00F8  // Audio control 2.
 291 #define P_MC1                   0x00FC  // Master control 1.
 292 #define P_MC2                   0x0100  // Master control 2.
 293 #define P_RPSADDR0              0x0104  // RPS0 instruction pointer.
 294 #define P_RPSADDR1              0x0108  // RPS1 instruction pointer.
 295 #define P_ISR                   0x010C  // Interrupt status.
 296 #define P_PSR                   0x0110  // Primary status.
 297 #define P_SSR                   0x0114  // Secondary status.
 298 #define P_EC1R                  0x0118  // Event counter set 1.
 299 #define P_ADP4                  0x0138  // Logical audio DMA
 300                                                 // pointer of audio
 301                                                 // input FIFO A2_IN.
 302 #define P_FB_BUFFER1            0x0144  // Audio feedback buffer 1.
 303 #define P_FB_BUFFER2            0x0148  // Audio feedback buffer 2.
 304 #define P_TSL1                  0x0180  // Audio time slot list 1.
 305 #define P_TSL2                  0x01C0  // Audio time slot list 2.
 306
 307 // LOCAL BUS (GATE ARRAY) REGISTER ADDRESS OFFSETS /////////////////
 308 // Analog I/O registers:
 309 #define LP_DACPOL               0x0082  //  Write DAC polarity.
 310 #define LP_GSEL                 0x0084  //  Write ADC gain.
 311 #define LP_ISEL                 0x0086  //  Write ADC channel select.
 312 // Digital I/O (write only):
 313 #define LP_WRINTSELA            0x0042  //  Write A interrupt enable.
 314 #define LP_WREDGSELA            0x0044  //  Write A edge selection.
 315 #define LP_WRCAPSELA            0x0046  //  Write A capture enable.
 316 #define LP_WRDOUTA              0x0048  //  Write A digital output.
 317 #define LP_WRINTSELB            0x0052  //  Write B interrupt enable.
 318 #define LP_WREDGSELB            0x0054  //  Write B edge selection.
 319 #define LP_WRCAPSELB            0x0056  //  Write B capture enable.
 320 #define LP_WRDOUTB              0x0058  //  Write B digital output.
 321 #define LP_WRINTSELC            0x0062  //  Write C interrupt enable.
 322 #define LP_WREDGSELC            0x0064  //  Write C edge selection.
 323 #define LP_WRCAPSELC            0x0066  //  Write C capture enable.
 324 #define LP_WRDOUTC              0x0068  //  Write C digital output.
 325
 326 // Digital I/O (read only):
 327 #define LP_RDDINA               0x0040  //  Read digital input.
 328 #define LP_RDCAPFLGA            0x0048  //  Read edges captured.
 329 #define LP_RDINTSELA            0x004A  //  Read interrupt
 330                                                 //  enable register.
 331 #define LP_RDEDGSELA            0x004C  //  Read edge
 332                                                 //  selection
 333                                                 //  register.
 334 #define LP_RDCAPSELA            0x004E  //  Read capture
 335                                                 //  enable register.
 336 #define LP_RDDINB               0x0050  //  Read digital input.
 337 #define LP_RDCAPFLGB            0x0058  //  Read edges captured.
 338 #define LP_RDINTSELB            0x005A  //  Read interrupt
 339                                                 //  enable register.
 340 #define LP_RDEDGSELB            0x005C  //  Read edge
 341                                                 //  selection
 342                                                 //  register.
 343 #define LP_RDCAPSELB            0x005E  //  Read capture
 344                                                 //  enable register.
 345 #define LP_RDDINC               0x0060  //  Read digital input.
 346 #define LP_RDCAPFLGC            0x0068  //  Read edges captured.
 347 #define LP_RDINTSELC            0x006A  //  Read interrupt
 348                                                 //  enable register.
 349 #define LP_RDEDGSELC            0x006C  //  Read edge
 350                                                 //  selection
 351                                                 //  register.
 352 #define LP_RDCAPSELC            0x006E  //  Read capture
 353                                                 //  enable register.
 354 // Counter Registers (read/write):
 355 #define LP_CR0A                 0x0000  //  0A setup register.
 356 #define LP_CR0B                 0x0002  //  0B setup register.
 357 #define LP_CR1A                 0x0004  //  1A setup register.
 358 #define LP_CR1B                 0x0006  //  1B setup register.
 359 #define LP_CR2A                 0x0008  //  2A setup register.
 360 #define LP_CR2B                 0x000A  //  2B setup register.
 361 // Counter PreLoad (write) and Latch (read) Registers:
 362 #define LP_CNTR0ALSW            0x000C  //  0A lsw.
 363 #define LP_CNTR0AMSW            0x000E  //  0A msw.
 364 #define LP_CNTR0BLSW            0x0010  //  0B lsw.
 365 #define LP_CNTR0BMSW            0x0012  //  0B msw.
 366 #define LP_CNTR1ALSW            0x0014  //  1A lsw.
 367 #define LP_CNTR1AMSW            0x0016  //  1A msw.
 368 #define LP_CNTR1BLSW            0x0018  //  1B lsw.
 369 #define LP_CNTR1BMSW            0x001A  //  1B msw.
 370 #define LP_CNTR2ALSW            0x001C  //  2A lsw.
 371 #define LP_CNTR2AMSW            0x001E  //  2A msw.
 372 #define LP_CNTR2BLSW            0x0020  //  2B lsw.
 373 #define LP_CNTR2BMSW            0x0022  //  2B msw.
 374 // Miscellaneous Registers (read/write):
 375 #define LP_MISC1                0x0088  //  Read/write Misc1.
 376 #define LP_WRMISC2              0x0090  //  Write Misc2.
 377 #define LP_RDMISC2              0x0082  //  Read Misc2.
 378
 379 // Bit masks for MISC1 register that are the same for reads and writes.
 380 #define MISC1_WENABLE           0x8000  // enab writes to
 381                                                 // MISC2 (except Clear
 382                                                 // Watchdog bit).
 383 #define MISC1_WDISABLE          0x0000  // Disable writes to MISC2.
 384 #define MISC1_EDCAP             0x1000  // enab edge capture
 385                                                 // on DIO chans
 386                                                 // specified by
 387                                                 // LP_WRCAPSELx.
 388 #define MISC1_NOEDCAP           0x0000  // Disable edge
 389                                                 // capture on
 390                                                 // specified DIO
 391                                                 // chans.
 392
 393 // Bit masks for MISC1 register reads.
 394 #define RDMISC1_WDTIMEOUT       0x4000  // Watchdog timer timed out.
 395
 396 // Bit masks for MISC2 register writes.
 397 #define WRMISC2_WDCLEAR         0x8000  // Reset watchdog
 398                                                 // timer to zero.
 399 #define WRMISC2_CHARGE_ENABLE   0x4000  // enab battery
 400                                                 // trickle charging.
 401
 402 // Bit masks for MISC2 register that are the same for reads and writes.
 403 #define MISC2_BATT_ENABLE       0x0008  // Backup battery enable.
 404 #define MISC2_WDENABLE          0x0004  // Watchdog timer enable.
 405 #define MISC2_WDPERIOD_MASK     0x0003  // Watchdog interval
 406                                                 // select mask.
 407
 408 // Bit masks for ACON1 register.
 409 #define A2_RUN                  0x40000000      // Run A2 based on TSL2.
 410 #define A1_RUN                  0x20000000      // Run A1 based on TSL1.
 411 #define A1_SWAP                 0x00200000      // Use big-endian for A1.
 412 #define A2_SWAP                 0x00100000      // Use big-endian for A2.
 413 #define WS_MODES                0x00019999      // WS0 = TSL1 trigger
 414                                                 // input, WS1-WS4 =
 415                                                 // CS* outputs.
 416
 417 #if PLATFORM == INTEL           // Base ACON1 config:
 418                                                 // always run A1 based
 419                                                 // on TSL1.
 420 #define ACON1_BASE              ( WS_MODES | A1_RUN )
 421 #elif PLATFORM == MOTOROLA
 422 #define ACON1_BASE              ( WS_MODES | A1_RUN | A1_SWAP | A2_SWAP )
 423 #endif
 424
 425 #define ACON1_ADCSTART          ACON1_BASE      // Start ADC: run A1
 426                                                 // based on TSL1.
 427 #define ACON1_DACSTART          ( ACON1_BASE | A2_RUN ) // Start
 428                                                         // transmit to
 429                                                         // DAC: run A2
 430                                                         // based on
 431                                                         // TSL2.
 432 #define ACON1_DACSTOP           ACON1_BASE      // Halt A2.
 433
 434 // Bit masks for ACON2 register.
 435 #define A1_CLKSRC_BCLK1         0x00000000      // A1 bit rate = BCLK1 (ADC).
 436 #define A2_CLKSRC_X1            0x00800000      // A2 bit rate = ACLK/1 (DACs).
 437 #define A2_CLKSRC_X2            0x00C00000      // A2 bit rate = ACLK/2 (DACs).
 438 #define A2_CLKSRC_X4            0x01400000      // A2 bit rate = ACLK/4 (DACs).
 439 #define INVERT_BCLK2            0x00100000      // Invert BCLK2 (DACs).
 440 #define BCLK2_OE                0x00040000      // enab BCLK2 (DACs).
 441 #define ACON2_XORMASK           0x000C0000      // XOR mask for ACON2
 442                                                 // active-low bits.
 443
 444 #define ACON2_INIT              ( ACON2_XORMASK ^ ( A1_CLKSRC_BCLK1 | A2_CLKSRC_X2 | INVERT_BCLK2 | BCLK2_OE ) )
 445
 446 // Bit masks for timeslot records.
 447 #define WS1                     0x40000000      // WS output to assert.
 448 #define WS2                     0x20000000
 449 #define WS3                     0x10000000
 450 #define WS4                     0x08000000
 451 #define RSD1                    0x01000000      // Shift A1 data in on SD1.
 452 #define SDW_A1                  0x00800000      // Store rcv'd char at
 453                                                 // next char slot of
 454                                                 // DWORD1 buffer.
 455 #define SIB_A1                  0x00400000      // Store rcv'd char at
 456                                                 // next char slot of
 457                                                 // FB1 buffer.
 458 #define SF_A1                   0x00200000      // Write unsigned long
 459                                                 // buffer to input
 460                                                 // FIFO.
 461
 462 //Select parallel-to-serial converter's data source:
 463 #define XFIFO_0                 0x00000000      //   Data fifo byte 0.
 464 #define XFIFO_1                 0x00000010      //   Data fifo byte 1.
 465 #define XFIFO_2                 0x00000020      //   Data fifo byte 2.
 466 #define XFIFO_3                 0x00000030      //   Data fifo byte 3.
 467 #define XFB0                    0x00000040      //   FB_BUFFER byte 0.
 468 #define XFB1                    0x00000050      //   FB_BUFFER byte 1.
 469 #define XFB2                    0x00000060      //   FB_BUFFER byte 2.
 470 #define XFB3                    0x00000070      //   FB_BUFFER byte 3.
 471 #define SIB_A2                  0x00000200      // Store next dword
 472                                                 // from A2's input
 473                                                 // shifter to FB2
 474                                                 // buffer.
 475 #define SF_A2                   0x00000100      // Store next dword
 476                                                 // from A2's input
 477                                                 // shifter to its
 478                                                 // input fifo.
 479 #define LF_A2                   0x00000080      // Load next dword
 480                                                 // from A2's output
 481                                                 // fifo into its
 482                                                 // output dword
 483                                                 // buffer.
 484 #define XSD2                    0x00000008      // Shift data out on SD2.
 485 #define RSD3                    0x00001800      // Shift data in on SD3.
 486 #define RSD2                    0x00001000      // Shift data in on SD2.
 487 #define LOW_A2                  0x00000002      // Drive last SD low
 488                                                 // for 7 clks, then
 489                                                 // tri-state.
 490 #define EOS                     0x00000001      // End of superframe.
 491
 492 //////////////////////
 493
 494 // I2C configuration constants.
 495 #define I2C_CLKSEL              0x0400  // I2C bit rate =
 496                                                 // PCIclk/480 = 68.75
 497                                                 // KHz.
 498 #define I2C_BITRATE             68.75   // I2C bus data bit
 499                                                 // rate (determined by
 500                                                 // I2C_CLKSEL) in KHz.
 501 #define I2C_WRTIME              15.0    // Worst case time,in
 502                                                 // msec, for EEPROM
 503                                                 // internal write op.
 504
 505 // I2C manifest constants.
 506
 507 // Max retries to wait for EEPROM write.
 508 #define I2C_RETRIES             ( I2C_WRTIME * I2C_BITRATE / 9.0 )
 509 #define I2C_ERR                 0x0002  // I2C control/status
 510                                                 // flag ERROR.
 511 #define I2C_BUSY                0x0001  // I2C control/status
 512                                                 // flag BUSY.
 513 #define I2C_ABORT               0x0080  // I2C status flag ABORT.
 514 #define I2C_ATTRSTART           0x3     // I2C attribute START.
 515 #define I2C_ATTRCONT            0x2     // I2C attribute CONT.
 516 #define I2C_ATTRSTOP            0x1     // I2C attribute STOP.
 517 #define I2C_ATTRNOP             0x0     // I2C attribute NOP.
 518
 519 // I2C read command  | EEPROM address.
 520 #define I2CR                    ( devpriv->I2CAdrs | 1 )
 521
 522 // I2C write command | EEPROM address.
 523 #define I2CW                    ( devpriv->I2CAdrs )
 524
 525 // Code macros used for constructing I2C command bytes.
 526 #define I2C_B2(ATTR,VAL)        ( ( (ATTR) << 6 ) | ( (VAL) << 24 ) )
 527 #define I2C_B1(ATTR,VAL)        ( ( (ATTR) << 4 ) | ( (VAL) << 16 ) )
 528 #define I2C_B0(ATTR,VAL)        ( ( (ATTR) << 2 ) | ( (VAL) <<  8 ) )
 529
 530 ////////////////////////////////////////////////////////
 531 //oldest
 532 #define P_DEBICFGq              0x007C  // DEBI configuration.
 533 #define P_DEBICMDq              0x0080  // DEBI command.
 534 #define P_DEBIPAGEq             0x0084  // DEBI page.
 535 #define P_DEBIADq               0x0088  // DEBI target address.
 536
 537 #define DEBI_CFG_TOQ            0x03C00000      // timeout (15 PCI cycles)
 538 #define DEBI_CFG_FASTQ          0x10000000      // fast mode enable
 539 #define DEBI_CFG_16Q            0x00080000      // 16-bit access enable
 540 #define DEBI_CFG_INCQ           0x00040000      // enable address increment
 541 #define DEBI_CFG_TIMEROFFQ      0x00010000      // disable timer
 542 #define DEBI_CMD_RDQ            0x00050000      // read immediate 2 bytes
 543 #define DEBI_CMD_WRQ            0x00040000      // write immediate 2 bytes
 544 #define DEBI_PAGE_DISABLEQ      0x00000000      // paging disable
 545
 546 ///////////////////////////////////////////
 547 // DEBI command constants.
 548 #define DEBI_CMD_SIZE16         ( 2 << 17 )     // Transfer size is
 549                                                 // always 2 bytes.
 550 #define DEBI_CMD_READ           0x00010000      // Read operation.
 551 #define DEBI_CMD_WRITE          0x00000000      // Write operation.
 552
 553 // Read immediate 2 bytes.
 554 #define DEBI_CMD_RDWORD         ( DEBI_CMD_READ  | DEBI_CMD_SIZE16 )
 555
 556 // Write immediate 2 bytes.
 557 #define DEBI_CMD_WRWORD         ( DEBI_CMD_WRITE | DEBI_CMD_SIZE16 )
 558
 559 // DEBI configuration constants.
 560 #define DEBI_CFG_XIRQ_EN        0x80000000      // enab external
 561                                                 // interrupt on GPIO3.
 562 #define DEBI_CFG_XRESUME        0x40000000      // Resume block
 563                                                 // transfer when XIRQ
 564                                                 // deasserted.
 565 #define DEBI_CFG_FAST           0x10000000      // Fast mode enable.
 566
 567 // 4-bit field that specifies DEBI timeout value in PCI clock cycles:
 568 #define DEBI_CFG_TOUT_BIT       22      //   Finish DEBI cycle after
 569                                         //   this many clocks.
 570
 571 // 2-bit field that specifies Endian byte lane steering:
 572 #define DEBI_CFG_SWAP_NONE      0x00000000      //   Straight - don't
 573                                                 //   swap any bytes
 574                                                 //   (Intel).
 575 #define DEBI_CFG_SWAP_2         0x00100000      //   2-byte swap (Motorola).
 576 #define DEBI_CFG_SWAP_4         0x00200000      //   4-byte swap.
 577 #define DEBI_CFG_16             0x00080000      // Slave is able to
 578                                                 // serve 16-bit
 579                                                 // cycles.
 580
 581 #define DEBI_CFG_SLAVE16        0x00080000      // Slave is able to
 582                                                 // serve 16-bit
 583                                                 // cycles.
 584 #define DEBI_CFG_INC            0x00040000      // enab address
 585                                                 // increment for block
 586                                                 // transfers.
 587 #define DEBI_CFG_INTEL          0x00020000      // Intel style local bus.
 588 #define DEBI_CFG_TIMEROFF       0x00010000      // Disable timer.
 589
 590 #if PLATFORM == INTEL
 591
 592 #define DEBI_TOUT               7       // Wait 7 PCI clocks
 593                                                 // (212 ns) before
 594                                                 // polling RDY.
 595
 596 // Intel byte lane steering (pass through all byte lanes).
 597 #define DEBI_SWAP               DEBI_CFG_SWAP_NONE
 598
 599 #elif PLATFORM == MOTOROLA
 600
 601 #define DEBI_TOUT               15      // Wait 15 PCI clocks (454 ns)
 602                                         // maximum before timing out.
 603 #define DEBI_SWAP               DEBI_CFG_SWAP_2 // Motorola byte lane steering.
 604
 605 #endif
 606
 607 // DEBI page table constants.
 608 #define DEBI_PAGE_DISABLE       0x00000000      // Paging disable.
 609
 610 ///////////////////EXTRA FROM OTHER SANSORAY  * .h////////
 611
 612 // LoadSrc values:
 613 #define LOADSRC_INDX            0       // Preload core in response to
 614                                         // Index.
 615 #define LOADSRC_OVER            1       // Preload core in response to
 616                                         // Overflow.
 617 #define LOADSRCB_OVERA          2       // Preload B core in response
 618                                         // to A Overflow.
 619 #define LOADSRC_NONE            3       // Never preload core.
 620
 621 // IntSrc values:
 622 #define INTSRC_NONE             0       // Interrupts disabled.
 623 #define INTSRC_OVER             1       // Interrupt on Overflow.
 624 #define INTSRC_INDX             2       // Interrupt on Index.
 625 #define INTSRC_BOTH             3       // Interrupt on Index or Overflow.
 626
 627 // LatchSrc values:
 628 #define LATCHSRC_AB_READ        0       // Latch on read.
 629 #define LATCHSRC_A_INDXA        1       // Latch A on A Index.
 630 #define LATCHSRC_B_INDXB        2       // Latch B on B Index.
 631 #define LATCHSRC_B_OVERA        3       // Latch B on A Overflow.
 632
 633 // IndxSrc values:
 634 #define INDXSRC_HARD            0       // Hardware or software index.
 635 #define INDXSRC_SOFT            1       // Software index only.
 636
 637 // IndxPol values:
 638 #define INDXPOL_POS             0       // Index input is active high.
 639 #define INDXPOL_NEG             1       // Index input is active low.
 640
 641 // ClkSrc values:
 642 #define CLKSRC_COUNTER          0       // Counter mode.
 643 #define CLKSRC_TIMER            2       // Timer mode.
 644 #define CLKSRC_EXTENDER         3       // Extender mode.
 645
 646 // ClkPol values:
 647 #define CLKPOL_POS              0       // Counter/Extender clock is
 648                                         // active high.
 649 #define CLKPOL_NEG              1       // Counter/Extender clock is
 650                                         // active low.
 651 #define CNTDIR_UP               0       // Timer counts up.
 652 #define CNTDIR_DOWN             1       // Timer counts down.
 653
 654 // ClkEnab values:
 655 #define CLKENAB_ALWAYS          0       // Clock always enabled.
 656 #define CLKENAB_INDEX           1       // Clock is enabled by index.
 657
 658 // ClkMult values:
 659 #define CLKMULT_4X              0       // 4x clock multiplier.
 660 #define CLKMULT_2X              1       // 2x clock multiplier.
 661 #define CLKMULT_1X              2       // 1x clock multiplier.
 662
 663 // Bit Field positions in COUNTER_SETUP structure:
 664 #define BF_LOADSRC              9       // Preload trigger.
 665 #define BF_INDXSRC              7       // Index source.
 666 #define BF_INDXPOL              6       // Index polarity.
 667 #define BF_CLKSRC               4       // Clock source.
 668 #define BF_CLKPOL               3       // Clock polarity/count direction.
 669 #define BF_CLKMULT              1       // Clock multiplier.
 670 #define BF_CLKENAB              0       // Clock enable.
 671
 672 // Enumerated counter operating modes specified by ClkSrc bit field in
 673 // a COUNTER_SETUP.
 674
 675 #define CLKSRC_COUNTER          0       // Counter: ENC_C clock, ENC_D
 676                                         // direction.
 677 #define CLKSRC_TIMER            2       // Timer: SYS_C clock,
 678                                         // direction specified by
 679                                         // ClkPol.
 680 #define CLKSRC_EXTENDER         3       // Extender: OVR_A clock,
 681                                         // ENC_D direction.
 682
 683 // Enumerated counter clock multipliers.
 684
 685 #define MULT_X0                 0x0003  // Supports no multipliers;
 686                                         // fixed physical multiplier =
 687                                         // 3.
 688 #define MULT_X1                 0x0002  // Supports multiplier x1;
 689                                         // fixed physical multiplier =
 690                                         // 2.
 691 #define MULT_X2                 0x0001  // Supports multipliers x1,
 692                                         // x2; physical multipliers =
 693                                         // 1 or 2.
 694 #define MULT_X4                 0x0000  // Supports multipliers x1,
 695                                         // x2, x4; physical
 696                                         // multipliers = 0, 1 or 2.
 697
 698 // Sanity-check limits for parameters.
 699
 700 #define NUM_COUNTERS            6       // Maximum valid counter
 701                                         // logical channel number.
 702 #define NUM_INTSOURCES          4
 703 #define NUM_LATCHSOURCES        4
 704 #define NUM_CLKMULTS            4
 705 #define NUM_CLKSOURCES          4
 706 #define NUM_CLKPOLS             2
 707 #define NUM_INDEXPOLS           2
 708 #define NUM_INDEXSOURCES        2
 709 #define NUM_LOADTRIGS           4
 710
 711 // Bit field positions in CRA and CRB counter control registers.
 712
 713 // Bit field positions in CRA:
 714 #define CRABIT_INDXSRC_B        14      //   B index source.
 715 #define CRABIT_CLKSRC_B         12      //   B clock source.
 716 #define CRABIT_INDXPOL_A        11      //   A index polarity.
 717 #define CRABIT_LOADSRC_A         9      //   A preload trigger.
 718 #define CRABIT_CLKMULT_A         7      //   A clock multiplier.
 719 #define CRABIT_INTSRC_A          5      //   A interrupt source.
 720 #define CRABIT_CLKPOL_A          4      //   A clock polarity.
 721 #define CRABIT_INDXSRC_A         2      //   A index source.
 722 #define CRABIT_CLKSRC_A          0      //   A clock source.
 723
 724 // Bit field positions in CRB:
 725 #define CRBBIT_INTRESETCMD      15      //   Interrupt reset command.
 726 #define CRBBIT_INTRESET_B       14      //   B interrupt reset enable.
 727 #define CRBBIT_INTRESET_A       13      //   A interrupt reset enable.
 728 #define CRBBIT_CLKENAB_A        12      //   A clock enable.
 729 #define CRBBIT_INTSRC_B         10      //   B interrupt source.
 730 #define CRBBIT_LATCHSRC          8      //   A/B latch source.
 731 #define CRBBIT_LOADSRC_B         6      //   B preload trigger.
 732 #define CRBBIT_CLKMULT_B         3      //   B clock multiplier.
 733 #define CRBBIT_CLKENAB_B         2      //   B clock enable.
 734 #define CRBBIT_INDXPOL_B         1      //   B index polarity.
 735 #define CRBBIT_CLKPOL_B          0      //   B clock polarity.
 736
 737 // Bit field masks for CRA and CRB.
 738
 739 #define CRAMSK_INDXSRC_B        ( (uint16_t)( 3 << CRABIT_INDXSRC_B) )
 740 #define CRAMSK_CLKSRC_B         ( (uint16_t)( 3 << CRABIT_CLKSRC_B) )
 741 #define CRAMSK_INDXPOL_A        ( (uint16_t)( 1 << CRABIT_INDXPOL_A) )
 742 #define CRAMSK_LOADSRC_A        ( (uint16_t)( 3 << CRABIT_LOADSRC_A) )
 743 #define CRAMSK_CLKMULT_A        ( (uint16_t)( 3 << CRABIT_CLKMULT_A) )
 744 #define CRAMSK_INTSRC_A         ( (uint16_t)( 3 << CRABIT_INTSRC_A) )
 745 #define CRAMSK_CLKPOL_A         ( (uint16_t)( 3 << CRABIT_CLKPOL_A) )
 746 #define CRAMSK_INDXSRC_A        ( (uint16_t)( 3 << CRABIT_INDXSRC_A) )
 747 #define CRAMSK_CLKSRC_A         ( (uint16_t)( 3 << CRABIT_CLKSRC_A) )
 748
 749 #define CRBMSK_INTRESETCMD      ( (uint16_t)( 1 << CRBBIT_INTRESETCMD) )
 750 #define CRBMSK_INTRESET_B       ( (uint16_t)( 1 << CRBBIT_INTRESET_B) )
 751 #define CRBMSK_INTRESET_A       ( (uint16_t)( 1 << CRBBIT_INTRESET_A) )
 752 #define CRBMSK_CLKENAB_A        ( (uint16_t)( 1 << CRBBIT_CLKENAB_A) )
 753 #define CRBMSK_INTSRC_B         ( (uint16_t)( 3 << CRBBIT_INTSRC_B) )
 754 #define CRBMSK_LATCHSRC         ( (uint16_t)( 3 << CRBBIT_LATCHSRC) )
 755 #define CRBMSK_LOADSRC_B        ( (uint16_t)( 3 << CRBBIT_LOADSRC_B) )
 756 #define CRBMSK_CLKMULT_B        ( (uint16_t)( 3 << CRBBIT_CLKMULT_B) )
 757 #define CRBMSK_CLKENAB_B        ( (uint16_t)( 1 << CRBBIT_CLKENAB_B) )
 758 #define CRBMSK_INDXPOL_B        ( (uint16_t)( 1 << CRBBIT_INDXPOL_B) )
 759 #define CRBMSK_CLKPOL_B         ( (uint16_t)( 1 << CRBBIT_CLKPOL_B) )
 760
 761 #define CRBMSK_INTCTRL          ( CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A | CRBMSK_INTRESET_B )  // Interrupt reset control bits.
 762
 763 // Bit field positions for standardized SETUP structure.
 764
 765 #define STDBIT_INTSRC           13
 766 #define STDBIT_LATCHSRC         11
 767 #define STDBIT_LOADSRC           9
 768 #define STDBIT_INDXSRC           7
 769 #define STDBIT_INDXPOL           6
 770 #define STDBIT_CLKSRC            4
 771 #define STDBIT_CLKPOL            3
 772 #define STDBIT_CLKMULT           1
 773 #define STDBIT_CLKENAB           0
 774
 775 // Bit field masks for standardized SETUP structure.
 776
 777 #define STDMSK_INTSRC           ( (uint16_t)( 3 << STDBIT_INTSRC   ) )
 778 #define STDMSK_LATCHSRC         ( (uint16_t)( 3 << STDBIT_LATCHSRC ) )
 779 #define STDMSK_LOADSRC          ( (uint16_t)( 3 << STDBIT_LOADSRC  ) )
 780 #define STDMSK_INDXSRC          ( (uint16_t)( 1 << STDBIT_INDXSRC  ) )
 781 #define STDMSK_INDXPOL          ( (uint16_t)( 1 << STDBIT_INDXPOL  ) )
 782 #define STDMSK_CLKSRC           ( (uint16_t)( 3 << STDBIT_CLKSRC   ) )
 783 #define STDMSK_CLKPOL           ( (uint16_t)( 1 << STDBIT_CLKPOL   ) )
 784 #define STDMSK_CLKMULT          ( (uint16_t)( 3 << STDBIT_CLKMULT  ) )
 785 #define STDMSK_CLKENAB          ( (uint16_t)( 1 << STDBIT_CLKENAB  ) )
 786
 787 //////////////////////////////////////////////////////////
 788
 789 /* typedef struct indexCounter */
 790 /* { */
 791 /*   unsigned int ao; */
 792 /*   unsigned int ai; */
 793 /*   unsigned int digout; */
 794 /*   unsigned int digin; */
 795 /*   unsigned int enc; */
 796 /* }CallCounter; */
 797
 798 typedef struct bufferDMA {
 799         dma_addr_t PhysicalBase;
 800         void *LogicalBase;
 801         uint32_t DMAHandle;
 802 } DMABUF;