kernel/2.6.29.6-aldebaran-rt/drivers/staging/agnx/xmit.h

   1 #ifndef AGNX_XMIT_H_
   2 #define AGNX_XMIT_H_
   3
   4 #include <net/mac80211.h>
   5
   6 struct agnx_priv;
   7
   8 static inline u32 agnx_set_bits(u32 mask, u8 shift, u32 value)
   9 {
  10         return (value << shift) & mask;
  11 }
  12
  13 static inline u32 agnx_get_bits(u32 mask, u8 shift, u32 value)
  14 {
  15         return (value & mask) >> shift;
  16 }
  17
  18
  19 struct agnx_rx {
  20         __be16 rx_packet_duration; /*  RX Packet Duration */
  21         __be16 replay_cnt;      /* Replay Count */
  22 } __attribute__((__packed__));
  23
  24
  25 struct agnx_tx {
  26         u8 long_retry_limit; /* Long Retry Limit */
  27         u8 short_retry_limit; /* Short Retry Limit */
  28         u8 long_retry_cnt;      /* Long Retry Count */
  29         u8 short_retry_cnt; /* Short Retry Count */
  30 } __attribute__((__packed__));
  31
  32
  33 /* Copy from bcm43xx */
  34 #define P4D_BYT3S(magic, nr_bytes)      u8 __p4dding##magic[nr_bytes]
  35 #define P4D_BYTES(line, nr_bytes)       P4D_BYT3S(line, nr_bytes)
  36 #define PAD_BYTES(nr_bytes)             P4D_BYTES(__LINE__, nr_bytes)
  37
  38 #define P4D_BIT3S(magic, nr_bits)       __be32 __padding##magic:nr_bits
  39 #define P4D_BITS(line, nr_bits)         P4D_BIT3S(line, nr_bits)
  40 #define PAD_BITS(nr_bits)               P4D_BITS(__LINE__, nr_bits)
  41
  42
  43 struct agnx_hdr {
  44         __be32 reg0;
  45 #define RTS                     0x80000000 /* RTS */
  46 #define RTS_SHIFT               31
  47 #define MULTICAST               0x40000000 /* multicast */
  48 #define MULTICAST_SHIFT         30
  49 #define ACK                     0x30000000 /* ACK */
  50 #define ACK_SHIFT               28
  51 #define TM                      0x08000000 /* TM */
  52 #define TM_SHIFT                27
  53 #define RELAY                   0x04000000 /* Relay */
  54 #define RELAY_SHIFT             26
  55 /*      PAD_BITS(4); */
  56 #define REVISED_FCS             0x00380000 /* revised FCS */
  57 #define REVISED_FCS_SHIFT       19
  58 #define NEXT_BUFFER_ADDR        0x0007FFFF /* Next Buffer Address */
  59 #define NEXT_BUFFER_ADDR_SHIFT  0
  60
  61         __be32 reg1;
  62 #define MAC_HDR_LEN             0xFC000000 /* MAC Header Length  */
  63 #define MAC_HDR_LEN_SHIFT       26
  64 #define DURATION_OVERIDE        0x02000000 /* Duration Override */
  65 #define DURATION_OVERIDE_SHIFT  25
  66 #define PHY_HDR_OVERIDE         0x01000000 /* PHY Header Override */
  67 #define PHY_HDR_OVERIDE_SHIFT   24
  68 #define CRC_FAIL                0x00800000 /* CRC fail */
  69 #define CRC_FAIL_SHIFT          23
  70 /*      PAD_BITS(1); */
  71 #define SEQUENCE_NUMBER         0x00200000 /* Sequence Number */
  72 #define SEQUENCE_NUMBER_SHIFT   21
  73 /*      PAD_BITS(2); */
  74 #define BUFF_HEAD_ADDR          0x0007FFFF /* Buffer Head Address */
  75 #define BUFF_HEAD_ADDR_SHIFT    0
  76
  77         __be32 reg2;
  78 #define PDU_COUNT               0xFC000000 /* PDU Count */
  79 #define PDU_COUNT_SHIFT         26
  80 /*      PAD_BITS(3); */
  81 #define WEP_KEY                 0x00600000 /* WEP Key # */
  82 #define WEP_KEY_SHIFT           21
  83 #define USES_WEP_KEY            0x00100000 /* Uses WEP Key */
  84 #define USES_WEP_KEY_SHIFT      20
  85 #define KEEP_ALIVE              0x00080000 /* Keep alive */
  86 #define KEEP_ALIVE_SHIFT        19
  87 #define BUFF_TAIL_ADDR          0x0007FFFF /* Buffer Tail Address */
  88 #define BUFF_TAIL_ADDR_SHIFT    0
  89
  90         __be32 reg3;
  91 #define CTS_11G                 0x80000000      /* CTS in 11g */
  92 #define CTS_11G_SHIFT           31
  93 #define RTS_11G                 0x40000000      /* RTS in 11g */
  94 #define RTS_11G_SHIFT           30
  95 /* PAD_BITS(2); */
  96 #define FRAG_SIZE               0x0FFF0000      /* fragment size */
  97 #define FRAG_SIZE_SHIFT         16
  98 #define PAYLOAD_LEN             0x0000FFF0      /* payload length */
  99 #define PAYLOAD_LEN_SHIFT       4
 100 #define FRAG_NUM                0x0000000F      /* number of frags */
 101 #define FRAG_NUM_SHIFT          0
 102
 103         __be32 reg4;
 104 /*      PAD_BITS(4); */
 105 #define RELAY_STAID             0x0FFF0000 /* relayStald */
 106 #define RELAY_STAID_SHIFT       16
 107 #define STATION_ID              0x0000FFF0 /* Station ID */
 108 #define STATION_ID_SHIFT        4
 109 #define WORKQUEUE_ID            0x0000000F /* Workqueue ID */
 110 #define WORKQUEUE_ID_SHIFT      0
 111
 112         /* FIXME this register maybe is LE? */
 113         __be32 reg5;
 114 /*      PAD_BITS(4); */
 115 #define ROUTE_HOST              0x0F000000
 116 #define ROUTE_HOST_SHIFT        24
 117 #define ROUTE_CARD_CPU          0x00F00000
 118 #define ROUTE_CARD_CPU_SHIFT    20
 119 #define ROUTE_ENCRYPTION        0x000F0000
 120 #define ROUTE_ENCRYPTION_SHIFT  16
 121 #define ROUTE_TX                0x0000F000
 122 #define ROUTE_TX_SHIFT          12
 123 #define ROUTE_RX1               0x00000F00
 124 #define ROUTE_RX1_SHIFT         8
 125 #define ROUTE_RX2               0x000000F0
 126 #define ROUTE_RX2_SHIFT         4
 127 #define ROUTE_COMPRESSION       0x0000000F
 128 #define ROUTE_COMPRESSION_SHIFT 0
 129
 130         __be32 _11g0;                   /* 11g */
 131         __be32 _11g1;                   /* 11g */
 132         __be32 _11b0;                   /* 11b */
 133         __be32 _11b1;                   /* 11b */
 134         u8 mac_hdr[32];                 /* MAC header */
 135
 136         __be16 rts_duration;            /* RTS duration */
 137         __be16 last_duration;           /* Last duration */
 138         __be16 sec_last_duration;       /* Second to Last duration */
 139         __be16 other_duration;          /* Other duration */
 140         __be16 tx_last_duration;        /* TX Last duration */
 141         __be16 tx_other_duration;       /* TX Other Duration */
 142         __be16 last_11g_len;            /* Length of last 11g */
 143         __be16 other_11g_len;           /* Lenght of other 11g */
 144
 145         __be16 last_11b_len;            /* Length of last 11b */
 146         __be16 other_11b_len;           /* Lenght of other 11b */
 147
 148
 149         __be16 reg6;
 150 #define MBF                     0xF000 /* mbf */
 151 #define MBF_SHIFT               12
 152 #define RSVD4                   0x0FFF /* rsvd4 */
 153 #define RSVD4_SHIFT             0
 154
 155         __be16 rx_frag_stat;    /* RX fragmentation status */
 156
 157         __be32 time_stamp;      /* TimeStamp */
 158         __be32 phy_stats_hi;    /* PHY stats hi */
 159         __be32 phy_stats_lo;    /* PHY stats lo */
 160         __be32 mic_key0;        /* MIC key 0 */
 161         __be32 mic_key1;        /* MIC key 1 */
 162
 163         union {                 /* RX/TX Union */
 164                 struct agnx_rx rx;
 165                 struct agnx_tx tx;
 166         };
 167
 168         u8 rx_channel;          /* Recieve Channel */
 169         PAD_BYTES(3);
 170
 171         u8 reserved[4];
 172 } __attribute__((__packed__));
 173
 174
 175 struct agnx_desc {
 176 #define PACKET_LEN              0xFFF00000
 177 #define PACKET_LEN_SHIFT        20
 178 /* ------------------------------------------------ */
 179 #define FIRST_PACKET_MASK       0x00080000
 180 #define FIRST_PACKET_MASK_SHIFT 19
 181 #define FIRST_RESERV2           0x00040000
 182 #define FIRST_RESERV2_SHIFT     18
 183 #define FIRST_TKIP_ERROR        0x00020000
 184 #define FIRST_TKIP_ERROR_SHIFT  17
 185 #define FIRST_TKIP_PACKET       0x00010000
 186 #define FIRST_TKIP_PACKET_SHIFT 16
 187 #define FIRST_RESERV1           0x0000F000
 188 #define FIRST_RESERV1_SHIFT     12
 189 #define FIRST_FRAG_LEN          0x00000FF8
 190 #define FIRST_FRAG_LEN_SHIFT    3
 191 /* ------------------------------------------------ */
 192 #define SUB_RESERV2             0x000c0000
 193 #define SUB_RESERV2_SHIFT       18
 194 #define SUB_TKIP_ERROR          0x00020000
 195 #define SUB_TKIP_ERROR_SHIFT    17
 196 #define SUB_TKIP_PACKET         0x00010000
 197 #define SUB_TKIP_PACKET_SHIFT   16
 198 #define SUB_RESERV1             0x00008000
 199 #define SUB_RESERV1_SHIFT       15
 200 #define SUB_FRAG_LEN            0x00007FF8
 201 #define SUB_FRAG_LEN_SHIFT      3
 202 /* ------------------------------------------------ */
 203 #define FIRST_FRAG              0x00000004
 204 #define FIRST_FRAG_SHIFT        2
 205 #define LAST_FRAG               0x00000002
 206 #define LAST_FRAG_SHIFT         1
 207 #define OWNER                   0x00000001
 208 #define OWNER_SHIFT             0
 209         __be32 frag;
 210         __be32 dma_addr;
 211 } __attribute__((__packed__));
 212
 213 enum {HEADER, PACKET};
 214
 215 struct agnx_info {
 216         struct sk_buff *skb;
 217         dma_addr_t mapping;
 218         u32 dma_len;            /* dma buffer len  */
 219         /* Below fields only usful for tx */
 220         u32 hdr_len;            /* ieee80211 header length */
 221         unsigned int type;
 222         struct ieee80211_tx_info *txi;
 223         struct ieee80211_hdr hdr;
 224 };
 225
 226
 227 struct agnx_ring {
 228         struct agnx_desc *desc;
 229         dma_addr_t dma;
 230         struct agnx_info *info;
 231         /* Will lead to overflow when sent packet number enough? */
 232         unsigned int idx;
 233         unsigned int idx_sent;          /* only usful for txd and txm */
 234         unsigned int size;
 235 };
 236
 237 #define AGNX_RX_RING_SIZE       128
 238 #define AGNX_TXD_RING_SIZE      256
 239 #define AGNX_TXM_RING_SIZE      128
 240
 241 void disable_rx_interrupt(struct agnx_priv *priv);
 242 void enable_rx_interrupt(struct agnx_priv *priv);
 243 int fill_rings(struct agnx_priv *priv);
 244 void unfill_rings(struct agnx_priv *priv);
 245 void handle_rx_irq(struct agnx_priv *priv);
 246 void handle_txd_irq(struct agnx_priv *priv);
 247 void handle_txm_irq(struct agnx_priv *priv);
 248 void handle_other_irq(struct agnx_priv *priv);
 249 int _agnx_tx(struct agnx_priv *priv, struct sk_buff *skb);
 250 #endif /* AGNX_XMIT_H_ */