?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / ssb / main.c
blob65a1ed951a1daa80abe1c9ac2b091af8664b38ad
1 /*
2 * Sonics Silicon Backplane
3 * Subsystem core
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11 #include "ssb_private.h"
12
13 #include <linux/delay.h>
14 #include <linux/io.h>
15 #include <linux/ssb/ssb.h>
16 #include <linux/ssb/ssb_regs.h>
17 #include <linux/ssb/ssb_driver_gige.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/pci.h>
20
21 #include <pcmcia/cs_types.h>
22 #include <pcmcia/cs.h>
23 #include <pcmcia/cistpl.h>
24 #include <pcmcia/ds.h>
25
26
27 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
28 MODULE_LICENSE("GPL");
29
30
31 /* Temporary list of yet-to-be-attached buses */
32 static LIST_HEAD(attach_queue);
33 /* List if running buses */
34 static LIST_HEAD(buses);
35 /* Software ID counter */
36 static unsigned int next_busnumber;
37 /* buses_mutes locks the two buslists and the next_busnumber.
38 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
39 static DEFINE_MUTEX(buses_mutex);
40
41 /* There are differences in the codeflow, if the bus is
42 * initialized from early boot, as various needed services
43 * are not available early. This is a mechanism to delay
44 * these initializations to after early boot has finished.
45 * It's also used to avoid mutex locking, as that's not
46 * available and needed early. */
47 static bool ssb_is_early_boot = 1;
48
49 static void ssb_buses_lock(void);
50 static void ssb_buses_unlock(void);
51
52
53 #ifdef CONFIG_SSB_PCIHOST
54 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
55 {
56 struct ssb_bus *bus;
57
58 ssb_buses_lock();
59 list_for_each_entry(bus, &buses, list) {
60 if (bus->bustype == SSB_BUSTYPE_PCI &&
61 bus->host_pci == pdev)
62 goto found;
63 }
64 bus = NULL;
65 found:
66 ssb_buses_unlock();
67
68 return bus;
69 }
70 #endif /* CONFIG_SSB_PCIHOST */
71
72 #ifdef CONFIG_SSB_PCMCIAHOST
73 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
74 {
75 struct ssb_bus *bus;
76
77 ssb_buses_lock();
78 list_for_each_entry(bus, &buses, list) {
79 if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
80 bus->host_pcmcia == pdev)
81 goto found;
82 }
83 bus = NULL;
84 found:
85 ssb_buses_unlock();
86
87 return bus;
88 }
89 #endif /* CONFIG_SSB_PCMCIAHOST */
90
91 int ssb_for_each_bus_call(unsigned long data,
92 int (*func)(struct ssb_bus *bus, unsigned long data))
93 {
94 struct ssb_bus *bus;
95 int res;
96
97 ssb_buses_lock();
98 list_for_each_entry(bus, &buses, list) {
99 res = func(bus, data);
100 if (res >= 0) {
101 ssb_buses_unlock();
102 return res;
103 }
104 }
105 ssb_buses_unlock();
106
107 return -ENODEV;
108 }
109
110 static struct ssb_device *ssb_device_get(struct ssb_device *dev)
111 {
112 if (dev)
113 get_device(dev->dev);
114 return dev;
115 }
116
117 static void ssb_device_put(struct ssb_device *dev)
118 {
119 if (dev)
120 put_device(dev->dev);
121 }
122
123 static int ssb_device_resume(struct device *dev)
124 {
125 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
126 struct ssb_driver *ssb_drv;
127 int err = 0;
128
129 if (dev->driver) {
130 ssb_drv = drv_to_ssb_drv(dev->driver);
131 if (ssb_drv && ssb_drv->resume)
132 err = ssb_drv->resume(ssb_dev);
133 if (err)
134 goto out;
135 }
136 out:
137 return err;
138 }
139
140 static int ssb_device_suspend(struct device *dev, pm_message_t state)
141 {
142 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
143 struct ssb_driver *ssb_drv;
144 int err = 0;
145
146 if (dev->driver) {
147 ssb_drv = drv_to_ssb_drv(dev->driver);
148 if (ssb_drv && ssb_drv->suspend)
149 err = ssb_drv->suspend(ssb_dev, state);
150 if (err)
151 goto out;
152 }
153 out:
154 return err;
155 }
156
157 int ssb_bus_resume(struct ssb_bus *bus)
158 {
159 int err;
160
161 /* Reset HW state information in memory, so that HW is
162 * completely reinitialized. */
163 bus->mapped_device = NULL;
164 #ifdef CONFIG_SSB_DRIVER_PCICORE
165 bus->pcicore.setup_done = 0;
166 #endif
167
168 err = ssb_bus_powerup(bus, 0);
169 if (err)
170 return err;
171 err = ssb_pcmcia_hardware_setup(bus);
172 if (err) {
173 ssb_bus_may_powerdown(bus);
174 return err;
175 }
176 ssb_chipco_resume(&bus->chipco);
177 ssb_bus_may_powerdown(bus);
178
179 return 0;
180 }
181 EXPORT_SYMBOL(ssb_bus_resume);
182
183 int ssb_bus_suspend(struct ssb_bus *bus)
184 {
185 ssb_chipco_suspend(&bus->chipco);
186 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
187
188 return 0;
189 }
190 EXPORT_SYMBOL(ssb_bus_suspend);
191
192 #ifdef CONFIG_SSB_SPROM
193 int ssb_devices_freeze(struct ssb_bus *bus)
194 {
195 struct ssb_device *dev;
196 struct ssb_driver *drv;
197 int err = 0;
198 int i;
199 pm_message_t state = PMSG_FREEZE;
200
201 /* First check that we are capable to freeze all devices. */
202 for (i = 0; i < bus->nr_devices; i++) {
203 dev = &(bus->devices[i]);
204 if (!dev->dev ||
205 !dev->dev->driver ||
206 !device_is_registered(dev->dev))
207 continue;
208 drv = drv_to_ssb_drv(dev->dev->driver);
209 if (!drv)
210 continue;
211 if (!drv->suspend) {
212 /* Nope, can't suspend this one. */
213 return -EOPNOTSUPP;
214 }
215 }
216 /* Now suspend all devices */
217 for (i = 0; i < bus->nr_devices; i++) {
218 dev = &(bus->devices[i]);
219 if (!dev->dev ||
220 !dev->dev->driver ||
221 !device_is_registered(dev->dev))
222 continue;
223 drv = drv_to_ssb_drv(dev->dev->driver);
224 if (!drv)
225 continue;
226 err = drv->suspend(dev, state);
227 if (err) {
228 ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
229 dev_name(dev->dev));
230 goto err_unwind;
231 }
232 }
233
234 return 0;
235 err_unwind:
236 for (i--; i >= 0; i--) {
237 dev = &(bus->devices[i]);
238 if (!dev->dev ||
239 !dev->dev->driver ||
240 !device_is_registered(dev->dev))
241 continue;
242 drv = drv_to_ssb_drv(dev->dev->driver);
243 if (!drv)
244 continue;
245 if (drv->resume)
246 drv->resume(dev);
247 }
248 return err;
249 }
250
251 int ssb_devices_thaw(struct ssb_bus *bus)
252 {
253 struct ssb_device *dev;
254 struct ssb_driver *drv;
255 int err;
256 int i;
257
258 for (i = 0; i < bus->nr_devices; i++) {
259 dev = &(bus->devices[i]);
260 if (!dev->dev ||
261 !dev->dev->driver ||
262 !device_is_registered(dev->dev))
263 continue;
264 drv = drv_to_ssb_drv(dev->dev->driver);
265 if (!drv)
266 continue;
267 if (SSB_WARN_ON(!drv->resume))
268 continue;
269 err = drv->resume(dev);
270 if (err) {
271 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
272 dev_name(dev->dev));
273 }
274 }
275
276 return 0;
277 }
278 #endif /* CONFIG_SSB_SPROM */
279
280 static void ssb_device_shutdown(struct device *dev)
281 {
282 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
283 struct ssb_driver *ssb_drv;
284
285 if (!dev->driver)
286 return;
287 ssb_drv = drv_to_ssb_drv(dev->driver);
288 if (ssb_drv && ssb_drv->shutdown)
289 ssb_drv->shutdown(ssb_dev);
290 }
291
292 static int ssb_device_remove(struct device *dev)
293 {
294 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
295 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
296
297 if (ssb_drv && ssb_drv->remove)
298 ssb_drv->remove(ssb_dev);
299 ssb_device_put(ssb_dev);
300
301 return 0;
302 }
303
304 static int ssb_device_probe(struct device *dev)
305 {
306 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
307 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
308 int err = 0;
309
310 ssb_device_get(ssb_dev);
311 if (ssb_drv && ssb_drv->probe)
312 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
313 if (err)
314 ssb_device_put(ssb_dev);
315
316 return err;
317 }
318
319 static int ssb_match_devid(const struct ssb_device_id *tabid,
320 const struct ssb_device_id *devid)
321 {
322 if ((tabid->vendor != devid->vendor) &&
323 tabid->vendor != SSB_ANY_VENDOR)
324 return 0;
325 if ((tabid->coreid != devid->coreid) &&
326 tabid->coreid != SSB_ANY_ID)
327 return 0;
328 if ((tabid->revision != devid->revision) &&
329 tabid->revision != SSB_ANY_REV)
330 return 0;
331 return 1;
332 }
333
334 static int ssb_bus_match(struct device *dev, struct device_driver *drv)
335 {
336 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
337 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
338 const struct ssb_device_id *id;
339
340 for (id = ssb_drv->id_table;
341 id->vendor || id->coreid || id->revision;
342 id++) {
343 if (ssb_match_devid(id, &ssb_dev->id))
344 return 1; /* found */
345 }
346
347 return 0;
348 }
349
350 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
351 {
352 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
353
354 if (!dev)
355 return -ENODEV;
356
357 return add_uevent_var(env,
358 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
359 ssb_dev->id.vendor, ssb_dev->id.coreid,
360 ssb_dev->id.revision);
361 }
362
363 static struct bus_type ssb_bustype = {
364 .name = "ssb",
365 .match = ssb_bus_match,
366 .probe = ssb_device_probe,
367 .remove = ssb_device_remove,
368 .shutdown = ssb_device_shutdown,
369 .suspend = ssb_device_suspend,
370 .resume = ssb_device_resume,
371 .uevent = ssb_device_uevent,
372 };
373
374 static void ssb_buses_lock(void)
375 {
376 /* See the comment at the ssb_is_early_boot definition */
377 if (!ssb_is_early_boot)
378 mutex_lock(&buses_mutex);
379 }
380
381 static void ssb_buses_unlock(void)
382 {
383 /* See the comment at the ssb_is_early_boot definition */
384 if (!ssb_is_early_boot)
385 mutex_unlock(&buses_mutex);
386 }
387
388 static void ssb_devices_unregister(struct ssb_bus *bus)
389 {
390 struct ssb_device *sdev;
391 int i;
392
393 for (i = bus->nr_devices - 1; i >= 0; i--) {
394 sdev = &(bus->devices[i]);
395 if (sdev->dev)
396 device_unregister(sdev->dev);
397 }
398 }
399
400 void ssb_bus_unregister(struct ssb_bus *bus)
401 {
402 ssb_buses_lock();
403 ssb_devices_unregister(bus);
404 list_del(&bus->list);
405 ssb_buses_unlock();
406
407 ssb_pcmcia_exit(bus);
408 ssb_pci_exit(bus);
409 ssb_iounmap(bus);
410 }
411 EXPORT_SYMBOL(ssb_bus_unregister);
412
413 static void ssb_release_dev(struct device *dev)
414 {
415 struct __ssb_dev_wrapper *devwrap;
416
417 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
418 kfree(devwrap);
419 }
420
421 static int ssb_devices_register(struct ssb_bus *bus)
422 {
423 struct ssb_device *sdev;
424 struct device *dev;
425 struct __ssb_dev_wrapper *devwrap;
426 int i, err = 0;
427 int dev_idx = 0;
428
429 for (i = 0; i < bus->nr_devices; i++) {
430 sdev = &(bus->devices[i]);
431
432 /* We don't register SSB-system devices to the kernel,
433 * as the drivers for them are built into SSB. */
434 switch (sdev->id.coreid) {
435 case SSB_DEV_CHIPCOMMON:
436 case SSB_DEV_PCI:
437 case SSB_DEV_PCIE:
438 case SSB_DEV_PCMCIA:
439 case SSB_DEV_MIPS:
440 case SSB_DEV_MIPS_3302:
441 case SSB_DEV_EXTIF:
442 continue;
443 }
444
445 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
446 if (!devwrap) {
447 ssb_printk(KERN_ERR PFX
448 "Could not allocate device\n");
449 err = -ENOMEM;
450 goto error;
451 }
452 dev = &devwrap->dev;
453 devwrap->sdev = sdev;
454
455 dev->release = ssb_release_dev;
456 dev->bus = &ssb_bustype;
457 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
458
459 switch (bus->bustype) {
460 case SSB_BUSTYPE_PCI:
461 #ifdef CONFIG_SSB_PCIHOST
462 sdev->irq = bus->host_pci->irq;
463 dev->parent = &bus->host_pci->dev;
464 #endif
465 break;
466 case SSB_BUSTYPE_PCMCIA:
467 #ifdef CONFIG_SSB_PCMCIAHOST
468 sdev->irq = bus->host_pcmcia->irq.AssignedIRQ;
469 dev->parent = &bus->host_pcmcia->dev;
470 #endif
471 break;
472 case SSB_BUSTYPE_SSB:
473 dev->dma_mask = &dev->coherent_dma_mask;
474 break;
475 }
476
477 sdev->dev = dev;
478 err = device_register(dev);
479 if (err) {
480 ssb_printk(KERN_ERR PFX
481 "Could not register %s\n",
482 dev_name(dev));
483 /* Set dev to NULL to not unregister
484 * dev on error unwinding. */
485 sdev->dev = NULL;
486 kfree(devwrap);
487 goto error;
488 }
489 dev_idx++;
490 }
491
492 return 0;
493 error:
494 /* Unwind the already registered devices. */
495 ssb_devices_unregister(bus);
496 return err;
497 }
498
499 /* Needs ssb_buses_lock() */
500 static int ssb_attach_queued_buses(void)
501 {
502 struct ssb_bus *bus, *n;
503 int err = 0;
504 int drop_them_all = 0;
505
506 list_for_each_entry_safe(bus, n, &attach_queue, list) {
507 if (drop_them_all) {
508 list_del(&bus->list);
509 continue;
510 }
511 /* Can't init the PCIcore in ssb_bus_register(), as that
512 * is too early in boot for embedded systems
513 * (no udelay() available). So do it here in attach stage.
514 */
515 err = ssb_bus_powerup(bus, 0);
516 if (err)
517 goto error;
518 ssb_pcicore_init(&bus->pcicore);
519 ssb_bus_may_powerdown(bus);
520
521 err = ssb_devices_register(bus);
522 error:
523 if (err) {
524 drop_them_all = 1;
525 list_del(&bus->list);
526 continue;
527 }
528 list_move_tail(&bus->list, &buses);
529 }
530
531 return err;
532 }
533
534 static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
535 {
536 struct ssb_bus *bus = dev->bus;
537
538 offset += dev->core_index * SSB_CORE_SIZE;
539 return readb(bus->mmio + offset);
540 }
541
542 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
543 {
544 struct ssb_bus *bus = dev->bus;
545
546 offset += dev->core_index * SSB_CORE_SIZE;
547 return readw(bus->mmio + offset);
548 }
549
550 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
551 {
552 struct ssb_bus *bus = dev->bus;
553
554 offset += dev->core_index * SSB_CORE_SIZE;
555 return readl(bus->mmio + offset);
556 }
557
558 #ifdef CONFIG_SSB_BLOCKIO
559 static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
560 size_t count, u16 offset, u8 reg_width)
561 {
562 struct ssb_bus *bus = dev->bus;
563 void __iomem *addr;
564
565 offset += dev->core_index * SSB_CORE_SIZE;
566 addr = bus->mmio + offset;
567
568 switch (reg_width) {
569 case sizeof(u8): {
570 u8 *buf = buffer;
571
572 while (count) {
573 *buf = __raw_readb(addr);
574 buf++;
575 count--;
576 }
577 break;
578 }
579 case sizeof(u16): {
580 __le16 *buf = buffer;
581
582 SSB_WARN_ON(count & 1);
583 while (count) {
584 *buf = (__force __le16)__raw_readw(addr);
585 buf++;
586 count -= 2;
587 }
588 break;
589 }
590 case sizeof(u32): {
591 __le32 *buf = buffer;
592
593 SSB_WARN_ON(count & 3);
594 while (count) {
595 *buf = (__force __le32)__raw_readl(addr);
596 buf++;
597 count -= 4;
598 }
599 break;
600 }
601 default:
602 SSB_WARN_ON(1);
603 }
604 }
605 #endif /* CONFIG_SSB_BLOCKIO */
606
607 static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
608 {
609 struct ssb_bus *bus = dev->bus;
610
611 offset += dev->core_index * SSB_CORE_SIZE;
612 writeb(value, bus->mmio + offset);
613 }
614
615 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
616 {
617 struct ssb_bus *bus = dev->bus;
618
619 offset += dev->core_index * SSB_CORE_SIZE;
620 writew(value, bus->mmio + offset);
621 }
622
623 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
624 {
625 struct ssb_bus *bus = dev->bus;
626
627 offset += dev->core_index * SSB_CORE_SIZE;
628 writel(value, bus->mmio + offset);
629 }
630
631 #ifdef CONFIG_SSB_BLOCKIO
632 static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
633 size_t count, u16 offset, u8 reg_width)
634 {
635 struct ssb_bus *bus = dev->bus;
636 void __iomem *addr;
637
638 offset += dev->core_index * SSB_CORE_SIZE;
639 addr = bus->mmio + offset;
640
641 switch (reg_width) {
642 case sizeof(u8): {
643 const u8 *buf = buffer;
644
645 while (count) {
646 __raw_writeb(*buf, addr);
647 buf++;
648 count--;
649 }
650 break;
651 }
652 case sizeof(u16): {
653 const __le16 *buf = buffer;
654
655 SSB_WARN_ON(count & 1);
656 while (count) {
657 __raw_writew((__force u16)(*buf), addr);
658 buf++;
659 count -= 2;
660 }
661 break;
662 }
663 case sizeof(u32): {
664 const __le32 *buf = buffer;
665
666 SSB_WARN_ON(count & 3);
667 while (count) {
668 __raw_writel((__force u32)(*buf), addr);
669 buf++;
670 count -= 4;
671 }
672 break;
673 }
674 default:
675 SSB_WARN_ON(1);
676 }
677 }
678 #endif /* CONFIG_SSB_BLOCKIO */
679
680 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
681 static const struct ssb_bus_ops ssb_ssb_ops = {
682 .read8 = ssb_ssb_read8,
683 .read16 = ssb_ssb_read16,
684 .read32 = ssb_ssb_read32,
685 .write8 = ssb_ssb_write8,
686 .write16 = ssb_ssb_write16,
687 .write32 = ssb_ssb_write32,
688 #ifdef CONFIG_SSB_BLOCKIO
689 .block_read = ssb_ssb_block_read,
690 .block_write = ssb_ssb_block_write,
691 #endif
692 };
693
694 static int ssb_fetch_invariants(struct ssb_bus *bus,
695 ssb_invariants_func_t get_invariants)
696 {
697 struct ssb_init_invariants iv;
698 int err;
699
700 memset(&iv, 0, sizeof(iv));
701 err = get_invariants(bus, &iv);
702 if (err)
703 goto out;
704 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
705 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
706 bus->has_cardbus_slot = iv.has_cardbus_slot;
707 out:
708 return err;
709 }
710
711 static int ssb_bus_register(struct ssb_bus *bus,
712 ssb_invariants_func_t get_invariants,
713 unsigned long baseaddr)
714 {
715 int err;
716
717 spin_lock_init(&bus->bar_lock);
718 INIT_LIST_HEAD(&bus->list);
719 #ifdef CONFIG_SSB_EMBEDDED
720 spin_lock_init(&bus->gpio_lock);
721 #endif
722
723 /* Powerup the bus */
724 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
725 if (err)
726 goto out;
727 ssb_buses_lock();
728 bus->busnumber = next_busnumber;
729 /* Scan for devices (cores) */
730 err = ssb_bus_scan(bus, baseaddr);
731 if (err)
732 goto err_disable_xtal;
733
734 /* Init PCI-host device (if any) */
735 err = ssb_pci_init(bus);
736 if (err)
737 goto err_unmap;
738 /* Init PCMCIA-host device (if any) */
739 err = ssb_pcmcia_init(bus);
740 if (err)
741 goto err_pci_exit;
742
743 /* Initialize basic system devices (if available) */
744 err = ssb_bus_powerup(bus, 0);
745 if (err)
746 goto err_pcmcia_exit;
747 ssb_chipcommon_init(&bus->chipco);
748 ssb_mipscore_init(&bus->mipscore);
749 err = ssb_fetch_invariants(bus, get_invariants);
750 if (err) {
751 ssb_bus_may_powerdown(bus);
752 goto err_pcmcia_exit;
753 }
754 ssb_bus_may_powerdown(bus);
755
756 /* Queue it for attach.
757 * See the comment at the ssb_is_early_boot definition. */
758 list_add_tail(&bus->list, &attach_queue);
759 if (!ssb_is_early_boot) {
760 /* This is not early boot, so we must attach the bus now */
761 err = ssb_attach_queued_buses();
762 if (err)
763 goto err_dequeue;
764 }
765 next_busnumber++;
766 ssb_buses_unlock();
767
768 out:
769 return err;
770
771 err_dequeue:
772 list_del(&bus->list);
773 err_pcmcia_exit:
774 ssb_pcmcia_exit(bus);
775 err_pci_exit:
776 ssb_pci_exit(bus);
777 err_unmap:
778 ssb_iounmap(bus);
779 err_disable_xtal:
780 ssb_buses_unlock();
781 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
782 return err;
783 }
784
785 #ifdef CONFIG_SSB_PCIHOST
786 int ssb_bus_pcibus_register(struct ssb_bus *bus,
787 struct pci_dev *host_pci)
788 {
789 int err;
790
791 bus->bustype = SSB_BUSTYPE_PCI;
792 bus->host_pci = host_pci;
793 bus->ops = &ssb_pci_ops;
794
795 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
796 if (!err) {
797 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
798 "PCI device %s\n", dev_name(&host_pci->dev));
799 }
800
801 return err;
802 }
803 EXPORT_SYMBOL(ssb_bus_pcibus_register);
804 #endif /* CONFIG_SSB_PCIHOST */
805
806 #ifdef CONFIG_SSB_PCMCIAHOST
807 int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
808 struct pcmcia_device *pcmcia_dev,
809 unsigned long baseaddr)
810 {
811 int err;
812
813 bus->bustype = SSB_BUSTYPE_PCMCIA;
814 bus->host_pcmcia = pcmcia_dev;
815 bus->ops = &ssb_pcmcia_ops;
816
817 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
818 if (!err) {
819 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
820 "PCMCIA device %s\n", pcmcia_dev->devname);
821 }
822
823 return err;
824 }
825 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
826 #endif /* CONFIG_SSB_PCMCIAHOST */
827
828 int ssb_bus_ssbbus_register(struct ssb_bus *bus,
829 unsigned long baseaddr,
830 ssb_invariants_func_t get_invariants)
831 {
832 int err;
833
834 bus->bustype = SSB_BUSTYPE_SSB;
835 bus->ops = &ssb_ssb_ops;
836
837 err = ssb_bus_register(bus, get_invariants, baseaddr);
838 if (!err) {
839 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
840 "address 0x%08lX\n", baseaddr);
841 }
842
843 return err;
844 }
845
846 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
847 {
848 drv->drv.name = drv->name;
849 drv->drv.bus = &ssb_bustype;
850 drv->drv.owner = owner;
851
852 return driver_register(&drv->drv);
853 }
854 EXPORT_SYMBOL(__ssb_driver_register);
855
856 void ssb_driver_unregister(struct ssb_driver *drv)
857 {
858 driver_unregister(&drv->drv);
859 }
860 EXPORT_SYMBOL(ssb_driver_unregister);
861
862 void ssb_set_devtypedata(struct ssb_device *dev, void *data)
863 {
864 struct ssb_bus *bus = dev->bus;
865 struct ssb_device *ent;
866 int i;
867
868 for (i = 0; i < bus->nr_devices; i++) {
869 ent = &(bus->devices[i]);
870 if (ent->id.vendor != dev->id.vendor)
871 continue;
872 if (ent->id.coreid != dev->id.coreid)
873 continue;
874
875 ent->devtypedata = data;
876 }
877 }
878 EXPORT_SYMBOL(ssb_set_devtypedata);
879
880 static u32 clkfactor_f6_resolve(u32 v)
881 {
882 /* map the magic values */
883 switch (v) {
884 case SSB_CHIPCO_CLK_F6_2:
885 return 2;
886 case SSB_CHIPCO_CLK_F6_3:
887 return 3;
888 case SSB_CHIPCO_CLK_F6_4:
889 return 4;
890 case SSB_CHIPCO_CLK_F6_5:
891 return 5;
892 case SSB_CHIPCO_CLK_F6_6:
893 return 6;
894 case SSB_CHIPCO_CLK_F6_7:
895 return 7;
896 }
897 return 0;
898 }
899
900 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
901 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
902 {
903 u32 n1, n2, clock, m1, m2, m3, mc;
904
905 n1 = (n & SSB_CHIPCO_CLK_N1);
906 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
907
908 switch (plltype) {
909 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
910 if (m & SSB_CHIPCO_CLK_T6_MMASK)
911 return SSB_CHIPCO_CLK_T6_M0;
912 return SSB_CHIPCO_CLK_T6_M1;
913 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
914 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
915 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
916 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
917 n1 = clkfactor_f6_resolve(n1);
918 n2 += SSB_CHIPCO_CLK_F5_BIAS;
919 break;
920 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
921 n1 += SSB_CHIPCO_CLK_T2_BIAS;
922 n2 += SSB_CHIPCO_CLK_T2_BIAS;
923 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
924 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
925 break;
926 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
927 return 100000000;
928 default:
929 SSB_WARN_ON(1);
930 }
931
932 switch (plltype) {
933 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
934 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
935 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
936 break;
937 default:
938 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
939 }
940 if (!clock)
941 return 0;
942
943 m1 = (m & SSB_CHIPCO_CLK_M1);
944 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
945 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
946 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
947
948 switch (plltype) {
949 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
950 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
951 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
952 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
953 m1 = clkfactor_f6_resolve(m1);
954 if ((plltype == SSB_PLLTYPE_1) ||
955 (plltype == SSB_PLLTYPE_3))
956 m2 += SSB_CHIPCO_CLK_F5_BIAS;
957 else
958 m2 = clkfactor_f6_resolve(m2);
959 m3 = clkfactor_f6_resolve(m3);
960
961 switch (mc) {
962 case SSB_CHIPCO_CLK_MC_BYPASS:
963 return clock;
964 case SSB_CHIPCO_CLK_MC_M1:
965 return (clock / m1);
966 case SSB_CHIPCO_CLK_MC_M1M2:
967 return (clock / (m1 * m2));
968 case SSB_CHIPCO_CLK_MC_M1M2M3:
969 return (clock / (m1 * m2 * m3));
970 case SSB_CHIPCO_CLK_MC_M1M3:
971 return (clock / (m1 * m3));
972 }
973 return 0;
974 case SSB_PLLTYPE_2:
975 m1 += SSB_CHIPCO_CLK_T2_BIAS;
976 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
977 m3 += SSB_CHIPCO_CLK_T2_BIAS;
978 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
979 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
980 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
981
982 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
983 clock /= m1;
984 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
985 clock /= m2;
986 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
987 clock /= m3;
988 return clock;
989 default:
990 SSB_WARN_ON(1);
991 }
992 return 0;
993 }
994
995 /* Get the current speed the backplane is running at */
996 u32 ssb_clockspeed(struct ssb_bus *bus)
997 {
998 u32 rate;
999 u32 plltype;
1000 u32 clkctl_n, clkctl_m;
1001
1002 if (ssb_extif_available(&bus->extif))
1003 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1004 &clkctl_n, &clkctl_m);
1005 else if (bus->chipco.dev)
1006 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
1007 &clkctl_n, &clkctl_m);
1008 else
1009 return 0;
1010
1011 if (bus->chip_id == 0x5365) {
1012 rate = 100000000;
1013 } else {
1014 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
1015 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
1016 rate /= 2;
1017 }
1018
1019 return rate;
1020 }
1021 EXPORT_SYMBOL(ssb_clockspeed);
1022
1023 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
1024 {
1025 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1026
1027 /* The REJECT bit changed position in TMSLOW between
1028 * Backplane revisions. */
1029 switch (rev) {
1030 case SSB_IDLOW_SSBREV_22:
1031 return SSB_TMSLOW_REJECT_22;
1032 case SSB_IDLOW_SSBREV_23:
1033 return SSB_TMSLOW_REJECT_23;
1034 case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
1035 case SSB_IDLOW_SSBREV_25: /* same here */
1036 case SSB_IDLOW_SSBREV_26: /* same here */
1037 case SSB_IDLOW_SSBREV_27: /* same here */
1038 return SSB_TMSLOW_REJECT_23; /* this is a guess */
1039 default:
1040 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1041 WARN_ON(1);
1042 }
1043 return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
1044 }
1045
1046 int ssb_device_is_enabled(struct ssb_device *dev)
1047 {
1048 u32 val;
1049 u32 reject;
1050
1051 reject = ssb_tmslow_reject_bitmask(dev);
1052 val = ssb_read32(dev, SSB_TMSLOW);
1053 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
1054
1055 return (val == SSB_TMSLOW_CLOCK);
1056 }
1057 EXPORT_SYMBOL(ssb_device_is_enabled);
1058
1059 static void ssb_flush_tmslow(struct ssb_device *dev)
1060 {
1061 /* Make _really_ sure the device has finished the TMSLOW
1062 * register write transaction, as we risk running into
1063 * a machine check exception otherwise.
1064 * Do this by reading the register back to commit the
1065 * PCI write and delay an additional usec for the device
1066 * to react to the change. */
1067 ssb_read32(dev, SSB_TMSLOW);
1068 udelay(1);
1069 }
1070
1071 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
1072 {
1073 u32 val;
1074
1075 ssb_device_disable(dev, core_specific_flags);
1076 ssb_write32(dev, SSB_TMSLOW,
1077 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
1078 SSB_TMSLOW_FGC | core_specific_flags);
1079 ssb_flush_tmslow(dev);
1080
1081 /* Clear SERR if set. This is a hw bug workaround. */
1082 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
1083 ssb_write32(dev, SSB_TMSHIGH, 0);
1084
1085 val = ssb_read32(dev, SSB_IMSTATE);
1086 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
1087 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
1088 ssb_write32(dev, SSB_IMSTATE, val);
1089 }
1090
1091 ssb_write32(dev, SSB_TMSLOW,
1092 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
1093 core_specific_flags);
1094 ssb_flush_tmslow(dev);
1095
1096 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
1097 core_specific_flags);
1098 ssb_flush_tmslow(dev);
1099 }
1100 EXPORT_SYMBOL(ssb_device_enable);
1101
1102 /* Wait for a bit in a register to get set or unset.
1103 * timeout is in units of ten-microseconds */
1104 static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
1105 int timeout, int set)
1106 {
1107 int i;
1108 u32 val;
1109
1110 for (i = 0; i < timeout; i++) {
1111 val = ssb_read32(dev, reg);
1112 if (set) {
1113 if (val & bitmask)
1114 return 0;
1115 } else {
1116 if (!(val & bitmask))
1117 return 0;
1118 }
1119 udelay(10);
1120 }
1121 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
1122 "register %04X to %s.\n",
1123 bitmask, reg, (set ? "set" : "clear"));
1124
1125 return -ETIMEDOUT;
1126 }
1127
1128 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1129 {
1130 u32 reject;
1131
1132 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1133 return;
1134
1135 reject = ssb_tmslow_reject_bitmask(dev);
1136 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1137 ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
1138 ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1139 ssb_write32(dev, SSB_TMSLOW,
1140 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1141 reject | SSB_TMSLOW_RESET |
1142 core_specific_flags);
1143 ssb_flush_tmslow(dev);
1144
1145 ssb_write32(dev, SSB_TMSLOW,
1146 reject | SSB_TMSLOW_RESET |
1147 core_specific_flags);
1148 ssb_flush_tmslow(dev);
1149 }
1150 EXPORT_SYMBOL(ssb_device_disable);
1151
1152 u32 ssb_dma_translation(struct ssb_device *dev)
1153 {
1154 switch (dev->bus->bustype) {
1155 case SSB_BUSTYPE_SSB:
1156 return 0;
1157 case SSB_BUSTYPE_PCI:
1158 return SSB_PCI_DMA;
1159 default:
1160 __ssb_dma_not_implemented(dev);
1161 }
1162 return 0;
1163 }
1164 EXPORT_SYMBOL(ssb_dma_translation);
1165
1166 int ssb_dma_set_mask(struct ssb_device *dev, u64 mask)
1167 {
1168 #ifdef CONFIG_SSB_PCIHOST
1169 int err;
1170 #endif
1171
1172 switch (dev->bus->bustype) {
1173 case SSB_BUSTYPE_PCI:
1174 #ifdef CONFIG_SSB_PCIHOST
1175 err = pci_set_dma_mask(dev->bus->host_pci, mask);
1176 if (err)
1177 return err;
1178 err = pci_set_consistent_dma_mask(dev->bus->host_pci, mask);
1179 return err;
1180 #endif
1181 case SSB_BUSTYPE_SSB:
1182 return dma_set_mask(dev->dev, mask);
1183 default:
1184 __ssb_dma_not_implemented(dev);
1185 }
1186 return -ENOSYS;
1187 }
1188 EXPORT_SYMBOL(ssb_dma_set_mask);
1189
1190 void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
1191 dma_addr_t *dma_handle, gfp_t gfp_flags)
1192 {
1193 switch (dev->bus->bustype) {
1194 case SSB_BUSTYPE_PCI:
1195 #ifdef CONFIG_SSB_PCIHOST
1196 if (gfp_flags & GFP_DMA) {
1197 /* Workaround: The PCI API does not support passing
1198 * a GFP flag. */
1199 return dma_alloc_coherent(&dev->bus->host_pci->dev,
1200 size, dma_handle, gfp_flags);
1201 }
1202 return pci_alloc_consistent(dev->bus->host_pci, size, dma_handle);
1203 #endif
1204 case SSB_BUSTYPE_SSB:
1205 return dma_alloc_coherent(dev->dev, size, dma_handle, gfp_flags);
1206 default:
1207 __ssb_dma_not_implemented(dev);
1208 }
1209 return NULL;
1210 }
1211 EXPORT_SYMBOL(ssb_dma_alloc_consistent);
1212
1213 void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
1214 void *vaddr, dma_addr_t dma_handle,
1215 gfp_t gfp_flags)
1216 {
1217 switch (dev->bus->bustype) {
1218 case SSB_BUSTYPE_PCI:
1219 #ifdef CONFIG_SSB_PCIHOST
1220 if (gfp_flags & GFP_DMA) {
1221 /* Workaround: The PCI API does not support passing
1222 * a GFP flag. */
1223 dma_free_coherent(&dev->bus->host_pci->dev,
1224 size, vaddr, dma_handle);
1225 return;
1226 }
1227 pci_free_consistent(dev->bus->host_pci, size,
1228 vaddr, dma_handle);
1229 return;
1230 #endif
1231 case SSB_BUSTYPE_SSB:
1232 dma_free_coherent(dev->dev, size, vaddr, dma_handle);
1233 return;
1234 default:
1235 __ssb_dma_not_implemented(dev);
1236 }
1237 }
1238 EXPORT_SYMBOL(ssb_dma_free_consistent);
1239
1240 int ssb_bus_may_powerdown(struct ssb_bus *bus)
1241 {
1242 struct ssb_chipcommon *cc;
1243 int err = 0;
1244
1245 /* On buses where more than one core may be working
1246 * at a time, we must not powerdown stuff if there are
1247 * still cores that may want to run. */
1248 if (bus->bustype == SSB_BUSTYPE_SSB)
1249 goto out;
1250
1251 cc = &bus->chipco;
1252
1253 if (!cc->dev)
1254 goto out;
1255 if (cc->dev->id.revision < 5)
1256 goto out;
1257
1258 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1259 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1260 if (err)
1261 goto error;
1262 out:
1263 #ifdef CONFIG_SSB_DEBUG
1264 bus->powered_up = 0;
1265 #endif
1266 return err;
1267 error:
1268 ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1269 goto out;
1270 }
1271 EXPORT_SYMBOL(ssb_bus_may_powerdown);
1272
1273 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1274 {
1275 struct ssb_chipcommon *cc;
1276 int err;
1277 enum ssb_clkmode mode;
1278
1279 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1280 if (err)
1281 goto error;
1282 cc = &bus->chipco;
1283 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1284 ssb_chipco_set_clockmode(cc, mode);
1285
1286 #ifdef CONFIG_SSB_DEBUG
1287 bus->powered_up = 1;
1288 #endif
1289 return 0;
1290 error:
1291 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1292 return err;
1293 }
1294 EXPORT_SYMBOL(ssb_bus_powerup);
1295
1296 u32 ssb_admatch_base(u32 adm)
1297 {
1298 u32 base = 0;
1299
1300 switch (adm & SSB_ADM_TYPE) {
1301 case SSB_ADM_TYPE0:
1302 base = (adm & SSB_ADM_BASE0);
1303 break;
1304 case SSB_ADM_TYPE1:
1305 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1306 base = (adm & SSB_ADM_BASE1);
1307 break;
1308 case SSB_ADM_TYPE2:
1309 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1310 base = (adm & SSB_ADM_BASE2);
1311 break;
1312 default:
1313 SSB_WARN_ON(1);
1314 }
1315
1316 return base;
1317 }
1318 EXPORT_SYMBOL(ssb_admatch_base);
1319
1320 u32 ssb_admatch_size(u32 adm)
1321 {
1322 u32 size = 0;
1323
1324 switch (adm & SSB_ADM_TYPE) {
1325 case SSB_ADM_TYPE0:
1326 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1327 break;
1328 case SSB_ADM_TYPE1:
1329 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1330 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1331 break;
1332 case SSB_ADM_TYPE2:
1333 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1334 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1335 break;
1336 default:
1337 SSB_WARN_ON(1);
1338 }
1339 size = (1 << (size + 1));
1340
1341 return size;
1342 }
1343 EXPORT_SYMBOL(ssb_admatch_size);
1344
1345 static int __init ssb_modinit(void)
1346 {
1347 int err;
1348
1349 /* See the comment at the ssb_is_early_boot definition */
1350 ssb_is_early_boot = 0;
1351 err = bus_register(&ssb_bustype);
1352 if (err)
1353 return err;
1354
1355 /* Maybe we already registered some buses at early boot.
1356 * Check for this and attach them
1357 */
1358 ssb_buses_lock();
1359 err = ssb_attach_queued_buses();
1360 ssb_buses_unlock();
1361 if (err)
1362 bus_unregister(&ssb_bustype);
1363
1364 err = b43_pci_ssb_bridge_init();
1365 if (err) {
1366 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1367 "initialization failed\n");
1368 /* don't fail SSB init because of this */
1369 err = 0;
1370 }
1371 err = ssb_gige_init();
1372 if (err) {
1373 ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1374 "driver initialization failed\n");
1375 /* don't fail SSB init because of this */
1376 err = 0;
1377 }
1378
1379 return err;
1380 }
1381 /* ssb must be initialized after PCI but before the ssb drivers.
1382 * That means we must use some initcall between subsys_initcall
1383 * and device_initcall. */
1384 fs_initcall(ssb_modinit);
1385
1386 static void __exit ssb_modexit(void)
1387 {
1388 ssb_gige_exit();
1389 b43_pci_ssb_bridge_exit();
1390 bus_unregister(&ssb_bustype);
1391 }
1392 module_exit(ssb_modexit)
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK