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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / serial / sh-sci.c
blob557b54ab2f25d22b0f623b7f6dde18cb12cc47f2
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 *
18 * This file is subject to the terms and conditions of the GNU General Public
19 * License. See the file "COPYING" in the main directory of this archive
20 * for more details.
21 */
22 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #define SUPPORT_SYSRQ
24 #endif
25
26 #undef DEBUG
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/timer.h>
31 #include <linux/interrupt.h>
32 #include <linux/tty.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial.h>
35 #include <linux/major.h>
36 #include <linux/string.h>
37 #include <linux/sysrq.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
42 #include <linux/console.h>
43 #include <linux/platform_device.h>
44 #include <linux/serial_sci.h>
45 #include <linux/notifier.h>
46 #include <linux/cpufreq.h>
47 #include <linux/clk.h>
48 #include <linux/ctype.h>
49 #include <linux/err.h>
50
51 #ifdef CONFIG_SUPERH
52 #include <asm/clock.h>
53 #include <asm/sh_bios.h>
54 #endif
55
56 #include "sh-sci.h"
57
58 struct sci_port {
59 struct uart_port port;
60
61 /* Port type */
62 unsigned int type;
63
64 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
65 unsigned int irqs[SCIx_NR_IRQS];
66
67 /* Port enable callback */
68 void (*enable)(struct uart_port *port);
69
70 /* Port disable callback */
71 void (*disable)(struct uart_port *port);
72
73 /* Break timer */
74 struct timer_list break_timer;
75 int break_flag;
76
77 #ifdef CONFIG_HAVE_CLK
78 /* Port clock */
79 struct clk *clk;
80 #endif
81 };
82
83 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
84 static struct sci_port *serial_console_port;
85 #endif
86
87 /* Function prototypes */
88 static void sci_stop_tx(struct uart_port *port);
89
90 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
91
92 static struct sci_port sci_ports[SCI_NPORTS];
93 static struct uart_driver sci_uart_driver;
94
95 static inline struct sci_port *
96 to_sci_port(struct uart_port *uart)
97 {
98 return container_of(uart, struct sci_port, port);
99 }
100
101 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
102
103 #ifdef CONFIG_CONSOLE_POLL
104 static inline void handle_error(struct uart_port *port)
105 {
106 /* Clear error flags */
107 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
108 }
109
110 static int sci_poll_get_char(struct uart_port *port)
111 {
112 unsigned short status;
113 int c;
114
115 do {
116 status = sci_in(port, SCxSR);
117 if (status & SCxSR_ERRORS(port)) {
118 handle_error(port);
119 continue;
120 }
121 } while (!(status & SCxSR_RDxF(port)));
122
123 c = sci_in(port, SCxRDR);
124
125 /* Dummy read */
126 sci_in(port, SCxSR);
127 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
128
129 return c;
130 }
131 #endif
132
133 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
134 {
135 unsigned short status;
136
137 do {
138 status = sci_in(port, SCxSR);
139 } while (!(status & SCxSR_TDxE(port)));
140
141 sci_in(port, SCxSR); /* Dummy read */
142 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
143 sci_out(port, SCxTDR, c);
144 }
145 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
146
147 #if defined(__H8300S__)
148 enum { sci_disable, sci_enable };
149
150 static void h8300_sci_config(struct uart_port *port, unsigned int ctrl)
151 {
152 volatile unsigned char *mstpcrl = (volatile unsigned char *)MSTPCRL;
153 int ch = (port->mapbase - SMR0) >> 3;
154 unsigned char mask = 1 << (ch+1);
155
156 if (ctrl == sci_disable)
157 *mstpcrl |= mask;
158 else
159 *mstpcrl &= ~mask;
160 }
161
162 static inline void h8300_sci_enable(struct uart_port *port)
163 {
164 h8300_sci_config(port, sci_enable);
165 }
166
167 static inline void h8300_sci_disable(struct uart_port *port)
168 {
169 h8300_sci_config(port, sci_disable);
170 }
171 #endif
172
173 #if defined(__H8300H__) || defined(__H8300S__)
174 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
175 {
176 int ch = (port->mapbase - SMR0) >> 3;
177
178 /* set DDR regs */
179 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
180 h8300_sci_pins[ch].rx,
181 H8300_GPIO_INPUT);
182 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
183 h8300_sci_pins[ch].tx,
184 H8300_GPIO_OUTPUT);
185
186 /* tx mark output*/
187 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
188 }
189 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
190 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
191 {
192 if (port->mapbase == 0xA4400000) {
193 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
194 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
195 } else if (port->mapbase == 0xA4410000)
196 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
197 }
198 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
199 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
200 {
201 unsigned short data;
202
203 if (cflag & CRTSCTS) {
204 /* enable RTS/CTS */
205 if (port->mapbase == 0xa4430000) { /* SCIF0 */
206 /* Clear PTCR bit 9-2; enable all scif pins but sck */
207 data = __raw_readw(PORT_PTCR);
208 __raw_writew((data & 0xfc03), PORT_PTCR);
209 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
210 /* Clear PVCR bit 9-2 */
211 data = __raw_readw(PORT_PVCR);
212 __raw_writew((data & 0xfc03), PORT_PVCR);
213 }
214 } else {
215 if (port->mapbase == 0xa4430000) { /* SCIF0 */
216 /* Clear PTCR bit 5-2; enable only tx and rx */
217 data = __raw_readw(PORT_PTCR);
218 __raw_writew((data & 0xffc3), PORT_PTCR);
219 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
220 /* Clear PVCR bit 5-2 */
221 data = __raw_readw(PORT_PVCR);
222 __raw_writew((data & 0xffc3), PORT_PVCR);
223 }
224 }
225 }
226 #elif defined(CONFIG_CPU_SH3)
227 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
228 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
229 {
230 unsigned short data;
231
232 /* We need to set SCPCR to enable RTS/CTS */
233 data = __raw_readw(SCPCR);
234 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
235 __raw_writew(data & 0x0fcf, SCPCR);
236
237 if (!(cflag & CRTSCTS)) {
238 /* We need to set SCPCR to enable RTS/CTS */
239 data = __raw_readw(SCPCR);
240 /* Clear out SCP7MD1,0, SCP4MD1,0,
241 Set SCP6MD1,0 = {01} (output) */
242 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
243
244 data = ctrl_inb(SCPDR);
245 /* Set /RTS2 (bit6) = 0 */
246 ctrl_outb(data & 0xbf, SCPDR);
247 }
248 }
249 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
250 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
251 {
252 unsigned short data;
253
254 if (port->mapbase == 0xffe00000) {
255 data = __raw_readw(PSCR);
256 data &= ~0x03cf;
257 if (!(cflag & CRTSCTS))
258 data |= 0x0340;
259
260 __raw_writew(data, PSCR);
261 }
262 }
263 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
265 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
266 defined(CONFIG_CPU_SUBTYPE_SHX3)
267 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
268 {
269 if (!(cflag & CRTSCTS))
270 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
271 }
272 #elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
273 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
274 {
275 if (!(cflag & CRTSCTS))
276 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
277 }
278 #else
279 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
280 {
281 /* Nothing to do */
282 }
283 #endif
284
285 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
286 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
287 defined(CONFIG_CPU_SUBTYPE_SH7785)
288 static inline int scif_txroom(struct uart_port *port)
289 {
290 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
291 }
292
293 static inline int scif_rxroom(struct uart_port *port)
294 {
295 return sci_in(port, SCRFDR) & 0xff;
296 }
297 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
298 static inline int scif_txroom(struct uart_port *port)
299 {
300 if ((port->mapbase == 0xffe00000) ||
301 (port->mapbase == 0xffe08000)) {
302 /* SCIF0/1*/
303 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
304 } else {
305 /* SCIF2 */
306 return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
307 }
308 }
309
310 static inline int scif_rxroom(struct uart_port *port)
311 {
312 if ((port->mapbase == 0xffe00000) ||
313 (port->mapbase == 0xffe08000)) {
314 /* SCIF0/1*/
315 return sci_in(port, SCRFDR) & 0xff;
316 } else {
317 /* SCIF2 */
318 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
319 }
320 }
321 #else
322 static inline int scif_txroom(struct uart_port *port)
323 {
324 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
325 }
326
327 static inline int scif_rxroom(struct uart_port *port)
328 {
329 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
330 }
331 #endif
332
333 static inline int sci_txroom(struct uart_port *port)
334 {
335 return (sci_in(port, SCxSR) & SCI_TDRE) != 0;
336 }
337
338 static inline int sci_rxroom(struct uart_port *port)
339 {
340 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
341 }
342
343 /* ********************************************************************** *
344 * the interrupt related routines *
345 * ********************************************************************** */
346
347 static void sci_transmit_chars(struct uart_port *port)
348 {
349 struct circ_buf *xmit = &port->info->xmit;
350 unsigned int stopped = uart_tx_stopped(port);
351 unsigned short status;
352 unsigned short ctrl;
353 int count;
354
355 status = sci_in(port, SCxSR);
356 if (!(status & SCxSR_TDxE(port))) {
357 ctrl = sci_in(port, SCSCR);
358 if (uart_circ_empty(xmit))
359 ctrl &= ~SCI_CTRL_FLAGS_TIE;
360 else
361 ctrl |= SCI_CTRL_FLAGS_TIE;
362 sci_out(port, SCSCR, ctrl);
363 return;
364 }
365
366 if (port->type == PORT_SCI)
367 count = sci_txroom(port);
368 else
369 count = scif_txroom(port);
370
371 do {
372 unsigned char c;
373
374 if (port->x_char) {
375 c = port->x_char;
376 port->x_char = 0;
377 } else if (!uart_circ_empty(xmit) && !stopped) {
378 c = xmit->buf[xmit->tail];
379 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
380 } else {
381 break;
382 }
383
384 sci_out(port, SCxTDR, c);
385
386 port->icount.tx++;
387 } while (--count > 0);
388
389 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
390
391 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
392 uart_write_wakeup(port);
393 if (uart_circ_empty(xmit)) {
394 sci_stop_tx(port);
395 } else {
396 ctrl = sci_in(port, SCSCR);
397
398 if (port->type != PORT_SCI) {
399 sci_in(port, SCxSR); /* Dummy read */
400 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
401 }
402
403 ctrl |= SCI_CTRL_FLAGS_TIE;
404 sci_out(port, SCSCR, ctrl);
405 }
406 }
407
408 /* On SH3, SCIF may read end-of-break as a space->mark char */
409 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
410
411 static inline void sci_receive_chars(struct uart_port *port)
412 {
413 struct sci_port *sci_port = to_sci_port(port);
414 struct tty_struct *tty = port->info->port.tty;
415 int i, count, copied = 0;
416 unsigned short status;
417 unsigned char flag;
418
419 status = sci_in(port, SCxSR);
420 if (!(status & SCxSR_RDxF(port)))
421 return;
422
423 while (1) {
424 if (port->type == PORT_SCI)
425 count = sci_rxroom(port);
426 else
427 count = scif_rxroom(port);
428
429 /* Don't copy more bytes than there is room for in the buffer */
430 count = tty_buffer_request_room(tty, count);
431
432 /* If for any reason we can't copy more data, we're done! */
433 if (count == 0)
434 break;
435
436 if (port->type == PORT_SCI) {
437 char c = sci_in(port, SCxRDR);
438 if (uart_handle_sysrq_char(port, c) ||
439 sci_port->break_flag)
440 count = 0;
441 else
442 tty_insert_flip_char(tty, c, TTY_NORMAL);
443 } else {
444 for (i = 0; i < count; i++) {
445 char c = sci_in(port, SCxRDR);
446 status = sci_in(port, SCxSR);
447 #if defined(CONFIG_CPU_SH3)
448 /* Skip "chars" during break */
449 if (sci_port->break_flag) {
450 if ((c == 0) &&
451 (status & SCxSR_FER(port))) {
452 count--; i--;
453 continue;
454 }
455
456 /* Nonzero => end-of-break */
457 dev_dbg(port->dev, "debounce<%02x>\n", c);
458 sci_port->break_flag = 0;
459
460 if (STEPFN(c)) {
461 count--; i--;
462 continue;
463 }
464 }
465 #endif /* CONFIG_CPU_SH3 */
466 if (uart_handle_sysrq_char(port, c)) {
467 count--; i--;
468 continue;
469 }
470
471 /* Store data and status */
472 if (status&SCxSR_FER(port)) {
473 flag = TTY_FRAME;
474 dev_notice(port->dev, "frame error\n");
475 } else if (status&SCxSR_PER(port)) {
476 flag = TTY_PARITY;
477 dev_notice(port->dev, "parity error\n");
478 } else
479 flag = TTY_NORMAL;
480
481 tty_insert_flip_char(tty, c, flag);
482 }
483 }
484
485 sci_in(port, SCxSR); /* dummy read */
486 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
487
488 copied += count;
489 port->icount.rx += count;
490 }
491
492 if (copied) {
493 /* Tell the rest of the system the news. New characters! */
494 tty_flip_buffer_push(tty);
495 } else {
496 sci_in(port, SCxSR); /* dummy read */
497 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
498 }
499 }
500
501 #define SCI_BREAK_JIFFIES (HZ/20)
502 /* The sci generates interrupts during the break,
503 * 1 per millisecond or so during the break period, for 9600 baud.
504 * So dont bother disabling interrupts.
505 * But dont want more than 1 break event.
506 * Use a kernel timer to periodically poll the rx line until
507 * the break is finished.
508 */
509 static void sci_schedule_break_timer(struct sci_port *port)
510 {
511 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
512 add_timer(&port->break_timer);
513 }
514 /* Ensure that two consecutive samples find the break over. */
515 static void sci_break_timer(unsigned long data)
516 {
517 struct sci_port *port = (struct sci_port *)data;
518
519 if (sci_rxd_in(&port->port) == 0) {
520 port->break_flag = 1;
521 sci_schedule_break_timer(port);
522 } else if (port->break_flag == 1) {
523 /* break is over. */
524 port->break_flag = 2;
525 sci_schedule_break_timer(port);
526 } else
527 port->break_flag = 0;
528 }
529
530 static inline int sci_handle_errors(struct uart_port *port)
531 {
532 int copied = 0;
533 unsigned short status = sci_in(port, SCxSR);
534 struct tty_struct *tty = port->info->port.tty;
535
536 if (status & SCxSR_ORER(port)) {
537 /* overrun error */
538 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
539 copied++;
540
541 dev_notice(port->dev, "overrun error");
542 }
543
544 if (status & SCxSR_FER(port)) {
545 if (sci_rxd_in(port) == 0) {
546 /* Notify of BREAK */
547 struct sci_port *sci_port = to_sci_port(port);
548
549 if (!sci_port->break_flag) {
550 sci_port->break_flag = 1;
551 sci_schedule_break_timer(sci_port);
552
553 /* Do sysrq handling. */
554 if (uart_handle_break(port))
555 return 0;
556
557 dev_dbg(port->dev, "BREAK detected\n");
558
559 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
560 copied++;
561 }
562
563 } else {
564 /* frame error */
565 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
566 copied++;
567
568 dev_notice(port->dev, "frame error\n");
569 }
570 }
571
572 if (status & SCxSR_PER(port)) {
573 /* parity error */
574 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
575 copied++;
576
577 dev_notice(port->dev, "parity error");
578 }
579
580 if (copied)
581 tty_flip_buffer_push(tty);
582
583 return copied;
584 }
585
586 static inline int sci_handle_fifo_overrun(struct uart_port *port)
587 {
588 struct tty_struct *tty = port->info->port.tty;
589 int copied = 0;
590
591 if (port->type != PORT_SCIF)
592 return 0;
593
594 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
595 sci_out(port, SCLSR, 0);
596
597 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
598 tty_flip_buffer_push(tty);
599
600 dev_notice(port->dev, "overrun error\n");
601 copied++;
602 }
603
604 return copied;
605 }
606
607 static inline int sci_handle_breaks(struct uart_port *port)
608 {
609 int copied = 0;
610 unsigned short status = sci_in(port, SCxSR);
611 struct tty_struct *tty = port->info->port.tty;
612 struct sci_port *s = &sci_ports[port->line];
613
614 if (uart_handle_break(port))
615 return 0;
616
617 if (!s->break_flag && status & SCxSR_BRK(port)) {
618 #if defined(CONFIG_CPU_SH3)
619 /* Debounce break */
620 s->break_flag = 1;
621 #endif
622 /* Notify of BREAK */
623 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
624 copied++;
625
626 dev_dbg(port->dev, "BREAK detected\n");
627 }
628
629 if (copied)
630 tty_flip_buffer_push(tty);
631
632 copied += sci_handle_fifo_overrun(port);
633
634 return copied;
635 }
636
637 static irqreturn_t sci_rx_interrupt(int irq, void *port)
638 {
639 /* I think sci_receive_chars has to be called irrespective
640 * of whether the I_IXOFF is set, otherwise, how is the interrupt
641 * to be disabled?
642 */
643 sci_receive_chars(port);
644
645 return IRQ_HANDLED;
646 }
647
648 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
649 {
650 struct uart_port *port = ptr;
651
652 spin_lock_irq(&port->lock);
653 sci_transmit_chars(port);
654 spin_unlock_irq(&port->lock);
655
656 return IRQ_HANDLED;
657 }
658
659 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
660 {
661 struct uart_port *port = ptr;
662
663 /* Handle errors */
664 if (port->type == PORT_SCI) {
665 if (sci_handle_errors(port)) {
666 /* discard character in rx buffer */
667 sci_in(port, SCxSR);
668 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
669 }
670 } else {
671 sci_handle_fifo_overrun(port);
672 sci_rx_interrupt(irq, ptr);
673 }
674
675 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
676
677 /* Kick the transmission */
678 sci_tx_interrupt(irq, ptr);
679
680 return IRQ_HANDLED;
681 }
682
683 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
684 {
685 struct uart_port *port = ptr;
686
687 /* Handle BREAKs */
688 sci_handle_breaks(port);
689 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
690
691 return IRQ_HANDLED;
692 }
693
694 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
695 {
696 unsigned short ssr_status, scr_status;
697 struct uart_port *port = ptr;
698 irqreturn_t ret = IRQ_NONE;
699
700 ssr_status = sci_in(port, SCxSR);
701 scr_status = sci_in(port, SCSCR);
702
703 /* Tx Interrupt */
704 if ((ssr_status & 0x0020) && (scr_status & SCI_CTRL_FLAGS_TIE))
705 ret = sci_tx_interrupt(irq, ptr);
706 /* Rx Interrupt */
707 if ((ssr_status & 0x0002) && (scr_status & SCI_CTRL_FLAGS_RIE))
708 ret = sci_rx_interrupt(irq, ptr);
709 /* Error Interrupt */
710 if ((ssr_status & 0x0080) && (scr_status & SCI_CTRL_FLAGS_REIE))
711 ret = sci_er_interrupt(irq, ptr);
712 /* Break Interrupt */
713 if ((ssr_status & 0x0010) && (scr_status & SCI_CTRL_FLAGS_REIE))
714 ret = sci_br_interrupt(irq, ptr);
715
716 return ret;
717 }
718
719 #ifdef CONFIG_HAVE_CLK
720 /*
721 * Here we define a transistion notifier so that we can update all of our
722 * ports' baud rate when the peripheral clock changes.
723 */
724 static int sci_notifier(struct notifier_block *self,
725 unsigned long phase, void *p)
726 {
727 int i;
728
729 if ((phase == CPUFREQ_POSTCHANGE) ||
730 (phase == CPUFREQ_RESUMECHANGE))
731 for (i = 0; i < SCI_NPORTS; i++) {
732 struct sci_port *s = &sci_ports[i];
733 s->port.uartclk = clk_get_rate(s->clk);
734 }
735
736 return NOTIFY_OK;
737 }
738
739 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
740 #endif
741
742 static int sci_request_irq(struct sci_port *port)
743 {
744 int i;
745 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
746 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
747 sci_br_interrupt,
748 };
749 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
750 "SCI Transmit Data Empty", "SCI Break" };
751
752 if (port->irqs[0] == port->irqs[1]) {
753 if (unlikely(!port->irqs[0]))
754 return -ENODEV;
755
756 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
757 IRQF_DISABLED, "sci", port)) {
758 dev_err(port->port.dev, "Can't allocate IRQ\n");
759 return -ENODEV;
760 }
761 } else {
762 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
763 if (unlikely(!port->irqs[i]))
764 continue;
765
766 if (request_irq(port->irqs[i], handlers[i],
767 IRQF_DISABLED, desc[i], port)) {
768 dev_err(port->port.dev, "Can't allocate IRQ\n");
769 return -ENODEV;
770 }
771 }
772 }
773
774 return 0;
775 }
776
777 static void sci_free_irq(struct sci_port *port)
778 {
779 int i;
780
781 if (port->irqs[0] == port->irqs[1])
782 free_irq(port->irqs[0], port);
783 else {
784 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
785 if (!port->irqs[i])
786 continue;
787
788 free_irq(port->irqs[i], port);
789 }
790 }
791 }
792
793 static unsigned int sci_tx_empty(struct uart_port *port)
794 {
795 /* Can't detect */
796 return TIOCSER_TEMT;
797 }
798
799 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
800 {
801 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
802 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
803 /* If you have signals for DTR and DCD, please implement here. */
804 }
805
806 static unsigned int sci_get_mctrl(struct uart_port *port)
807 {
808 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
809 and CTS/RTS */
810
811 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
812 }
813
814 static void sci_start_tx(struct uart_port *port)
815 {
816 unsigned short ctrl;
817
818 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
819 ctrl = sci_in(port, SCSCR);
820 ctrl |= SCI_CTRL_FLAGS_TIE;
821 sci_out(port, SCSCR, ctrl);
822 }
823
824 static void sci_stop_tx(struct uart_port *port)
825 {
826 unsigned short ctrl;
827
828 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
829 ctrl = sci_in(port, SCSCR);
830 ctrl &= ~SCI_CTRL_FLAGS_TIE;
831 sci_out(port, SCSCR, ctrl);
832 }
833
834 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
835 {
836 unsigned short ctrl;
837
838 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
839 ctrl = sci_in(port, SCSCR);
840 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
841 sci_out(port, SCSCR, ctrl);
842 }
843
844 static void sci_stop_rx(struct uart_port *port)
845 {
846 unsigned short ctrl;
847
848 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
849 ctrl = sci_in(port, SCSCR);
850 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
851 sci_out(port, SCSCR, ctrl);
852 }
853
854 static void sci_enable_ms(struct uart_port *port)
855 {
856 /* Nothing here yet .. */
857 }
858
859 static void sci_break_ctl(struct uart_port *port, int break_state)
860 {
861 /* Nothing here yet .. */
862 }
863
864 static int sci_startup(struct uart_port *port)
865 {
866 struct sci_port *s = &sci_ports[port->line];
867
868 if (s->enable)
869 s->enable(port);
870
871 #ifdef CONFIG_HAVE_CLK
872 s->clk = clk_get(NULL, "module_clk");
873 #endif
874
875 sci_request_irq(s);
876 sci_start_tx(port);
877 sci_start_rx(port, 1);
878
879 return 0;
880 }
881
882 static void sci_shutdown(struct uart_port *port)
883 {
884 struct sci_port *s = &sci_ports[port->line];
885
886 sci_stop_rx(port);
887 sci_stop_tx(port);
888 sci_free_irq(s);
889
890 if (s->disable)
891 s->disable(port);
892
893 #ifdef CONFIG_HAVE_CLK
894 clk_put(s->clk);
895 s->clk = NULL;
896 #endif
897 }
898
899 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
900 struct ktermios *old)
901 {
902 unsigned int status, baud, smr_val;
903 int t = -1;
904
905 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
906 if (likely(baud))
907 t = SCBRR_VALUE(baud, port->uartclk);
908
909 do {
910 status = sci_in(port, SCxSR);
911 } while (!(status & SCxSR_TEND(port)));
912
913 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
914
915 if (port->type != PORT_SCI)
916 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
917
918 smr_val = sci_in(port, SCSMR) & 3;
919 if ((termios->c_cflag & CSIZE) == CS7)
920 smr_val |= 0x40;
921 if (termios->c_cflag & PARENB)
922 smr_val |= 0x20;
923 if (termios->c_cflag & PARODD)
924 smr_val |= 0x30;
925 if (termios->c_cflag & CSTOPB)
926 smr_val |= 0x08;
927
928 uart_update_timeout(port, termios->c_cflag, baud);
929
930 sci_out(port, SCSMR, smr_val);
931
932 if (t > 0) {
933 if (t >= 256) {
934 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
935 t >>= 2;
936 } else
937 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
938
939 sci_out(port, SCBRR, t);
940 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
941 }
942
943 sci_init_pins(port, termios->c_cflag);
944 sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
945
946 sci_out(port, SCSCR, SCSCR_INIT(port));
947
948 if ((termios->c_cflag & CREAD) != 0)
949 sci_start_rx(port, 0);
950 }
951
952 static const char *sci_type(struct uart_port *port)
953 {
954 switch (port->type) {
955 case PORT_IRDA:
956 return "irda";
957 case PORT_SCI:
958 return "sci";
959 case PORT_SCIF:
960 return "scif";
961 case PORT_SCIFA:
962 return "scifa";
963 }
964
965 return NULL;
966 }
967
968 static void sci_release_port(struct uart_port *port)
969 {
970 /* Nothing here yet .. */
971 }
972
973 static int sci_request_port(struct uart_port *port)
974 {
975 /* Nothing here yet .. */
976 return 0;
977 }
978
979 static void sci_config_port(struct uart_port *port, int flags)
980 {
981 struct sci_port *s = &sci_ports[port->line];
982
983 port->type = s->type;
984
985 if (port->flags & UPF_IOREMAP && !port->membase) {
986 #if defined(CONFIG_SUPERH64)
987 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
988 port->membase = (void __iomem *)port->mapbase;
989 #else
990 port->membase = ioremap_nocache(port->mapbase, 0x40);
991 #endif
992
993 dev_err(port->dev, "can't remap port#%d\n", port->line);
994 }
995 }
996
997 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
998 {
999 struct sci_port *s = &sci_ports[port->line];
1000
1001 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1002 return -EINVAL;
1003 if (ser->baud_base < 2400)
1004 /* No paper tape reader for Mitch.. */
1005 return -EINVAL;
1006
1007 return 0;
1008 }
1009
1010 static struct uart_ops sci_uart_ops = {
1011 .tx_empty = sci_tx_empty,
1012 .set_mctrl = sci_set_mctrl,
1013 .get_mctrl = sci_get_mctrl,
1014 .start_tx = sci_start_tx,
1015 .stop_tx = sci_stop_tx,
1016 .stop_rx = sci_stop_rx,
1017 .enable_ms = sci_enable_ms,
1018 .break_ctl = sci_break_ctl,
1019 .startup = sci_startup,
1020 .shutdown = sci_shutdown,
1021 .set_termios = sci_set_termios,
1022 .type = sci_type,
1023 .release_port = sci_release_port,
1024 .request_port = sci_request_port,
1025 .config_port = sci_config_port,
1026 .verify_port = sci_verify_port,
1027 #ifdef CONFIG_CONSOLE_POLL
1028 .poll_get_char = sci_poll_get_char,
1029 .poll_put_char = sci_poll_put_char,
1030 #endif
1031 };
1032
1033 static void __init sci_init_ports(void)
1034 {
1035 static int first = 1;
1036 int i;
1037
1038 if (!first)
1039 return;
1040
1041 first = 0;
1042
1043 for (i = 0; i < SCI_NPORTS; i++) {
1044 sci_ports[i].port.ops = &sci_uart_ops;
1045 sci_ports[i].port.iotype = UPIO_MEM;
1046 sci_ports[i].port.line = i;
1047 sci_ports[i].port.fifosize = 1;
1048
1049 #if defined(__H8300H__) || defined(__H8300S__)
1050 #ifdef __H8300S__
1051 sci_ports[i].enable = h8300_sci_enable;
1052 sci_ports[i].disable = h8300_sci_disable;
1053 #endif
1054 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1055 #elif defined(CONFIG_HAVE_CLK)
1056 /*
1057 * XXX: We should use a proper SCI/SCIF clock
1058 */
1059 {
1060 struct clk *clk = clk_get(NULL, "module_clk");
1061 sci_ports[i].port.uartclk = clk_get_rate(clk);
1062 clk_put(clk);
1063 }
1064 #else
1065 #error "Need a valid uartclk"
1066 #endif
1067
1068 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1069 sci_ports[i].break_timer.function = sci_break_timer;
1070
1071 init_timer(&sci_ports[i].break_timer);
1072 }
1073 }
1074
1075 int __init early_sci_setup(struct uart_port *port)
1076 {
1077 if (unlikely(port->line > SCI_NPORTS))
1078 return -ENODEV;
1079
1080 sci_init_ports();
1081
1082 sci_ports[port->line].port.membase = port->membase;
1083 sci_ports[port->line].port.mapbase = port->mapbase;
1084 sci_ports[port->line].port.type = port->type;
1085
1086 return 0;
1087 }
1088
1089 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1090 /*
1091 * Print a string to the serial port trying not to disturb
1092 * any possible real use of the port...
1093 */
1094 static void serial_console_write(struct console *co, const char *s,
1095 unsigned count)
1096 {
1097 struct uart_port *port = &serial_console_port->port;
1098 int i;
1099
1100 for (i = 0; i < count; i++) {
1101 if (*s == 10)
1102 sci_poll_put_char(port, '\r');
1103
1104 sci_poll_put_char(port, *s++);
1105 }
1106 }
1107
1108 static int __init serial_console_setup(struct console *co, char *options)
1109 {
1110 struct uart_port *port;
1111 int baud = 115200;
1112 int bits = 8;
1113 int parity = 'n';
1114 int flow = 'n';
1115 int ret;
1116
1117 /*
1118 * Check whether an invalid uart number has been specified, and
1119 * if so, search for the first available port that does have
1120 * console support.
1121 */
1122 if (co->index >= SCI_NPORTS)
1123 co->index = 0;
1124
1125 serial_console_port = &sci_ports[co->index];
1126 port = &serial_console_port->port;
1127
1128 /*
1129 * Also need to check port->type, we don't actually have any
1130 * UPIO_PORT ports, but uart_report_port() handily misreports
1131 * it anyways if we don't have a port available by the time this is
1132 * called.
1133 */
1134 if (!port->type)
1135 return -ENODEV;
1136 if (!port->membase || !port->mapbase)
1137 return -ENODEV;
1138
1139 port->type = serial_console_port->type;
1140
1141 #ifdef CONFIG_HAVE_CLK
1142 if (!serial_console_port->clk)
1143 serial_console_port->clk = clk_get(NULL, "module_clk");
1144 #endif
1145
1146 if (port->flags & UPF_IOREMAP)
1147 sci_config_port(port, 0);
1148
1149 if (serial_console_port->enable)
1150 serial_console_port->enable(port);
1151
1152 if (options)
1153 uart_parse_options(options, &baud, &parity, &bits, &flow);
1154
1155 ret = uart_set_options(port, co, baud, parity, bits, flow);
1156 #if defined(__H8300H__) || defined(__H8300S__)
1157 /* disable rx interrupt */
1158 if (ret == 0)
1159 sci_stop_rx(port);
1160 #endif
1161 return ret;
1162 }
1163
1164 static struct console serial_console = {
1165 .name = "ttySC",
1166 .device = uart_console_device,
1167 .write = serial_console_write,
1168 .setup = serial_console_setup,
1169 .flags = CON_PRINTBUFFER,
1170 .index = -1,
1171 .data = &sci_uart_driver,
1172 };
1173
1174 static int __init sci_console_init(void)
1175 {
1176 sci_init_ports();
1177 register_console(&serial_console);
1178 return 0;
1179 }
1180 console_initcall(sci_console_init);
1181 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1182
1183 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1184 #define SCI_CONSOLE (&serial_console)
1185 #else
1186 #define SCI_CONSOLE 0
1187 #endif
1188
1189 static char banner[] __initdata =
1190 KERN_INFO "SuperH SCI(F) driver initialized\n";
1191
1192 static struct uart_driver sci_uart_driver = {
1193 .owner = THIS_MODULE,
1194 .driver_name = "sci",
1195 .dev_name = "ttySC",
1196 .major = SCI_MAJOR,
1197 .minor = SCI_MINOR_START,
1198 .nr = SCI_NPORTS,
1199 .cons = SCI_CONSOLE,
1200 };
1201
1202 /*
1203 * Register a set of serial devices attached to a platform device. The
1204 * list is terminated with a zero flags entry, which means we expect
1205 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1206 * remapping (such as sh64) should also set UPF_IOREMAP.
1207 */
1208 static int __devinit sci_probe(struct platform_device *dev)
1209 {
1210 struct plat_sci_port *p = dev->dev.platform_data;
1211 int i, ret = -EINVAL;
1212
1213 for (i = 0; p && p->flags != 0; p++, i++) {
1214 struct sci_port *sciport = &sci_ports[i];
1215
1216 /* Sanity check */
1217 if (unlikely(i == SCI_NPORTS)) {
1218 dev_notice(&dev->dev, "Attempting to register port "
1219 "%d when only %d are available.\n",
1220 i+1, SCI_NPORTS);
1221 dev_notice(&dev->dev, "Consider bumping "
1222 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1223 break;
1224 }
1225
1226 sciport->port.mapbase = p->mapbase;
1227
1228 if (p->mapbase && !p->membase) {
1229 if (p->flags & UPF_IOREMAP) {
1230 p->membase = ioremap_nocache(p->mapbase, 0x40);
1231 if (IS_ERR(p->membase)) {
1232 ret = PTR_ERR(p->membase);
1233 goto err_unreg;
1234 }
1235 } else {
1236 /*
1237 * For the simple (and majority of) cases
1238 * where we don't need to do any remapping,
1239 * just cast the cookie directly.
1240 */
1241 p->membase = (void __iomem *)p->mapbase;
1242 }
1243 }
1244
1245 sciport->port.membase = p->membase;
1246
1247 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1248 sciport->port.flags = p->flags;
1249 sciport->port.dev = &dev->dev;
1250
1251 sciport->type = sciport->port.type = p->type;
1252
1253 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1254
1255 uart_add_one_port(&sci_uart_driver, &sciport->port);
1256 }
1257
1258 #ifdef CONFIG_HAVE_CLK
1259 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1260 #endif
1261
1262 #ifdef CONFIG_SH_STANDARD_BIOS
1263 sh_bios_gdb_detach();
1264 #endif
1265
1266 return 0;
1267
1268 err_unreg:
1269 for (i = i - 1; i >= 0; i--)
1270 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1271
1272 return ret;
1273 }
1274
1275 static int __devexit sci_remove(struct platform_device *dev)
1276 {
1277 int i;
1278
1279 #ifdef CONFIG_HAVE_CLK
1280 cpufreq_unregister_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1281 #endif
1282
1283 for (i = 0; i < SCI_NPORTS; i++)
1284 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1285
1286 return 0;
1287 }
1288
1289 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1290 {
1291 int i;
1292
1293 for (i = 0; i < SCI_NPORTS; i++) {
1294 struct sci_port *p = &sci_ports[i];
1295
1296 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1297 uart_suspend_port(&sci_uart_driver, &p->port);
1298 }
1299
1300 return 0;
1301 }
1302
1303 static int sci_resume(struct platform_device *dev)
1304 {
1305 int i;
1306
1307 for (i = 0; i < SCI_NPORTS; i++) {
1308 struct sci_port *p = &sci_ports[i];
1309
1310 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1311 uart_resume_port(&sci_uart_driver, &p->port);
1312 }
1313
1314 return 0;
1315 }
1316
1317 static struct platform_driver sci_driver = {
1318 .probe = sci_probe,
1319 .remove = __devexit_p(sci_remove),
1320 .suspend = sci_suspend,
1321 .resume = sci_resume,
1322 .driver = {
1323 .name = "sh-sci",
1324 .owner = THIS_MODULE,
1325 },
1326 };
1327
1328 static int __init sci_init(void)
1329 {
1330 int ret;
1331
1332 printk(banner);
1333
1334 sci_init_ports();
1335
1336 ret = uart_register_driver(&sci_uart_driver);
1337 if (likely(ret == 0)) {
1338 ret = platform_driver_register(&sci_driver);
1339 if (unlikely(ret))
1340 uart_unregister_driver(&sci_uart_driver);
1341 }
1342
1343 return ret;
1344 }
1345
1346 static void __exit sci_exit(void)
1347 {
1348 platform_driver_unregister(&sci_driver);
1349 uart_unregister_driver(&sci_uart_driver);
1350 }
1351
1352 module_init(sci_init);
1353 module_exit(sci_exit);
1354
1355 MODULE_LICENSE("GPL");
1356 MODULE_ALIAS("platform:sh-sci");
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK