?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / net / wireless / ath9k / hw.c
blobc38a00bbce64664caa1042be4ee37da97e1f6c46
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "core.h"
21 #include "hw.h"
22 #include "reg.h"
23 #include "phy.h"
24 #include "initvals.h"
25
26 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
27
28 extern struct hal_percal_data iq_cal_multi_sample;
29 extern struct hal_percal_data iq_cal_single_sample;
30 extern struct hal_percal_data adc_gain_cal_multi_sample;
31 extern struct hal_percal_data adc_gain_cal_single_sample;
32 extern struct hal_percal_data adc_dc_cal_multi_sample;
33 extern struct hal_percal_data adc_dc_cal_single_sample;
34 extern struct hal_percal_data adc_init_dc_cal;
35
36 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
37 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
38 enum ath9k_ht_macmode macmode);
39 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
40 struct ar5416_eeprom_def *pEepData,
41 u32 reg, u32 value);
42 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
43 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
44
45 /********************/
46 /* Helper Functions */
47 /********************/
48
49 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
50 {
51 if (ah->ah_curchan != NULL)
52 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
53 else
54 return clks / CLOCK_RATE[ATH9K_MODE_11B];
55 }
56
57 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
58 {
59 struct ath9k_channel *chan = ah->ah_curchan;
60
61 if (chan && IS_CHAN_HT40(chan))
62 return ath9k_hw_mac_usec(ah, clks) / 2;
63 else
64 return ath9k_hw_mac_usec(ah, clks);
65 }
66
67 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
68 {
69 if (ah->ah_curchan != NULL)
70 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
71 ah->ah_curchan)];
72 else
73 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
74 }
75
76 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
77 {
78 struct ath9k_channel *chan = ah->ah_curchan;
79
80 if (chan && IS_CHAN_HT40(chan))
81 return ath9k_hw_mac_clks(ah, usecs) * 2;
82 else
83 return ath9k_hw_mac_clks(ah, usecs);
84 }
85
86 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
87 const struct ath9k_channel *chan)
88 {
89 if (IS_CHAN_B(chan))
90 return ATH9K_MODE_11B;
91 if (IS_CHAN_G(chan))
92 return ATH9K_MODE_11G;
93
94 return ATH9K_MODE_11A;
95 }
96
97 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
98 {
99 int i;
100
101 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
102 if ((REG_READ(ah, reg) & mask) == val)
103 return true;
104
105 udelay(AH_TIME_QUANTUM);
106 }
107
108 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
109 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
110 reg, REG_READ(ah, reg), mask, val);
111
112 return false;
113 }
114
115 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
116 {
117 u32 retval;
118 int i;
119
120 for (i = 0, retval = 0; i < n; i++) {
121 retval = (retval << 1) | (val & 1);
122 val >>= 1;
123 }
124 return retval;
125 }
126
127 bool ath9k_get_channel_edges(struct ath_hal *ah,
128 u16 flags, u16 *low,
129 u16 *high)
130 {
131 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
132
133 if (flags & CHANNEL_5GHZ) {
134 *low = pCap->low_5ghz_chan;
135 *high = pCap->high_5ghz_chan;
136 return true;
137 }
138 if ((flags & CHANNEL_2GHZ)) {
139 *low = pCap->low_2ghz_chan;
140 *high = pCap->high_2ghz_chan;
141 return true;
142 }
143 return false;
144 }
145
146 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
147 struct ath_rate_table *rates,
148 u32 frameLen, u16 rateix,
149 bool shortPreamble)
150 {
151 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
152 u32 kbps;
153
154 kbps = rates->info[rateix].ratekbps;
155
156 if (kbps == 0)
157 return 0;
158
159 switch (rates->info[rateix].phy) {
160 case WLAN_RC_PHY_CCK:
161 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
162 if (shortPreamble && rates->info[rateix].short_preamble)
163 phyTime >>= 1;
164 numBits = frameLen << 3;
165 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
166 break;
167 case WLAN_RC_PHY_OFDM:
168 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
169 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
170 numBits = OFDM_PLCP_BITS + (frameLen << 3);
171 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
172 txTime = OFDM_SIFS_TIME_QUARTER
173 + OFDM_PREAMBLE_TIME_QUARTER
174 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
175 } else if (ah->ah_curchan &&
176 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
177 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
178 numBits = OFDM_PLCP_BITS + (frameLen << 3);
179 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
180 txTime = OFDM_SIFS_TIME_HALF +
181 OFDM_PREAMBLE_TIME_HALF
182 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
183 } else {
184 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
185 numBits = OFDM_PLCP_BITS + (frameLen << 3);
186 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
187 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
188 + (numSymbols * OFDM_SYMBOL_TIME);
189 }
190 break;
191 default:
192 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
193 "Unknown phy %u (rate ix %u)\n",
194 rates->info[rateix].phy, rateix);
195 txTime = 0;
196 break;
197 }
198
199 return txTime;
200 }
201
202 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
203 {
204 if (flags & CHANNEL_2GHZ) {
205 if (freq == 2484)
206 return 14;
207 if (freq < 2484)
208 return (freq - 2407) / 5;
209 else
210 return 15 + ((freq - 2512) / 20);
211 } else if (flags & CHANNEL_5GHZ) {
212 if (ath9k_regd_is_public_safety_sku(ah) &&
213 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
214 return ((freq * 10) +
215 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
216 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
217 return (freq - 4000) / 5;
218 } else {
219 return (freq - 5000) / 5;
220 }
221 } else {
222 if (freq == 2484)
223 return 14;
224 if (freq < 2484)
225 return (freq - 2407) / 5;
226 if (freq < 5000) {
227 if (ath9k_regd_is_public_safety_sku(ah)
228 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
229 return ((freq * 10) +
230 (((freq % 5) ==
231 2) ? 5 : 0) - 49400) / 5;
232 } else if (freq > 4900) {
233 return (freq - 4000) / 5;
234 } else {
235 return 15 + ((freq - 2512) / 20);
236 }
237 }
238 return (freq - 5000) / 5;
239 }
240 }
241
242 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
243 struct ath9k_channel *chan,
244 struct chan_centers *centers)
245 {
246 int8_t extoff;
247 struct ath_hal_5416 *ahp = AH5416(ah);
248
249 if (!IS_CHAN_HT40(chan)) {
250 centers->ctl_center = centers->ext_center =
251 centers->synth_center = chan->channel;
252 return;
253 }
254
255 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
256 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
257 centers->synth_center =
258 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
259 extoff = 1;
260 } else {
261 centers->synth_center =
262 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
263 extoff = -1;
264 }
265
266 centers->ctl_center =
267 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
268 centers->ext_center =
269 centers->synth_center + (extoff *
270 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
271 HT40_CHANNEL_CENTER_SHIFT : 15));
272
273 }
274
275 /******************/
276 /* Chip Revisions */
277 /******************/
278
279 static void ath9k_hw_read_revisions(struct ath_hal *ah)
280 {
281 u32 val;
282
283 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
284
285 if (val == 0xFF) {
286 val = REG_READ(ah, AR_SREV);
287 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
288 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
289 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
290 } else {
291 if (!AR_SREV_9100(ah))
292 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
293
294 ah->ah_macRev = val & AR_SREV_REVISION;
295
296 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
297 ah->ah_isPciExpress = true;
298 }
299 }
300
301 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
302 {
303 u32 val;
304 int i;
305
306 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
307
308 for (i = 0; i < 8; i++)
309 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
310 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
311 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
312
313 return ath9k_hw_reverse_bits(val, 8);
314 }
315
316 /************************************/
317 /* HW Attach, Detach, Init Routines */
318 /************************************/
319
320 static void ath9k_hw_disablepcie(struct ath_hal *ah)
321 {
322 if (!AR_SREV_9100(ah))
323 return;
324
325 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
327 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
328 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
329 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
330 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
332 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
334
335 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
336 }
337
338 static bool ath9k_hw_chip_test(struct ath_hal *ah)
339 {
340 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
341 u32 regHold[2];
342 u32 patternData[4] = { 0x55555555,
343 0xaaaaaaaa,
344 0x66666666,
345 0x99999999 };
346 int i, j;
347
348 for (i = 0; i < 2; i++) {
349 u32 addr = regAddr[i];
350 u32 wrData, rdData;
351
352 regHold[i] = REG_READ(ah, addr);
353 for (j = 0; j < 0x100; j++) {
354 wrData = (j << 16) | j;
355 REG_WRITE(ah, addr, wrData);
356 rdData = REG_READ(ah, addr);
357 if (rdData != wrData) {
358 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
359 "address test failed "
360 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
361 addr, wrData, rdData);
362 return false;
363 }
364 }
365 for (j = 0; j < 4; j++) {
366 wrData = patternData[j];
367 REG_WRITE(ah, addr, wrData);
368 rdData = REG_READ(ah, addr);
369 if (wrData != rdData) {
370 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
371 "address test failed "
372 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
373 addr, wrData, rdData);
374 return false;
375 }
376 }
377 REG_WRITE(ah, regAddr[i], regHold[i]);
378 }
379 udelay(100);
380 return true;
381 }
382
383 static const char *ath9k_hw_devname(u16 devid)
384 {
385 switch (devid) {
386 case AR5416_DEVID_PCI:
387 return "Atheros 5416";
388 case AR5416_DEVID_PCIE:
389 return "Atheros 5418";
390 case AR9160_DEVID_PCI:
391 return "Atheros 9160";
392 case AR9280_DEVID_PCI:
393 case AR9280_DEVID_PCIE:
394 return "Atheros 9280";
395 case AR9285_DEVID_PCIE:
396 return "Atheros 9285";
397 }
398
399 return NULL;
400 }
401
402 static void ath9k_hw_set_defaults(struct ath_hal *ah)
403 {
404 int i;
405
406 ah->ah_config.dma_beacon_response_time = 2;
407 ah->ah_config.sw_beacon_response_time = 10;
408 ah->ah_config.additional_swba_backoff = 0;
409 ah->ah_config.ack_6mb = 0x0;
410 ah->ah_config.cwm_ignore_extcca = 0;
411 ah->ah_config.pcie_powersave_enable = 0;
412 ah->ah_config.pcie_l1skp_enable = 0;
413 ah->ah_config.pcie_clock_req = 0;
414 ah->ah_config.pcie_power_reset = 0x100;
415 ah->ah_config.pcie_restore = 0;
416 ah->ah_config.pcie_waen = 0;
417 ah->ah_config.analog_shiftreg = 1;
418 ah->ah_config.ht_enable = 1;
419 ah->ah_config.ofdm_trig_low = 200;
420 ah->ah_config.ofdm_trig_high = 500;
421 ah->ah_config.cck_trig_high = 200;
422 ah->ah_config.cck_trig_low = 100;
423 ah->ah_config.enable_ani = 1;
424 ah->ah_config.noise_immunity_level = 4;
425 ah->ah_config.ofdm_weaksignal_det = 1;
426 ah->ah_config.cck_weaksignal_thr = 0;
427 ah->ah_config.spur_immunity_level = 2;
428 ah->ah_config.firstep_level = 0;
429 ah->ah_config.rssi_thr_high = 40;
430 ah->ah_config.rssi_thr_low = 7;
431 ah->ah_config.diversity_control = 0;
432 ah->ah_config.antenna_switch_swap = 0;
433
434 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
435 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
436 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
437 }
438
439 ah->ah_config.intr_mitigation = 1;
440
441 /*
442 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
443 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
444 * This means we use it for all AR5416 devices, and the few
445 * minor PCI AR9280 devices out there.
446 *
447 * Serialization is required because these devices do not handle
448 * well the case of two concurrent reads/writes due to the latency
449 * involved. During one read/write another read/write can be issued
450 * on another CPU while the previous read/write may still be working
451 * on our hardware, if we hit this case the hardware poops in a loop.
452 * We prevent this by serializing reads and writes.
453 *
454 * This issue is not present on PCI-Express devices or pre-AR5416
455 * devices (legacy, 802.11abg).
456 */
457 if (num_possible_cpus() > 1)
458 ah->ah_config.serialize_regmode = SER_REG_MODE_AUTO;
459 }
460
461 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
462 struct ath_softc *sc,
463 void __iomem *mem,
464 int *status)
465 {
466 static const u8 defbssidmask[ETH_ALEN] =
467 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
468 struct ath_hal_5416 *ahp;
469 struct ath_hal *ah;
470
471 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
472 if (ahp == NULL) {
473 DPRINTF(sc, ATH_DBG_FATAL,
474 "Cannot allocate memory for state block\n");
475 *status = -ENOMEM;
476 return NULL;
477 }
478
479 ah = &ahp->ah;
480 ah->ah_sc = sc;
481 ah->ah_sh = mem;
482 ah->ah_magic = AR5416_MAGIC;
483 ah->ah_countryCode = CTRY_DEFAULT;
484 ah->ah_devid = devid;
485 ah->ah_subvendorid = 0;
486
487 ah->ah_flags = 0;
488 if ((devid == AR5416_AR9100_DEVID))
489 ah->ah_macVersion = AR_SREV_VERSION_9100;
490 if (!AR_SREV_9100(ah))
491 ah->ah_flags = AH_USE_EEPROM;
492
493 ah->ah_powerLimit = MAX_RATE_POWER;
494 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
495 ahp->ah_atimWindow = 0;
496 ahp->ah_diversityControl = ah->ah_config.diversity_control;
497 ahp->ah_antennaSwitchSwap =
498 ah->ah_config.antenna_switch_swap;
499 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
500 ahp->ah_beaconInterval = 100;
501 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
502 ahp->ah_slottime = (u32) -1;
503 ahp->ah_acktimeout = (u32) -1;
504 ahp->ah_ctstimeout = (u32) -1;
505 ahp->ah_globaltxtimeout = (u32) -1;
506 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
507
508 ahp->ah_gBeaconRate = 0;
509
510 return ahp;
511 }
512
513 static int ath9k_hw_rfattach(struct ath_hal *ah)
514 {
515 bool rfStatus = false;
516 int ecode = 0;
517
518 rfStatus = ath9k_hw_init_rf(ah, &ecode);
519 if (!rfStatus) {
520 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
521 "RF setup failed, status %u\n", ecode);
522 return ecode;
523 }
524
525 return 0;
526 }
527
528 static int ath9k_hw_rf_claim(struct ath_hal *ah)
529 {
530 u32 val;
531
532 REG_WRITE(ah, AR_PHY(0), 0x00000007);
533
534 val = ath9k_hw_get_radiorev(ah);
535 switch (val & AR_RADIO_SREV_MAJOR) {
536 case 0:
537 val = AR_RAD5133_SREV_MAJOR;
538 break;
539 case AR_RAD5133_SREV_MAJOR:
540 case AR_RAD5122_SREV_MAJOR:
541 case AR_RAD2133_SREV_MAJOR:
542 case AR_RAD2122_SREV_MAJOR:
543 break;
544 default:
545 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
546 "5G Radio Chip Rev 0x%02X is not "
547 "supported by this driver\n",
548 ah->ah_analog5GhzRev);
549 return -EOPNOTSUPP;
550 }
551
552 ah->ah_analog5GhzRev = val;
553
554 return 0;
555 }
556
557 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
558 {
559 u32 sum;
560 int i;
561 u16 eeval;
562 struct ath_hal_5416 *ahp = AH5416(ah);
563
564 sum = 0;
565 for (i = 0; i < 3; i++) {
566 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
567 sum += eeval;
568 ahp->ah_macaddr[2 * i] = eeval >> 8;
569 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
570 }
571 if (sum == 0 || sum == 0xffff * 3) {
572 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
573 "mac address read failed: %pM\n",
574 ahp->ah_macaddr);
575 return -EADDRNOTAVAIL;
576 }
577
578 return 0;
579 }
580
581 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
582 {
583 u32 rxgain_type;
584 struct ath_hal_5416 *ahp = AH5416(ah);
585
586 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
587 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
588
589 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
590 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
591 ar9280Modes_backoff_13db_rxgain_9280_2,
592 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
593 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
594 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
595 ar9280Modes_backoff_23db_rxgain_9280_2,
596 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
597 else
598 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
599 ar9280Modes_original_rxgain_9280_2,
600 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
601 } else
602 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
603 ar9280Modes_original_rxgain_9280_2,
604 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
605 }
606
607 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
608 {
609 u32 txgain_type;
610 struct ath_hal_5416 *ahp = AH5416(ah);
611
612 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
613 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
614
615 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
616 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
617 ar9280Modes_high_power_tx_gain_9280_2,
618 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
619 else
620 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
621 ar9280Modes_original_tx_gain_9280_2,
622 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
623 } else
624 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
625 ar9280Modes_original_tx_gain_9280_2,
626 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
627 }
628
629 static int ath9k_hw_post_attach(struct ath_hal *ah)
630 {
631 int ecode;
632
633 if (!ath9k_hw_chip_test(ah)) {
634 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
635 "hardware self-test failed\n");
636 return -ENODEV;
637 }
638
639 ecode = ath9k_hw_rf_claim(ah);
640 if (ecode != 0)
641 return ecode;
642
643 ecode = ath9k_hw_eeprom_attach(ah);
644 if (ecode != 0)
645 return ecode;
646 ecode = ath9k_hw_rfattach(ah);
647 if (ecode != 0)
648 return ecode;
649
650 if (!AR_SREV_9100(ah)) {
651 ath9k_hw_ani_setup(ah);
652 ath9k_hw_ani_attach(ah);
653 }
654
655 return 0;
656 }
657
658 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
659 void __iomem *mem, int *status)
660 {
661 struct ath_hal_5416 *ahp;
662 struct ath_hal *ah;
663 int ecode;
664 u32 i, j;
665
666 ahp = ath9k_hw_newstate(devid, sc, mem, status);
667 if (ahp == NULL)
668 return NULL;
669
670 ah = &ahp->ah;
671
672 ath9k_hw_set_defaults(ah);
673
674 if (ah->ah_config.intr_mitigation != 0)
675 ahp->ah_intrMitigation = true;
676
677 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
678 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
679 ecode = -EIO;
680 goto bad;
681 }
682
683 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
684 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
685 ecode = -EIO;
686 goto bad;
687 }
688
689 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
690 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI ||
691 (AR_SREV_9280(ah) && !ah->ah_isPciExpress)) {
692 ah->ah_config.serialize_regmode =
693 SER_REG_MODE_ON;
694 } else {
695 ah->ah_config.serialize_regmode =
696 SER_REG_MODE_OFF;
697 }
698 }
699
700 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
701 "serialize_regmode is %d\n",
702 ah->ah_config.serialize_regmode);
703
704 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
705 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
706 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
707 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
708 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
709 "Mac Chip Rev 0x%02x.%x is not supported by "
710 "this driver\n", ah->ah_macVersion, ah->ah_macRev);
711 ecode = -EOPNOTSUPP;
712 goto bad;
713 }
714
715 if (AR_SREV_9100(ah)) {
716 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
717 ahp->ah_suppCals = IQ_MISMATCH_CAL;
718 ah->ah_isPciExpress = false;
719 }
720 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
721
722 if (AR_SREV_9160_10_OR_LATER(ah)) {
723 if (AR_SREV_9280_10_OR_LATER(ah)) {
724 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
725 ahp->ah_adcGainCalData.calData =
726 &adc_gain_cal_single_sample;
727 ahp->ah_adcDcCalData.calData =
728 &adc_dc_cal_single_sample;
729 ahp->ah_adcDcCalInitData.calData =
730 &adc_init_dc_cal;
731 } else {
732 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
733 ahp->ah_adcGainCalData.calData =
734 &adc_gain_cal_multi_sample;
735 ahp->ah_adcDcCalData.calData =
736 &adc_dc_cal_multi_sample;
737 ahp->ah_adcDcCalInitData.calData =
738 &adc_init_dc_cal;
739 }
740 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
741 }
742
743 if (AR_SREV_9160(ah)) {
744 ah->ah_config.enable_ani = 1;
745 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
746 ATH9K_ANI_FIRSTEP_LEVEL);
747 } else {
748 ahp->ah_ani_function = ATH9K_ANI_ALL;
749 if (AR_SREV_9280_10_OR_LATER(ah)) {
750 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
751 }
752 }
753
754 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
755 "This Mac Chip Rev 0x%02x.%x is \n",
756 ah->ah_macVersion, ah->ah_macRev);
757
758 if (AR_SREV_9285_12_OR_LATER(ah)) {
759 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
760 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
761 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
762 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
763
764 if (ah->ah_config.pcie_clock_req) {
765 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
766 ar9285PciePhy_clkreq_off_L1_9285_1_2,
767 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
768 } else {
769 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
770 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
771 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
772 2);
773 }
774 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
775 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
776 ARRAY_SIZE(ar9285Modes_9285), 6);
777 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
778 ARRAY_SIZE(ar9285Common_9285), 2);
779
780 if (ah->ah_config.pcie_clock_req) {
781 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
782 ar9285PciePhy_clkreq_off_L1_9285,
783 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
784 } else {
785 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
786 ar9285PciePhy_clkreq_always_on_L1_9285,
787 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
788 }
789 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
790 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
791 ARRAY_SIZE(ar9280Modes_9280_2), 6);
792 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
793 ARRAY_SIZE(ar9280Common_9280_2), 2);
794
795 if (ah->ah_config.pcie_clock_req) {
796 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
797 ar9280PciePhy_clkreq_off_L1_9280,
798 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
799 } else {
800 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
801 ar9280PciePhy_clkreq_always_on_L1_9280,
802 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
803 }
804 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
805 ar9280Modes_fast_clock_9280_2,
806 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
807 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
808 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
809 ARRAY_SIZE(ar9280Modes_9280), 6);
810 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
811 ARRAY_SIZE(ar9280Common_9280), 2);
812 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
813 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
814 ARRAY_SIZE(ar5416Modes_9160), 6);
815 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
816 ARRAY_SIZE(ar5416Common_9160), 2);
817 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
818 ARRAY_SIZE(ar5416Bank0_9160), 2);
819 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
820 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
821 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
822 ARRAY_SIZE(ar5416Bank1_9160), 2);
823 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
824 ARRAY_SIZE(ar5416Bank2_9160), 2);
825 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
826 ARRAY_SIZE(ar5416Bank3_9160), 3);
827 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
828 ARRAY_SIZE(ar5416Bank6_9160), 3);
829 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
830 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
831 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
832 ARRAY_SIZE(ar5416Bank7_9160), 2);
833 if (AR_SREV_9160_11(ah)) {
834 INIT_INI_ARRAY(&ahp->ah_iniAddac,
835 ar5416Addac_91601_1,
836 ARRAY_SIZE(ar5416Addac_91601_1), 2);
837 } else {
838 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
839 ARRAY_SIZE(ar5416Addac_9160), 2);
840 }
841 } else if (AR_SREV_9100_OR_LATER(ah)) {
842 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
843 ARRAY_SIZE(ar5416Modes_9100), 6);
844 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
845 ARRAY_SIZE(ar5416Common_9100), 2);
846 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
847 ARRAY_SIZE(ar5416Bank0_9100), 2);
848 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
849 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
850 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
851 ARRAY_SIZE(ar5416Bank1_9100), 2);
852 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
853 ARRAY_SIZE(ar5416Bank2_9100), 2);
854 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
855 ARRAY_SIZE(ar5416Bank3_9100), 3);
856 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
857 ARRAY_SIZE(ar5416Bank6_9100), 3);
858 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
859 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
860 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
861 ARRAY_SIZE(ar5416Bank7_9100), 2);
862 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
863 ARRAY_SIZE(ar5416Addac_9100), 2);
864 } else {
865 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
866 ARRAY_SIZE(ar5416Modes), 6);
867 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
868 ARRAY_SIZE(ar5416Common), 2);
869 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
870 ARRAY_SIZE(ar5416Bank0), 2);
871 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
872 ARRAY_SIZE(ar5416BB_RfGain), 3);
873 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
874 ARRAY_SIZE(ar5416Bank1), 2);
875 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
876 ARRAY_SIZE(ar5416Bank2), 2);
877 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
878 ARRAY_SIZE(ar5416Bank3), 3);
879 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
880 ARRAY_SIZE(ar5416Bank6), 3);
881 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
882 ARRAY_SIZE(ar5416Bank6TPC), 3);
883 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
884 ARRAY_SIZE(ar5416Bank7), 2);
885 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
886 ARRAY_SIZE(ar5416Addac), 2);
887 }
888
889 if (ah->ah_isPciExpress)
890 ath9k_hw_configpcipowersave(ah, 0);
891 else
892 ath9k_hw_disablepcie(ah);
893
894 ecode = ath9k_hw_post_attach(ah);
895 if (ecode != 0)
896 goto bad;
897
898 /* rxgain table */
899 if (AR_SREV_9280_20(ah))
900 ath9k_hw_init_rxgain_ini(ah);
901
902 /* txgain table */
903 if (AR_SREV_9280_20(ah))
904 ath9k_hw_init_txgain_ini(ah);
905
906 if (ah->ah_devid == AR9280_DEVID_PCI) {
907 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
908 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
909
910 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
911 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
912
913 INI_RA(&ahp->ah_iniModes, i, j) =
914 ath9k_hw_ini_fixup(ah,
915 &ahp->ah_eeprom.def,
916 reg, val);
917 }
918 }
919 }
920
921 if (!ath9k_hw_fill_cap_info(ah)) {
922 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
923 "failed ath9k_hw_fill_cap_info\n");
924 ecode = -EINVAL;
925 goto bad;
926 }
927
928 ecode = ath9k_hw_init_macaddr(ah);
929 if (ecode != 0) {
930 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
931 "failed initializing mac address\n");
932 goto bad;
933 }
934
935 if (AR_SREV_9285(ah))
936 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
937 else
938 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
939
940 ath9k_init_nfcal_hist_buffer(ah);
941
942 return ah;
943 bad:
944 if (ahp)
945 ath9k_hw_detach((struct ath_hal *) ahp);
946 if (status)
947 *status = ecode;
948
949 return NULL;
950 }
951
952 static void ath9k_hw_init_bb(struct ath_hal *ah,
953 struct ath9k_channel *chan)
954 {
955 u32 synthDelay;
956
957 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
958 if (IS_CHAN_B(chan))
959 synthDelay = (4 * synthDelay) / 22;
960 else
961 synthDelay /= 10;
962
963 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
964
965 udelay(synthDelay + BASE_ACTIVATE_DELAY);
966 }
967
968 static void ath9k_hw_init_qos(struct ath_hal *ah)
969 {
970 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
971 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
972
973 REG_WRITE(ah, AR_QOS_NO_ACK,
974 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
975 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
976 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
977
978 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
979 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
980 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
981 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
982 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
983 }
984
985 static void ath9k_hw_init_pll(struct ath_hal *ah,
986 struct ath9k_channel *chan)
987 {
988 u32 pll;
989
990 if (AR_SREV_9100(ah)) {
991 if (chan && IS_CHAN_5GHZ(chan))
992 pll = 0x1450;
993 else
994 pll = 0x1458;
995 } else {
996 if (AR_SREV_9280_10_OR_LATER(ah)) {
997 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
998
999 if (chan && IS_CHAN_HALF_RATE(chan))
1000 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1001 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1002 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1003
1004 if (chan && IS_CHAN_5GHZ(chan)) {
1005 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1006
1007
1008 if (AR_SREV_9280_20(ah)) {
1009 if (((chan->channel % 20) == 0)
1010 || ((chan->channel % 10) == 0))
1011 pll = 0x2850;
1012 else
1013 pll = 0x142c;
1014 }
1015 } else {
1016 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1017 }
1018
1019 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1020
1021 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1022
1023 if (chan && IS_CHAN_HALF_RATE(chan))
1024 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1025 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1026 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1027
1028 if (chan && IS_CHAN_5GHZ(chan))
1029 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1030 else
1031 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1032 } else {
1033 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1034
1035 if (chan && IS_CHAN_HALF_RATE(chan))
1036 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1037 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1038 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1039
1040 if (chan && IS_CHAN_5GHZ(chan))
1041 pll |= SM(0xa, AR_RTC_PLL_DIV);
1042 else
1043 pll |= SM(0xb, AR_RTC_PLL_DIV);
1044 }
1045 }
1046 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1047
1048 udelay(RTC_PLL_SETTLE_DELAY);
1049
1050 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1051 }
1052
1053 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1054 {
1055 struct ath_hal_5416 *ahp = AH5416(ah);
1056 int rx_chainmask, tx_chainmask;
1057
1058 rx_chainmask = ahp->ah_rxchainmask;
1059 tx_chainmask = ahp->ah_txchainmask;
1060
1061 switch (rx_chainmask) {
1062 case 0x5:
1063 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1064 AR_PHY_SWAP_ALT_CHAIN);
1065 case 0x3:
1066 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1067 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1068 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1069 break;
1070 }
1071 case 0x1:
1072 case 0x2:
1073 case 0x7:
1074 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1075 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1076 break;
1077 default:
1078 break;
1079 }
1080
1081 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1082 if (tx_chainmask == 0x5) {
1083 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1084 AR_PHY_SWAP_ALT_CHAIN);
1085 }
1086 if (AR_SREV_9100(ah))
1087 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1088 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1089 }
1090
1091 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1092 enum nl80211_iftype opmode)
1093 {
1094 struct ath_hal_5416 *ahp = AH5416(ah);
1095
1096 ahp->ah_maskReg = AR_IMR_TXERR |
1097 AR_IMR_TXURN |
1098 AR_IMR_RXERR |
1099 AR_IMR_RXORN |
1100 AR_IMR_BCNMISC;
1101
1102 if (ahp->ah_intrMitigation)
1103 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1104 else
1105 ahp->ah_maskReg |= AR_IMR_RXOK;
1106
1107 ahp->ah_maskReg |= AR_IMR_TXOK;
1108
1109 if (opmode == NL80211_IFTYPE_AP)
1110 ahp->ah_maskReg |= AR_IMR_MIB;
1111
1112 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1113 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1114
1115 if (!AR_SREV_9100(ah)) {
1116 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1117 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1118 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1119 }
1120 }
1121
1122 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1123 {
1124 struct ath_hal_5416 *ahp = AH5416(ah);
1125
1126 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1127 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1128 ahp->ah_acktimeout = (u32) -1;
1129 return false;
1130 } else {
1131 REG_RMW_FIELD(ah, AR_TIME_OUT,
1132 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1133 ahp->ah_acktimeout = us;
1134 return true;
1135 }
1136 }
1137
1138 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1139 {
1140 struct ath_hal_5416 *ahp = AH5416(ah);
1141
1142 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1143 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1144 ahp->ah_ctstimeout = (u32) -1;
1145 return false;
1146 } else {
1147 REG_RMW_FIELD(ah, AR_TIME_OUT,
1148 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1149 ahp->ah_ctstimeout = us;
1150 return true;
1151 }
1152 }
1153
1154 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1155 {
1156 struct ath_hal_5416 *ahp = AH5416(ah);
1157
1158 if (tu > 0xFFFF) {
1159 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1160 "bad global tx timeout %u\n", tu);
1161 ahp->ah_globaltxtimeout = (u32) -1;
1162 return false;
1163 } else {
1164 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1165 ahp->ah_globaltxtimeout = tu;
1166 return true;
1167 }
1168 }
1169
1170 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1171 {
1172 struct ath_hal_5416 *ahp = AH5416(ah);
1173
1174 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1175 ahp->ah_miscMode);
1176
1177 if (ahp->ah_miscMode != 0)
1178 REG_WRITE(ah, AR_PCU_MISC,
1179 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1180 if (ahp->ah_slottime != (u32) -1)
1181 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1182 if (ahp->ah_acktimeout != (u32) -1)
1183 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1184 if (ahp->ah_ctstimeout != (u32) -1)
1185 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1186 if (ahp->ah_globaltxtimeout != (u32) -1)
1187 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1188 }
1189
1190 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1191 {
1192 return vendorid == ATHEROS_VENDOR_ID ?
1193 ath9k_hw_devname(devid) : NULL;
1194 }
1195
1196 void ath9k_hw_detach(struct ath_hal *ah)
1197 {
1198 if (!AR_SREV_9100(ah))
1199 ath9k_hw_ani_detach(ah);
1200
1201 ath9k_hw_rfdetach(ah);
1202 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1203 kfree(ah);
1204 }
1205
1206 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1207 void __iomem *mem, int *error)
1208 {
1209 struct ath_hal *ah = NULL;
1210
1211 switch (devid) {
1212 case AR5416_DEVID_PCI:
1213 case AR5416_DEVID_PCIE:
1214 case AR9160_DEVID_PCI:
1215 case AR9280_DEVID_PCI:
1216 case AR9280_DEVID_PCIE:
1217 case AR9285_DEVID_PCIE:
1218 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1219 break;
1220 default:
1221 *error = -ENXIO;
1222 break;
1223 }
1224
1225 return ah;
1226 }
1227
1228 /*******/
1229 /* INI */
1230 /*******/
1231
1232 static void ath9k_hw_override_ini(struct ath_hal *ah,
1233 struct ath9k_channel *chan)
1234 {
1235 /*
1236 * Set the RX_ABORT and RX_DIS and clear if off only after
1237 * RXE is set for MAC. This prevents frames with corrupted
1238 * descriptor status.
1239 */
1240 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1241
1242
1243 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1244 AR_SREV_9280_10_OR_LATER(ah))
1245 return;
1246
1247 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1248 }
1249
1250 static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1251 struct ar5416_eeprom_def *pEepData,
1252 u32 reg, u32 value)
1253 {
1254 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1255
1256 switch (ah->ah_devid) {
1257 case AR9280_DEVID_PCI:
1258 if (reg == 0x7894) {
1259 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1260 "ini VAL: %x EEPROM: %x\n", value,
1261 (pBase->version & 0xff));
1262
1263 if ((pBase->version & 0xff) > 0x0a) {
1264 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1265 "PWDCLKIND: %d\n",
1266 pBase->pwdclkind);
1267 value &= ~AR_AN_TOP2_PWDCLKIND;
1268 value |= AR_AN_TOP2_PWDCLKIND &
1269 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1270 } else {
1271 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1272 "PWDCLKIND Earlier Rev\n");
1273 }
1274
1275 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1276 "final ini VAL: %x\n", value);
1277 }
1278 break;
1279 }
1280
1281 return value;
1282 }
1283
1284 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1285 struct ar5416_eeprom_def *pEepData,
1286 u32 reg, u32 value)
1287 {
1288 struct ath_hal_5416 *ahp = AH5416(ah);
1289
1290 if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1291 return value;
1292 else
1293 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1294 }
1295
1296 static int ath9k_hw_process_ini(struct ath_hal *ah,
1297 struct ath9k_channel *chan,
1298 enum ath9k_ht_macmode macmode)
1299 {
1300 int i, regWrites = 0;
1301 struct ath_hal_5416 *ahp = AH5416(ah);
1302 u32 modesIndex, freqIndex;
1303 int status;
1304
1305 switch (chan->chanmode) {
1306 case CHANNEL_A:
1307 case CHANNEL_A_HT20:
1308 modesIndex = 1;
1309 freqIndex = 1;
1310 break;
1311 case CHANNEL_A_HT40PLUS:
1312 case CHANNEL_A_HT40MINUS:
1313 modesIndex = 2;
1314 freqIndex = 1;
1315 break;
1316 case CHANNEL_G:
1317 case CHANNEL_G_HT20:
1318 case CHANNEL_B:
1319 modesIndex = 4;
1320 freqIndex = 2;
1321 break;
1322 case CHANNEL_G_HT40PLUS:
1323 case CHANNEL_G_HT40MINUS:
1324 modesIndex = 3;
1325 freqIndex = 2;
1326 break;
1327
1328 default:
1329 return -EINVAL;
1330 }
1331
1332 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1333
1334 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1335
1336 ath9k_hw_set_addac(ah, chan);
1337
1338 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1339 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1340 } else {
1341 struct ar5416IniArray temp;
1342 u32 addacSize =
1343 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1344 ahp->ah_iniAddac.ia_columns;
1345
1346 memcpy(ahp->ah_addac5416_21,
1347 ahp->ah_iniAddac.ia_array, addacSize);
1348
1349 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1350
1351 temp.ia_array = ahp->ah_addac5416_21;
1352 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1353 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1354 REG_WRITE_ARRAY(&temp, 1, regWrites);
1355 }
1356
1357 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1358
1359 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1360 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1361 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1362
1363 REG_WRITE(ah, reg, val);
1364
1365 if (reg >= 0x7800 && reg < 0x78a0
1366 && ah->ah_config.analog_shiftreg) {
1367 udelay(100);
1368 }
1369
1370 DO_DELAY(regWrites);
1371 }
1372
1373 if (AR_SREV_9280(ah))
1374 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1375
1376 if (AR_SREV_9280(ah))
1377 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1378
1379 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1380 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1381 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1382
1383 REG_WRITE(ah, reg, val);
1384
1385 if (reg >= 0x7800 && reg < 0x78a0
1386 && ah->ah_config.analog_shiftreg) {
1387 udelay(100);
1388 }
1389
1390 DO_DELAY(regWrites);
1391 }
1392
1393 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1394
1395 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1396 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1397 regWrites);
1398 }
1399
1400 ath9k_hw_override_ini(ah, chan);
1401 ath9k_hw_set_regs(ah, chan, macmode);
1402 ath9k_hw_init_chain_masks(ah);
1403
1404 status = ath9k_hw_set_txpower(ah, chan,
1405 ath9k_regd_get_ctl(ah, chan),
1406 ath9k_regd_get_antenna_allowed(ah,
1407 chan),
1408 chan->maxRegTxPower * 2,
1409 min((u32) MAX_RATE_POWER,
1410 (u32) ah->ah_powerLimit));
1411 if (status != 0) {
1412 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1413 "error init'ing transmit power\n");
1414 return -EIO;
1415 }
1416
1417 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1418 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1419 "ar5416SetRfRegs failed\n");
1420 return -EIO;
1421 }
1422
1423 return 0;
1424 }
1425
1426 /****************************************/
1427 /* Reset and Channel Switching Routines */
1428 /****************************************/
1429
1430 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1431 {
1432 u32 rfMode = 0;
1433
1434 if (chan == NULL)
1435 return;
1436
1437 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1438 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1439
1440 if (!AR_SREV_9280_10_OR_LATER(ah))
1441 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1442 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1443
1444 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1445 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1446
1447 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1448 }
1449
1450 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1451 {
1452 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1453 }
1454
1455 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1456 {
1457 u32 regval;
1458
1459 regval = REG_READ(ah, AR_AHB_MODE);
1460 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1461
1462 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1463 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1464
1465 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1466
1467 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1468 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1469
1470 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1471
1472 if (AR_SREV_9285(ah)) {
1473 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1474 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1475 } else {
1476 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1477 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1478 }
1479 }
1480
1481 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1482 {
1483 u32 val;
1484
1485 val = REG_READ(ah, AR_STA_ID1);
1486 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1487 switch (opmode) {
1488 case NL80211_IFTYPE_AP:
1489 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1490 | AR_STA_ID1_KSRCH_MODE);
1491 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1492 break;
1493 case NL80211_IFTYPE_ADHOC:
1494 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1495 | AR_STA_ID1_KSRCH_MODE);
1496 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1497 break;
1498 case NL80211_IFTYPE_STATION:
1499 case NL80211_IFTYPE_MONITOR:
1500 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1501 break;
1502 }
1503 }
1504
1505 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1506 u32 coef_scaled,
1507 u32 *coef_mantissa,
1508 u32 *coef_exponent)
1509 {
1510 u32 coef_exp, coef_man;
1511
1512 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1513 if ((coef_scaled >> coef_exp) & 0x1)
1514 break;
1515
1516 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1517
1518 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1519
1520 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1521 *coef_exponent = coef_exp - 16;
1522 }
1523
1524 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1525 struct ath9k_channel *chan)
1526 {
1527 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1528 u32 clockMhzScaled = 0x64000000;
1529 struct chan_centers centers;
1530
1531 if (IS_CHAN_HALF_RATE(chan))
1532 clockMhzScaled = clockMhzScaled >> 1;
1533 else if (IS_CHAN_QUARTER_RATE(chan))
1534 clockMhzScaled = clockMhzScaled >> 2;
1535
1536 ath9k_hw_get_channel_centers(ah, chan, &centers);
1537 coef_scaled = clockMhzScaled / centers.synth_center;
1538
1539 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1540 &ds_coef_exp);
1541
1542 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1543 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1544 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1545 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1546
1547 coef_scaled = (9 * coef_scaled) / 10;
1548
1549 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1550 &ds_coef_exp);
1551
1552 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1553 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1554 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1555 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1556 }
1557
1558 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1559 {
1560 u32 rst_flags;
1561 u32 tmpReg;
1562
1563 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1564 AR_RTC_FORCE_WAKE_ON_INT);
1565
1566 if (AR_SREV_9100(ah)) {
1567 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1568 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1569 } else {
1570 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1571 if (tmpReg &
1572 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1573 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1574 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1575 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1576 } else {
1577 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1578 }
1579
1580 rst_flags = AR_RTC_RC_MAC_WARM;
1581 if (type == ATH9K_RESET_COLD)
1582 rst_flags |= AR_RTC_RC_MAC_COLD;
1583 }
1584
1585 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1586 udelay(50);
1587
1588 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1589 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1590 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1591 "RTC stuck in MAC reset\n");
1592 return false;
1593 }
1594
1595 if (!AR_SREV_9100(ah))
1596 REG_WRITE(ah, AR_RC, 0);
1597
1598 ath9k_hw_init_pll(ah, NULL);
1599
1600 if (AR_SREV_9100(ah))
1601 udelay(50);
1602
1603 return true;
1604 }
1605
1606 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1607 {
1608 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1609 AR_RTC_FORCE_WAKE_ON_INT);
1610
1611 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1612 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1613
1614 if (!ath9k_hw_wait(ah,
1615 AR_RTC_STATUS,
1616 AR_RTC_STATUS_M,
1617 AR_RTC_STATUS_ON)) {
1618 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1619 return false;
1620 }
1621
1622 ath9k_hw_read_revisions(ah);
1623
1624 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1625 }
1626
1627 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1628 {
1629 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1630 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1631
1632 switch (type) {
1633 case ATH9K_RESET_POWER_ON:
1634 return ath9k_hw_set_reset_power_on(ah);
1635 break;
1636 case ATH9K_RESET_WARM:
1637 case ATH9K_RESET_COLD:
1638 return ath9k_hw_set_reset(ah, type);
1639 break;
1640 default:
1641 return false;
1642 }
1643 }
1644
1645 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1646 enum ath9k_ht_macmode macmode)
1647 {
1648 u32 phymode;
1649 u32 enableDacFifo = 0;
1650 struct ath_hal_5416 *ahp = AH5416(ah);
1651
1652 if (AR_SREV_9285_10_OR_LATER(ah))
1653 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1654 AR_PHY_FC_ENABLE_DAC_FIFO);
1655
1656 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1657 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1658
1659 if (IS_CHAN_HT40(chan)) {
1660 phymode |= AR_PHY_FC_DYN2040_EN;
1661
1662 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1663 (chan->chanmode == CHANNEL_G_HT40PLUS))
1664 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1665
1666 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1667 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1668 }
1669 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1670
1671 ath9k_hw_set11nmac2040(ah, macmode);
1672
1673 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1674 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1675 }
1676
1677 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1678 struct ath9k_channel *chan)
1679 {
1680 struct ath_hal_5416 *ahp = AH5416(ah);
1681
1682 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1683 return false;
1684
1685 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1686 return false;
1687
1688 ahp->ah_chipFullSleep = false;
1689
1690 ath9k_hw_init_pll(ah, chan);
1691
1692 ath9k_hw_set_rfmode(ah, chan);
1693
1694 return true;
1695 }
1696
1697 static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1698 struct ath9k_channel *chan)
1699 {
1700 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1701 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1702 "invalid channel %u/0x%x; not marked as "
1703 "2GHz or 5GHz\n", chan->channel, chan->channelFlags);
1704 return NULL;
1705 }
1706
1707 if (!IS_CHAN_OFDM(chan) &&
1708 !IS_CHAN_B(chan) &&
1709 !IS_CHAN_HT20(chan) &&
1710 !IS_CHAN_HT40(chan)) {
1711 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1712 "invalid channel %u/0x%x; not marked as "
1713 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1714 chan->channel, chan->channelFlags);
1715 return NULL;
1716 }
1717
1718 return ath9k_regd_check_channel(ah, chan);
1719 }
1720
1721 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1722 struct ath9k_channel *chan,
1723 enum ath9k_ht_macmode macmode)
1724 {
1725 u32 synthDelay, qnum;
1726
1727 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1728 if (ath9k_hw_numtxpending(ah, qnum)) {
1729 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1730 "Transmit frames pending on queue %d\n", qnum);
1731 return false;
1732 }
1733 }
1734
1735 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1736 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1737 AR_PHY_RFBUS_GRANT_EN)) {
1738 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1739 "Could not kill baseband RX\n");
1740 return false;
1741 }
1742
1743 ath9k_hw_set_regs(ah, chan, macmode);
1744
1745 if (AR_SREV_9280_10_OR_LATER(ah)) {
1746 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1747 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1748 "failed to set channel\n");
1749 return false;
1750 }
1751 } else {
1752 if (!(ath9k_hw_set_channel(ah, chan))) {
1753 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1754 "failed to set channel\n");
1755 return false;
1756 }
1757 }
1758
1759 if (ath9k_hw_set_txpower(ah, chan,
1760 ath9k_regd_get_ctl(ah, chan),
1761 ath9k_regd_get_antenna_allowed(ah, chan),
1762 chan->maxRegTxPower * 2,
1763 min((u32) MAX_RATE_POWER,
1764 (u32) ah->ah_powerLimit)) != 0) {
1765 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1766 "error init'ing transmit power\n");
1767 return false;
1768 }
1769
1770 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1771 if (IS_CHAN_B(chan))
1772 synthDelay = (4 * synthDelay) / 22;
1773 else
1774 synthDelay /= 10;
1775
1776 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1777
1778 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1779
1780 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1781 ath9k_hw_set_delta_slope(ah, chan);
1782
1783 if (AR_SREV_9280_10_OR_LATER(ah))
1784 ath9k_hw_9280_spur_mitigate(ah, chan);
1785 else
1786 ath9k_hw_spur_mitigate(ah, chan);
1787
1788 if (!chan->oneTimeCalsDone)
1789 chan->oneTimeCalsDone = true;
1790
1791 return true;
1792 }
1793
1794 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1795 {
1796 int bb_spur = AR_NO_SPUR;
1797 int freq;
1798 int bin, cur_bin;
1799 int bb_spur_off, spur_subchannel_sd;
1800 int spur_freq_sd;
1801 int spur_delta_phase;
1802 int denominator;
1803 int upper, lower, cur_vit_mask;
1804 int tmp, newVal;
1805 int i;
1806 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1807 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1808 };
1809 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1810 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1811 };
1812 int inc[4] = { 0, 100, 0, 0 };
1813 struct chan_centers centers;
1814
1815 int8_t mask_m[123];
1816 int8_t mask_p[123];
1817 int8_t mask_amt;
1818 int tmp_mask;
1819 int cur_bb_spur;
1820 bool is2GHz = IS_CHAN_2GHZ(chan);
1821
1822 memset(&mask_m, 0, sizeof(int8_t) * 123);
1823 memset(&mask_p, 0, sizeof(int8_t) * 123);
1824
1825 ath9k_hw_get_channel_centers(ah, chan, &centers);
1826 freq = centers.synth_center;
1827
1828 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1829 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1830 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1831
1832 if (is2GHz)
1833 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1834 else
1835 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1836
1837 if (AR_NO_SPUR == cur_bb_spur)
1838 break;
1839 cur_bb_spur = cur_bb_spur - freq;
1840
1841 if (IS_CHAN_HT40(chan)) {
1842 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1843 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1844 bb_spur = cur_bb_spur;
1845 break;
1846 }
1847 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1848 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1849 bb_spur = cur_bb_spur;
1850 break;
1851 }
1852 }
1853
1854 if (AR_NO_SPUR == bb_spur) {
1855 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1856 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1857 return;
1858 } else {
1859 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1860 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1861 }
1862
1863 bin = bb_spur * 320;
1864
1865 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1866
1867 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1868 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1869 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1870 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1871 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1872
1873 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1874 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1875 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1876 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1877 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1878 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1879
1880 if (IS_CHAN_HT40(chan)) {
1881 if (bb_spur < 0) {
1882 spur_subchannel_sd = 1;
1883 bb_spur_off = bb_spur + 10;
1884 } else {
1885 spur_subchannel_sd = 0;
1886 bb_spur_off = bb_spur - 10;
1887 }
1888 } else {
1889 spur_subchannel_sd = 0;
1890 bb_spur_off = bb_spur;
1891 }
1892
1893 if (IS_CHAN_HT40(chan))
1894 spur_delta_phase =
1895 ((bb_spur * 262144) /
1896 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1897 else
1898 spur_delta_phase =
1899 ((bb_spur * 524288) /
1900 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1901
1902 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1903 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1904
1905 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1906 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1907 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1908 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1909
1910 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1911 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1912
1913 cur_bin = -6000;
1914 upper = bin + 100;
1915 lower = bin - 100;
1916
1917 for (i = 0; i < 4; i++) {
1918 int pilot_mask = 0;
1919 int chan_mask = 0;
1920 int bp = 0;
1921 for (bp = 0; bp < 30; bp++) {
1922 if ((cur_bin > lower) && (cur_bin < upper)) {
1923 pilot_mask = pilot_mask | 0x1 << bp;
1924 chan_mask = chan_mask | 0x1 << bp;
1925 }
1926 cur_bin += 100;
1927 }
1928 cur_bin += inc[i];
1929 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1930 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1931 }
1932
1933 cur_vit_mask = 6100;
1934 upper = bin + 120;
1935 lower = bin - 120;
1936
1937 for (i = 0; i < 123; i++) {
1938 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1939
1940 /* workaround for gcc bug #37014 */
1941 volatile int tmp = abs(cur_vit_mask - bin);
1942
1943 if (tmp < 75)
1944 mask_amt = 1;
1945 else
1946 mask_amt = 0;
1947 if (cur_vit_mask < 0)
1948 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1949 else
1950 mask_p[cur_vit_mask / 100] = mask_amt;
1951 }
1952 cur_vit_mask -= 100;
1953 }
1954
1955 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1956 | (mask_m[48] << 26) | (mask_m[49] << 24)
1957 | (mask_m[50] << 22) | (mask_m[51] << 20)
1958 | (mask_m[52] << 18) | (mask_m[53] << 16)
1959 | (mask_m[54] << 14) | (mask_m[55] << 12)
1960 | (mask_m[56] << 10) | (mask_m[57] << 8)
1961 | (mask_m[58] << 6) | (mask_m[59] << 4)
1962 | (mask_m[60] << 2) | (mask_m[61] << 0);
1963 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1964 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1965
1966 tmp_mask = (mask_m[31] << 28)
1967 | (mask_m[32] << 26) | (mask_m[33] << 24)
1968 | (mask_m[34] << 22) | (mask_m[35] << 20)
1969 | (mask_m[36] << 18) | (mask_m[37] << 16)
1970 | (mask_m[48] << 14) | (mask_m[39] << 12)
1971 | (mask_m[40] << 10) | (mask_m[41] << 8)
1972 | (mask_m[42] << 6) | (mask_m[43] << 4)
1973 | (mask_m[44] << 2) | (mask_m[45] << 0);
1974 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1975 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1976
1977 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1978 | (mask_m[18] << 26) | (mask_m[18] << 24)
1979 | (mask_m[20] << 22) | (mask_m[20] << 20)
1980 | (mask_m[22] << 18) | (mask_m[22] << 16)
1981 | (mask_m[24] << 14) | (mask_m[24] << 12)
1982 | (mask_m[25] << 10) | (mask_m[26] << 8)
1983 | (mask_m[27] << 6) | (mask_m[28] << 4)
1984 | (mask_m[29] << 2) | (mask_m[30] << 0);
1985 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1986 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1987
1988 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1989 | (mask_m[2] << 26) | (mask_m[3] << 24)
1990 | (mask_m[4] << 22) | (mask_m[5] << 20)
1991 | (mask_m[6] << 18) | (mask_m[7] << 16)
1992 | (mask_m[8] << 14) | (mask_m[9] << 12)
1993 | (mask_m[10] << 10) | (mask_m[11] << 8)
1994 | (mask_m[12] << 6) | (mask_m[13] << 4)
1995 | (mask_m[14] << 2) | (mask_m[15] << 0);
1996 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1997 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1998
1999 tmp_mask = (mask_p[15] << 28)
2000 | (mask_p[14] << 26) | (mask_p[13] << 24)
2001 | (mask_p[12] << 22) | (mask_p[11] << 20)
2002 | (mask_p[10] << 18) | (mask_p[9] << 16)
2003 | (mask_p[8] << 14) | (mask_p[7] << 12)
2004 | (mask_p[6] << 10) | (mask_p[5] << 8)
2005 | (mask_p[4] << 6) | (mask_p[3] << 4)
2006 | (mask_p[2] << 2) | (mask_p[1] << 0);
2007 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2008 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2009
2010 tmp_mask = (mask_p[30] << 28)
2011 | (mask_p[29] << 26) | (mask_p[28] << 24)
2012 | (mask_p[27] << 22) | (mask_p[26] << 20)
2013 | (mask_p[25] << 18) | (mask_p[24] << 16)
2014 | (mask_p[23] << 14) | (mask_p[22] << 12)
2015 | (mask_p[21] << 10) | (mask_p[20] << 8)
2016 | (mask_p[19] << 6) | (mask_p[18] << 4)
2017 | (mask_p[17] << 2) | (mask_p[16] << 0);
2018 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2019 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2020
2021 tmp_mask = (mask_p[45] << 28)
2022 | (mask_p[44] << 26) | (mask_p[43] << 24)
2023 | (mask_p[42] << 22) | (mask_p[41] << 20)
2024 | (mask_p[40] << 18) | (mask_p[39] << 16)
2025 | (mask_p[38] << 14) | (mask_p[37] << 12)
2026 | (mask_p[36] << 10) | (mask_p[35] << 8)
2027 | (mask_p[34] << 6) | (mask_p[33] << 4)
2028 | (mask_p[32] << 2) | (mask_p[31] << 0);
2029 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2030 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2031
2032 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2033 | (mask_p[59] << 26) | (mask_p[58] << 24)
2034 | (mask_p[57] << 22) | (mask_p[56] << 20)
2035 | (mask_p[55] << 18) | (mask_p[54] << 16)
2036 | (mask_p[53] << 14) | (mask_p[52] << 12)
2037 | (mask_p[51] << 10) | (mask_p[50] << 8)
2038 | (mask_p[49] << 6) | (mask_p[48] << 4)
2039 | (mask_p[47] << 2) | (mask_p[46] << 0);
2040 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2041 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2042 }
2043
2044 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
2045 {
2046 int bb_spur = AR_NO_SPUR;
2047 int bin, cur_bin;
2048 int spur_freq_sd;
2049 int spur_delta_phase;
2050 int denominator;
2051 int upper, lower, cur_vit_mask;
2052 int tmp, new;
2053 int i;
2054 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2055 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2056 };
2057 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2058 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2059 };
2060 int inc[4] = { 0, 100, 0, 0 };
2061
2062 int8_t mask_m[123];
2063 int8_t mask_p[123];
2064 int8_t mask_amt;
2065 int tmp_mask;
2066 int cur_bb_spur;
2067 bool is2GHz = IS_CHAN_2GHZ(chan);
2068
2069 memset(&mask_m, 0, sizeof(int8_t) * 123);
2070 memset(&mask_p, 0, sizeof(int8_t) * 123);
2071
2072 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2073 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2074 if (AR_NO_SPUR == cur_bb_spur)
2075 break;
2076 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2077 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2078 bb_spur = cur_bb_spur;
2079 break;
2080 }
2081 }
2082
2083 if (AR_NO_SPUR == bb_spur)
2084 return;
2085
2086 bin = bb_spur * 32;
2087
2088 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2089 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2090 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2091 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2092 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2093
2094 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2095
2096 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2097 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2098 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2099 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2100 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2101 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2102
2103 spur_delta_phase = ((bb_spur * 524288) / 100) &
2104 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2105
2106 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2107 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2108
2109 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2110 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2111 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2112 REG_WRITE(ah, AR_PHY_TIMING11, new);
2113
2114 cur_bin = -6000;
2115 upper = bin + 100;
2116 lower = bin - 100;
2117
2118 for (i = 0; i < 4; i++) {
2119 int pilot_mask = 0;
2120 int chan_mask = 0;
2121 int bp = 0;
2122 for (bp = 0; bp < 30; bp++) {
2123 if ((cur_bin > lower) && (cur_bin < upper)) {
2124 pilot_mask = pilot_mask | 0x1 << bp;
2125 chan_mask = chan_mask | 0x1 << bp;
2126 }
2127 cur_bin += 100;
2128 }
2129 cur_bin += inc[i];
2130 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2131 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2132 }
2133
2134 cur_vit_mask = 6100;
2135 upper = bin + 120;
2136 lower = bin - 120;
2137
2138 for (i = 0; i < 123; i++) {
2139 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2140
2141 /* workaround for gcc bug #37014 */
2142 volatile int tmp = abs(cur_vit_mask - bin);
2143
2144 if (tmp < 75)
2145 mask_amt = 1;
2146 else
2147 mask_amt = 0;
2148 if (cur_vit_mask < 0)
2149 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2150 else
2151 mask_p[cur_vit_mask / 100] = mask_amt;
2152 }
2153 cur_vit_mask -= 100;
2154 }
2155
2156 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2157 | (mask_m[48] << 26) | (mask_m[49] << 24)
2158 | (mask_m[50] << 22) | (mask_m[51] << 20)
2159 | (mask_m[52] << 18) | (mask_m[53] << 16)
2160 | (mask_m[54] << 14) | (mask_m[55] << 12)
2161 | (mask_m[56] << 10) | (mask_m[57] << 8)
2162 | (mask_m[58] << 6) | (mask_m[59] << 4)
2163 | (mask_m[60] << 2) | (mask_m[61] << 0);
2164 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2165 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2166
2167 tmp_mask = (mask_m[31] << 28)
2168 | (mask_m[32] << 26) | (mask_m[33] << 24)
2169 | (mask_m[34] << 22) | (mask_m[35] << 20)
2170 | (mask_m[36] << 18) | (mask_m[37] << 16)
2171 | (mask_m[48] << 14) | (mask_m[39] << 12)
2172 | (mask_m[40] << 10) | (mask_m[41] << 8)
2173 | (mask_m[42] << 6) | (mask_m[43] << 4)
2174 | (mask_m[44] << 2) | (mask_m[45] << 0);
2175 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2176 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2177
2178 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2179 | (mask_m[18] << 26) | (mask_m[18] << 24)
2180 | (mask_m[20] << 22) | (mask_m[20] << 20)
2181 | (mask_m[22] << 18) | (mask_m[22] << 16)
2182 | (mask_m[24] << 14) | (mask_m[24] << 12)
2183 | (mask_m[25] << 10) | (mask_m[26] << 8)
2184 | (mask_m[27] << 6) | (mask_m[28] << 4)
2185 | (mask_m[29] << 2) | (mask_m[30] << 0);
2186 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2187 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2188
2189 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2190 | (mask_m[2] << 26) | (mask_m[3] << 24)
2191 | (mask_m[4] << 22) | (mask_m[5] << 20)
2192 | (mask_m[6] << 18) | (mask_m[7] << 16)
2193 | (mask_m[8] << 14) | (mask_m[9] << 12)
2194 | (mask_m[10] << 10) | (mask_m[11] << 8)
2195 | (mask_m[12] << 6) | (mask_m[13] << 4)
2196 | (mask_m[14] << 2) | (mask_m[15] << 0);
2197 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2198 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2199
2200 tmp_mask = (mask_p[15] << 28)
2201 | (mask_p[14] << 26) | (mask_p[13] << 24)
2202 | (mask_p[12] << 22) | (mask_p[11] << 20)
2203 | (mask_p[10] << 18) | (mask_p[9] << 16)
2204 | (mask_p[8] << 14) | (mask_p[7] << 12)
2205 | (mask_p[6] << 10) | (mask_p[5] << 8)
2206 | (mask_p[4] << 6) | (mask_p[3] << 4)
2207 | (mask_p[2] << 2) | (mask_p[1] << 0);
2208 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2209 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2210
2211 tmp_mask = (mask_p[30] << 28)
2212 | (mask_p[29] << 26) | (mask_p[28] << 24)
2213 | (mask_p[27] << 22) | (mask_p[26] << 20)
2214 | (mask_p[25] << 18) | (mask_p[24] << 16)
2215 | (mask_p[23] << 14) | (mask_p[22] << 12)
2216 | (mask_p[21] << 10) | (mask_p[20] << 8)
2217 | (mask_p[19] << 6) | (mask_p[18] << 4)
2218 | (mask_p[17] << 2) | (mask_p[16] << 0);
2219 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2220 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2221
2222 tmp_mask = (mask_p[45] << 28)
2223 | (mask_p[44] << 26) | (mask_p[43] << 24)
2224 | (mask_p[42] << 22) | (mask_p[41] << 20)
2225 | (mask_p[40] << 18) | (mask_p[39] << 16)
2226 | (mask_p[38] << 14) | (mask_p[37] << 12)
2227 | (mask_p[36] << 10) | (mask_p[35] << 8)
2228 | (mask_p[34] << 6) | (mask_p[33] << 4)
2229 | (mask_p[32] << 2) | (mask_p[31] << 0);
2230 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2231 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2232
2233 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2234 | (mask_p[59] << 26) | (mask_p[58] << 24)
2235 | (mask_p[57] << 22) | (mask_p[56] << 20)
2236 | (mask_p[55] << 18) | (mask_p[54] << 16)
2237 | (mask_p[53] << 14) | (mask_p[52] << 12)
2238 | (mask_p[51] << 10) | (mask_p[50] << 8)
2239 | (mask_p[49] << 6) | (mask_p[48] << 4)
2240 | (mask_p[47] << 2) | (mask_p[46] << 0);
2241 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2242 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2243 }
2244
2245 bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2246 enum ath9k_ht_macmode macmode,
2247 u8 txchainmask, u8 rxchainmask,
2248 enum ath9k_ht_extprotspacing extprotspacing,
2249 bool bChannelChange, int *status)
2250 {
2251 u32 saveLedState;
2252 struct ath_hal_5416 *ahp = AH5416(ah);
2253 struct ath9k_channel *curchan = ah->ah_curchan;
2254 u32 saveDefAntenna;
2255 u32 macStaId1;
2256 int ecode;
2257 int i, rx_chainmask;
2258
2259 ahp->ah_extprotspacing = extprotspacing;
2260 ahp->ah_txchainmask = txchainmask;
2261 ahp->ah_rxchainmask = rxchainmask;
2262
2263 if (AR_SREV_9280(ah)) {
2264 ahp->ah_txchainmask &= 0x3;
2265 ahp->ah_rxchainmask &= 0x3;
2266 }
2267
2268 if (ath9k_hw_check_chan(ah, chan) == NULL) {
2269 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2270 "invalid channel %u/0x%x; no mapping\n",
2271 chan->channel, chan->channelFlags);
2272 ecode = -EINVAL;
2273 goto bad;
2274 }
2275
2276 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
2277 ecode = -EIO;
2278 goto bad;
2279 }
2280
2281 if (curchan)
2282 ath9k_hw_getnf(ah, curchan);
2283
2284 if (bChannelChange &&
2285 (ahp->ah_chipFullSleep != true) &&
2286 (ah->ah_curchan != NULL) &&
2287 (chan->channel != ah->ah_curchan->channel) &&
2288 ((chan->channelFlags & CHANNEL_ALL) ==
2289 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2290 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2291 !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2292
2293 if (ath9k_hw_channel_change(ah, chan, macmode)) {
2294 ath9k_hw_loadnf(ah, ah->ah_curchan);
2295 ath9k_hw_start_nfcal(ah);
2296 return true;
2297 }
2298 }
2299
2300 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2301 if (saveDefAntenna == 0)
2302 saveDefAntenna = 1;
2303
2304 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2305
2306 saveLedState = REG_READ(ah, AR_CFG_LED) &
2307 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2308 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2309
2310 ath9k_hw_mark_phy_inactive(ah);
2311
2312 if (!ath9k_hw_chip_reset(ah, chan)) {
2313 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2314 ecode = -EINVAL;
2315 goto bad;
2316 }
2317
2318 if (AR_SREV_9280(ah)) {
2319 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2320 AR_GPIO_JTAG_DISABLE);
2321
2322 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2323 if (IS_CHAN_5GHZ(chan))
2324 ath9k_hw_set_gpio(ah, 9, 0);
2325 else
2326 ath9k_hw_set_gpio(ah, 9, 1);
2327 }
2328 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2329 }
2330
2331 ecode = ath9k_hw_process_ini(ah, chan, macmode);
2332 if (ecode != 0) {
2333 ecode = -EINVAL;
2334 goto bad;
2335 }
2336
2337 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2338 ath9k_hw_set_delta_slope(ah, chan);
2339
2340 if (AR_SREV_9280_10_OR_LATER(ah))
2341 ath9k_hw_9280_spur_mitigate(ah, chan);
2342 else
2343 ath9k_hw_spur_mitigate(ah, chan);
2344
2345 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2346 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2347 "error setting board options\n");
2348 ecode = -EIO;
2349 goto bad;
2350 }
2351
2352 ath9k_hw_decrease_chain_power(ah, chan);
2353
2354 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2355 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2356 | macStaId1
2357 | AR_STA_ID1_RTS_USE_DEF
2358 | (ah->ah_config.
2359 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2360 | ahp->ah_staId1Defaults);
2361 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2362
2363 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2364 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2365
2366 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2367
2368 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2369 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2370 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2371
2372 REG_WRITE(ah, AR_ISR, ~0);
2373
2374 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2375
2376 if (AR_SREV_9280_10_OR_LATER(ah)) {
2377 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
2378 ecode = -EIO;
2379 goto bad;
2380 }
2381 } else {
2382 if (!(ath9k_hw_set_channel(ah, chan))) {
2383 ecode = -EIO;
2384 goto bad;
2385 }
2386 }
2387
2388 for (i = 0; i < AR_NUM_DCU; i++)
2389 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2390
2391 ahp->ah_intrTxqs = 0;
2392 for (i = 0; i < ah->ah_caps.total_queues; i++)
2393 ath9k_hw_resettxqueue(ah, i);
2394
2395 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2396 ath9k_hw_init_qos(ah);
2397
2398 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2399 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2400 ath9k_enable_rfkill(ah);
2401 #endif
2402 ath9k_hw_init_user_settings(ah);
2403
2404 REG_WRITE(ah, AR_STA_ID1,
2405 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2406
2407 ath9k_hw_set_dma(ah);
2408
2409 REG_WRITE(ah, AR_OBS, 8);
2410
2411 if (ahp->ah_intrMitigation) {
2412
2413 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2414 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2415 }
2416
2417 ath9k_hw_init_bb(ah, chan);
2418
2419 if (!ath9k_hw_init_cal(ah, chan)){
2420 ecode = -EIO;;
2421 goto bad;
2422 }
2423
2424 rx_chainmask = ahp->ah_rxchainmask;
2425 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2426 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2427 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2428 }
2429
2430 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2431
2432 if (AR_SREV_9100(ah)) {
2433 u32 mask;
2434 mask = REG_READ(ah, AR_CFG);
2435 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2436 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2437 "CFG Byte Swap Set 0x%x\n", mask);
2438 } else {
2439 mask =
2440 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2441 REG_WRITE(ah, AR_CFG, mask);
2442 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2443 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2444 }
2445 } else {
2446 #ifdef __BIG_ENDIAN
2447 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2448 #endif
2449 }
2450
2451 return true;
2452 bad:
2453 if (status)
2454 *status = ecode;
2455 return false;
2456 }
2457
2458 /************************/
2459 /* Key Cache Management */
2460 /************************/
2461
2462 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2463 {
2464 u32 keyType;
2465
2466 if (entry >= ah->ah_caps.keycache_size) {
2467 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2468 "entry %u out of range\n", entry);
2469 return false;
2470 }
2471
2472 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2473
2474 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2475 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2476 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2477 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2478 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2479 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2480 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2481 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2482
2483 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2484 u16 micentry = entry + 64;
2485
2486 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2487 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2488 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2489 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2490
2491 }
2492
2493 if (ah->ah_curchan == NULL)
2494 return true;
2495
2496 return true;
2497 }
2498
2499 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2500 {
2501 u32 macHi, macLo;
2502
2503 if (entry >= ah->ah_caps.keycache_size) {
2504 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2505 "entry %u out of range\n", entry);
2506 return false;
2507 }
2508
2509 if (mac != NULL) {
2510 macHi = (mac[5] << 8) | mac[4];
2511 macLo = (mac[3] << 24) |
2512 (mac[2] << 16) |
2513 (mac[1] << 8) |
2514 mac[0];
2515 macLo >>= 1;
2516 macLo |= (macHi & 1) << 31;
2517 macHi >>= 1;
2518 } else {
2519 macLo = macHi = 0;
2520 }
2521 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2522 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2523
2524 return true;
2525 }
2526
2527 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2528 const struct ath9k_keyval *k,
2529 const u8 *mac, int xorKey)
2530 {
2531 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2532 u32 key0, key1, key2, key3, key4;
2533 u32 keyType;
2534 u32 xorMask = xorKey ?
2535 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2536 | ATH9K_KEY_XOR) : 0;
2537 struct ath_hal_5416 *ahp = AH5416(ah);
2538
2539 if (entry >= pCap->keycache_size) {
2540 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2541 "entry %u out of range\n", entry);
2542 return false;
2543 }
2544
2545 switch (k->kv_type) {
2546 case ATH9K_CIPHER_AES_OCB:
2547 keyType = AR_KEYTABLE_TYPE_AES;
2548 break;
2549 case ATH9K_CIPHER_AES_CCM:
2550 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2551 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2552 "AES-CCM not supported by mac rev 0x%x\n",
2553 ah->ah_macRev);
2554 return false;
2555 }
2556 keyType = AR_KEYTABLE_TYPE_CCM;
2557 break;
2558 case ATH9K_CIPHER_TKIP:
2559 keyType = AR_KEYTABLE_TYPE_TKIP;
2560 if (ATH9K_IS_MIC_ENABLED(ah)
2561 && entry + 64 >= pCap->keycache_size) {
2562 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2563 "entry %u inappropriate for TKIP\n", entry);
2564 return false;
2565 }
2566 break;
2567 case ATH9K_CIPHER_WEP:
2568 if (k->kv_len < LEN_WEP40) {
2569 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2570 "WEP key length %u too small\n", k->kv_len);
2571 return false;
2572 }
2573 if (k->kv_len <= LEN_WEP40)
2574 keyType = AR_KEYTABLE_TYPE_40;
2575 else if (k->kv_len <= LEN_WEP104)
2576 keyType = AR_KEYTABLE_TYPE_104;
2577 else
2578 keyType = AR_KEYTABLE_TYPE_128;
2579 break;
2580 case ATH9K_CIPHER_CLR:
2581 keyType = AR_KEYTABLE_TYPE_CLR;
2582 break;
2583 default:
2584 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2585 "cipher %u not supported\n", k->kv_type);
2586 return false;
2587 }
2588
2589 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2590 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2591 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2592 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2593 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2594 if (k->kv_len <= LEN_WEP104)
2595 key4 &= 0xff;
2596
2597 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2598 u16 micentry = entry + 64;
2599
2600 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2601 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2602 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2603 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2604 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2605 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2606 (void) ath9k_hw_keysetmac(ah, entry, mac);
2607
2608 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2609 u32 mic0, mic1, mic2, mic3, mic4;
2610
2611 mic0 = get_unaligned_le32(k->kv_mic + 0);
2612 mic2 = get_unaligned_le32(k->kv_mic + 4);
2613 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2614 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2615 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2616 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2617 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2618 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2619 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2620 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2621 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2622 AR_KEYTABLE_TYPE_CLR);
2623
2624 } else {
2625 u32 mic0, mic2;
2626
2627 mic0 = get_unaligned_le32(k->kv_mic + 0);
2628 mic2 = get_unaligned_le32(k->kv_mic + 4);
2629 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2630 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2631 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2632 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2633 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2634 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2635 AR_KEYTABLE_TYPE_CLR);
2636 }
2637 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2638 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2639 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2640 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2641 } else {
2642 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2643 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2644 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2645 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2646 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2647 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2648
2649 (void) ath9k_hw_keysetmac(ah, entry, mac);
2650 }
2651
2652 if (ah->ah_curchan == NULL)
2653 return true;
2654
2655 return true;
2656 }
2657
2658 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2659 {
2660 if (entry < ah->ah_caps.keycache_size) {
2661 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2662 if (val & AR_KEYTABLE_VALID)
2663 return true;
2664 }
2665 return false;
2666 }
2667
2668 /******************************/
2669 /* Power Management (Chipset) */
2670 /******************************/
2671
2672 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2673 {
2674 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2675 if (setChip) {
2676 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2677 AR_RTC_FORCE_WAKE_EN);
2678 if (!AR_SREV_9100(ah))
2679 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2680
2681 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2682 AR_RTC_RESET_EN);
2683 }
2684 }
2685
2686 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2687 {
2688 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2689 if (setChip) {
2690 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2691
2692 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2693 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2694 AR_RTC_FORCE_WAKE_ON_INT);
2695 } else {
2696 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2697 AR_RTC_FORCE_WAKE_EN);
2698 }
2699 }
2700 }
2701
2702 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2703 int setChip)
2704 {
2705 u32 val;
2706 int i;
2707
2708 if (setChip) {
2709 if ((REG_READ(ah, AR_RTC_STATUS) &
2710 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2711 if (ath9k_hw_set_reset_reg(ah,
2712 ATH9K_RESET_POWER_ON) != true) {
2713 return false;
2714 }
2715 }
2716 if (AR_SREV_9100(ah))
2717 REG_SET_BIT(ah, AR_RTC_RESET,
2718 AR_RTC_RESET_EN);
2719
2720 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2721 AR_RTC_FORCE_WAKE_EN);
2722 udelay(50);
2723
2724 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2725 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2726 if (val == AR_RTC_STATUS_ON)
2727 break;
2728 udelay(50);
2729 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2730 AR_RTC_FORCE_WAKE_EN);
2731 }
2732 if (i == 0) {
2733 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2734 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2735 return false;
2736 }
2737 }
2738
2739 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2740
2741 return true;
2742 }
2743
2744 bool ath9k_hw_setpower(struct ath_hal *ah,
2745 enum ath9k_power_mode mode)
2746 {
2747 struct ath_hal_5416 *ahp = AH5416(ah);
2748 static const char *modes[] = {
2749 "AWAKE",
2750 "FULL-SLEEP",
2751 "NETWORK SLEEP",
2752 "UNDEFINED"
2753 };
2754 int status = true, setChip = true;
2755
2756 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2757 modes[ahp->ah_powerMode], modes[mode],
2758 setChip ? "set chip " : "");
2759
2760 switch (mode) {
2761 case ATH9K_PM_AWAKE:
2762 status = ath9k_hw_set_power_awake(ah, setChip);
2763 break;
2764 case ATH9K_PM_FULL_SLEEP:
2765 ath9k_set_power_sleep(ah, setChip);
2766 ahp->ah_chipFullSleep = true;
2767 break;
2768 case ATH9K_PM_NETWORK_SLEEP:
2769 ath9k_set_power_network_sleep(ah, setChip);
2770 break;
2771 default:
2772 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2773 "Unknown power mode %u\n", mode);
2774 return false;
2775 }
2776 ahp->ah_powerMode = mode;
2777
2778 return status;
2779 }
2780
2781 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2782 {
2783 struct ath_hal_5416 *ahp = AH5416(ah);
2784 u8 i;
2785
2786 if (ah->ah_isPciExpress != true)
2787 return;
2788
2789 if (ah->ah_config.pcie_powersave_enable == 2)
2790 return;
2791
2792 if (restore)
2793 return;
2794
2795 if (AR_SREV_9280_20_OR_LATER(ah)) {
2796 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2797 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2798 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2799 }
2800 udelay(1000);
2801 } else if (AR_SREV_9280(ah) &&
2802 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2803 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2804 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2805
2806 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2807 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2808 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2809
2810 if (ah->ah_config.pcie_clock_req)
2811 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2812 else
2813 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2814
2815 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2816 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2817 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2818
2819 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2820
2821 udelay(1000);
2822 } else {
2823 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2824 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2825 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2826 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2827 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2828 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2829 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2830 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2831 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2832 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2833 }
2834
2835 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2836
2837 if (ah->ah_config.pcie_waen) {
2838 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2839 } else {
2840 if (AR_SREV_9285(ah))
2841 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2842 else if (AR_SREV_9280(ah))
2843 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2844 else
2845 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2846 }
2847
2848 }
2849
2850 /**********************/
2851 /* Interrupt Handling */
2852 /**********************/
2853
2854 bool ath9k_hw_intrpend(struct ath_hal *ah)
2855 {
2856 u32 host_isr;
2857
2858 if (AR_SREV_9100(ah))
2859 return true;
2860
2861 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2862 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2863 return true;
2864
2865 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2866 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2867 && (host_isr != AR_INTR_SPURIOUS))
2868 return true;
2869
2870 return false;
2871 }
2872
2873 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2874 {
2875 u32 isr = 0;
2876 u32 mask2 = 0;
2877 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2878 u32 sync_cause = 0;
2879 bool fatal_int = false;
2880 struct ath_hal_5416 *ahp = AH5416(ah);
2881
2882 if (!AR_SREV_9100(ah)) {
2883 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2884 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2885 == AR_RTC_STATUS_ON) {
2886 isr = REG_READ(ah, AR_ISR);
2887 }
2888 }
2889
2890 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2891 AR_INTR_SYNC_DEFAULT;
2892
2893 *masked = 0;
2894
2895 if (!isr && !sync_cause)
2896 return false;
2897 } else {
2898 *masked = 0;
2899 isr = REG_READ(ah, AR_ISR);
2900 }
2901
2902 if (isr) {
2903 if (isr & AR_ISR_BCNMISC) {
2904 u32 isr2;
2905 isr2 = REG_READ(ah, AR_ISR_S2);
2906 if (isr2 & AR_ISR_S2_TIM)
2907 mask2 |= ATH9K_INT_TIM;
2908 if (isr2 & AR_ISR_S2_DTIM)
2909 mask2 |= ATH9K_INT_DTIM;
2910 if (isr2 & AR_ISR_S2_DTIMSYNC)
2911 mask2 |= ATH9K_INT_DTIMSYNC;
2912 if (isr2 & (AR_ISR_S2_CABEND))
2913 mask2 |= ATH9K_INT_CABEND;
2914 if (isr2 & AR_ISR_S2_GTT)
2915 mask2 |= ATH9K_INT_GTT;
2916 if (isr2 & AR_ISR_S2_CST)
2917 mask2 |= ATH9K_INT_CST;
2918 }
2919
2920 isr = REG_READ(ah, AR_ISR_RAC);
2921 if (isr == 0xffffffff) {
2922 *masked = 0;
2923 return false;
2924 }
2925
2926 *masked = isr & ATH9K_INT_COMMON;
2927
2928 if (ahp->ah_intrMitigation) {
2929 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2930 *masked |= ATH9K_INT_RX;
2931 }
2932
2933 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2934 *masked |= ATH9K_INT_RX;
2935 if (isr &
2936 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2937 AR_ISR_TXEOL)) {
2938 u32 s0_s, s1_s;
2939
2940 *masked |= ATH9K_INT_TX;
2941
2942 s0_s = REG_READ(ah, AR_ISR_S0_S);
2943 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2944 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2945
2946 s1_s = REG_READ(ah, AR_ISR_S1_S);
2947 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2948 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2949 }
2950
2951 if (isr & AR_ISR_RXORN) {
2952 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2953 "receive FIFO overrun interrupt\n");
2954 }
2955
2956 if (!AR_SREV_9100(ah)) {
2957 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2958 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2959 if (isr5 & AR_ISR_S5_TIM_TIMER)
2960 *masked |= ATH9K_INT_TIM_TIMER;
2961 }
2962 }
2963
2964 *masked |= mask2;
2965 }
2966
2967 if (AR_SREV_9100(ah))
2968 return true;
2969
2970 if (sync_cause) {
2971 fatal_int =
2972 (sync_cause &
2973 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2974 ? true : false;
2975
2976 if (fatal_int) {
2977 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2978 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2979 "received PCI FATAL interrupt\n");
2980 }
2981 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2982 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2983 "received PCI PERR interrupt\n");
2984 }
2985 }
2986 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2987 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2988 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2989 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2990 REG_WRITE(ah, AR_RC, 0);
2991 *masked |= ATH9K_INT_FATAL;
2992 }
2993 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2994 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2995 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2996 }
2997
2998 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2999 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3000 }
3001
3002 return true;
3003 }
3004
3005 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
3006 {
3007 return AH5416(ah)->ah_maskReg;
3008 }
3009
3010 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
3011 {
3012 struct ath_hal_5416 *ahp = AH5416(ah);
3013 u32 omask = ahp->ah_maskReg;
3014 u32 mask, mask2;
3015 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3016
3017 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3018
3019 if (omask & ATH9K_INT_GLOBAL) {
3020 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3021 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3022 (void) REG_READ(ah, AR_IER);
3023 if (!AR_SREV_9100(ah)) {
3024 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3025 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3026
3027 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3028 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3029 }
3030 }
3031
3032 mask = ints & ATH9K_INT_COMMON;
3033 mask2 = 0;
3034
3035 if (ints & ATH9K_INT_TX) {
3036 if (ahp->ah_txOkInterruptMask)
3037 mask |= AR_IMR_TXOK;
3038 if (ahp->ah_txDescInterruptMask)
3039 mask |= AR_IMR_TXDESC;
3040 if (ahp->ah_txErrInterruptMask)
3041 mask |= AR_IMR_TXERR;
3042 if (ahp->ah_txEolInterruptMask)
3043 mask |= AR_IMR_TXEOL;
3044 }
3045 if (ints & ATH9K_INT_RX) {
3046 mask |= AR_IMR_RXERR;
3047 if (ahp->ah_intrMitigation)
3048 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3049 else
3050 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3051 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3052 mask |= AR_IMR_GENTMR;
3053 }
3054
3055 if (ints & (ATH9K_INT_BMISC)) {
3056 mask |= AR_IMR_BCNMISC;
3057 if (ints & ATH9K_INT_TIM)
3058 mask2 |= AR_IMR_S2_TIM;
3059 if (ints & ATH9K_INT_DTIM)
3060 mask2 |= AR_IMR_S2_DTIM;
3061 if (ints & ATH9K_INT_DTIMSYNC)
3062 mask2 |= AR_IMR_S2_DTIMSYNC;
3063 if (ints & ATH9K_INT_CABEND)
3064 mask2 |= (AR_IMR_S2_CABEND);
3065 }
3066
3067 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3068 mask |= AR_IMR_BCNMISC;
3069 if (ints & ATH9K_INT_GTT)
3070 mask2 |= AR_IMR_S2_GTT;
3071 if (ints & ATH9K_INT_CST)
3072 mask2 |= AR_IMR_S2_CST;
3073 }
3074
3075 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3076 REG_WRITE(ah, AR_IMR, mask);
3077 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3078 AR_IMR_S2_DTIM |
3079 AR_IMR_S2_DTIMSYNC |
3080 AR_IMR_S2_CABEND |
3081 AR_IMR_S2_CABTO |
3082 AR_IMR_S2_TSFOOR |
3083 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3084 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3085 ahp->ah_maskReg = ints;
3086
3087 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3088 if (ints & ATH9K_INT_TIM_TIMER)
3089 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3090 else
3091 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3092 }
3093
3094 if (ints & ATH9K_INT_GLOBAL) {
3095 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3096 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3097 if (!AR_SREV_9100(ah)) {
3098 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3099 AR_INTR_MAC_IRQ);
3100 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3101
3102
3103 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3104 AR_INTR_SYNC_DEFAULT);
3105 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3106 AR_INTR_SYNC_DEFAULT);
3107 }
3108 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3109 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3110 }
3111
3112 return omask;
3113 }
3114
3115 /*******************/
3116 /* Beacon Handling */
3117 /*******************/
3118
3119 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3120 {
3121 struct ath_hal_5416 *ahp = AH5416(ah);
3122 int flags = 0;
3123
3124 ahp->ah_beaconInterval = beacon_period;
3125
3126 switch (ah->ah_opmode) {
3127 case NL80211_IFTYPE_STATION:
3128 case NL80211_IFTYPE_MONITOR:
3129 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3130 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3131 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3132 flags |= AR_TBTT_TIMER_EN;
3133 break;
3134 case NL80211_IFTYPE_ADHOC:
3135 REG_SET_BIT(ah, AR_TXCFG,
3136 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3137 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3138 TU_TO_USEC(next_beacon +
3139 (ahp->ah_atimWindow ? ahp->
3140 ah_atimWindow : 1)));
3141 flags |= AR_NDP_TIMER_EN;
3142 case NL80211_IFTYPE_AP:
3143 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3144 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3145 TU_TO_USEC(next_beacon -
3146 ah->ah_config.
3147 dma_beacon_response_time));
3148 REG_WRITE(ah, AR_NEXT_SWBA,
3149 TU_TO_USEC(next_beacon -
3150 ah->ah_config.
3151 sw_beacon_response_time));
3152 flags |=
3153 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3154 break;
3155 default:
3156 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3157 "%s: unsupported opmode: %d\n",
3158 __func__, ah->ah_opmode);
3159 return;
3160 break;
3161 }
3162
3163 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3164 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3165 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3166 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3167
3168 beacon_period &= ~ATH9K_BEACON_ENA;
3169 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3170 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3171 ath9k_hw_reset_tsf(ah);
3172 }
3173
3174 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3175 }
3176
3177 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3178 const struct ath9k_beacon_state *bs)
3179 {
3180 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3181 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3182
3183 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3184
3185 REG_WRITE(ah, AR_BEACON_PERIOD,
3186 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3187 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3188 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3189
3190 REG_RMW_FIELD(ah, AR_RSSI_THR,
3191 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3192
3193 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3194
3195 if (bs->bs_sleepduration > beaconintval)
3196 beaconintval = bs->bs_sleepduration;
3197
3198 dtimperiod = bs->bs_dtimperiod;
3199 if (bs->bs_sleepduration > dtimperiod)
3200 dtimperiod = bs->bs_sleepduration;
3201
3202 if (beaconintval == dtimperiod)
3203 nextTbtt = bs->bs_nextdtim;
3204 else
3205 nextTbtt = bs->bs_nexttbtt;
3206
3207 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3208 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3209 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3210 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3211
3212 REG_WRITE(ah, AR_NEXT_DTIM,
3213 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3214 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3215
3216 REG_WRITE(ah, AR_SLEEP1,
3217 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3218 | AR_SLEEP1_ASSUME_DTIM);
3219
3220 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3221 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3222 else
3223 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3224
3225 REG_WRITE(ah, AR_SLEEP2,
3226 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3227
3228 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3229 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3230
3231 REG_SET_BIT(ah, AR_TIMER_MODE,
3232 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3233 AR_DTIM_TIMER_EN);
3234
3235 }
3236
3237 /*******************/
3238 /* HW Capabilities */
3239 /*******************/
3240
3241 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3242 {
3243 struct ath_hal_5416 *ahp = AH5416(ah);
3244 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3245 u16 capField = 0, eeval;
3246
3247 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3248
3249 ah->ah_currentRD = eeval;
3250
3251 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3252 ah->ah_currentRDExt = eeval;
3253
3254 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3255
3256 if (ah->ah_opmode != NL80211_IFTYPE_AP &&
3257 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3258 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3259 ah->ah_currentRD += 5;
3260 else if (ah->ah_currentRD == 0x41)
3261 ah->ah_currentRD = 0x43;
3262 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3263 "regdomain mapped to 0x%x\n", ah->ah_currentRD);
3264 }
3265
3266 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3267 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3268
3269 if (eeval & AR5416_OPFLAGS_11A) {
3270 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3271 if (ah->ah_config.ht_enable) {
3272 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3273 set_bit(ATH9K_MODE_11NA_HT20,
3274 pCap->wireless_modes);
3275 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3276 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3277 pCap->wireless_modes);
3278 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3279 pCap->wireless_modes);
3280 }
3281 }
3282 }
3283
3284 if (eeval & AR5416_OPFLAGS_11G) {
3285 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3286 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3287 if (ah->ah_config.ht_enable) {
3288 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3289 set_bit(ATH9K_MODE_11NG_HT20,
3290 pCap->wireless_modes);
3291 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3292 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3293 pCap->wireless_modes);
3294 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3295 pCap->wireless_modes);
3296 }
3297 }
3298 }
3299
3300 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3301 if ((ah->ah_isPciExpress)
3302 || (eeval & AR5416_OPFLAGS_11A)) {
3303 pCap->rx_chainmask =
3304 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3305 } else {
3306 pCap->rx_chainmask =
3307 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3308 }
3309
3310 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3311 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3312
3313 pCap->low_2ghz_chan = 2312;
3314 pCap->high_2ghz_chan = 2732;
3315
3316 pCap->low_5ghz_chan = 4920;
3317 pCap->high_5ghz_chan = 6100;
3318
3319 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3320 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3321 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3322
3323 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3324 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3325 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3326
3327 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3328
3329 if (ah->ah_config.ht_enable)
3330 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3331 else
3332 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3333
3334 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3335 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3336 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3337 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3338
3339 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3340 pCap->total_queues =
3341 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3342 else
3343 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3344
3345 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3346 pCap->keycache_size =
3347 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3348 else
3349 pCap->keycache_size = AR_KEYTABLE_SIZE;
3350
3351 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3352 pCap->num_mr_retries = 4;
3353 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3354
3355 if (AR_SREV_9280_10_OR_LATER(ah))
3356 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3357 else
3358 pCap->num_gpio_pins = AR_NUM_GPIO;
3359
3360 if (AR_SREV_9280_10_OR_LATER(ah)) {
3361 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3362 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3363 } else {
3364 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3365 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3366 }
3367
3368 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3369 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3370 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3371 } else {
3372 pCap->rts_aggr_limit = (8 * 1024);
3373 }
3374
3375 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3376
3377 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3378 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3379 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3380 ah->ah_rfkill_gpio =
3381 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3382 ah->ah_rfkill_polarity =
3383 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3384
3385 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3386 }
3387 #endif
3388
3389 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3390 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3391 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3392 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3393 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3394 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3395 else
3396 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3397
3398 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3399 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3400 else
3401 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3402
3403 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3404 pCap->reg_cap =
3405 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3406 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3407 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3408 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3409 } else {
3410 pCap->reg_cap =
3411 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3412 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3413 }
3414
3415 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3416
3417 pCap->num_antcfg_5ghz =
3418 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3419 pCap->num_antcfg_2ghz =
3420 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3421
3422 return true;
3423 }
3424
3425 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3426 u32 capability, u32 *result)
3427 {
3428 struct ath_hal_5416 *ahp = AH5416(ah);
3429 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3430
3431 switch (type) {
3432 case ATH9K_CAP_CIPHER:
3433 switch (capability) {
3434 case ATH9K_CIPHER_AES_CCM:
3435 case ATH9K_CIPHER_AES_OCB:
3436 case ATH9K_CIPHER_TKIP:
3437 case ATH9K_CIPHER_WEP:
3438 case ATH9K_CIPHER_MIC:
3439 case ATH9K_CIPHER_CLR:
3440 return true;
3441 default:
3442 return false;
3443 }
3444 case ATH9K_CAP_TKIP_MIC:
3445 switch (capability) {
3446 case 0:
3447 return true;
3448 case 1:
3449 return (ahp->ah_staId1Defaults &
3450 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3451 false;
3452 }
3453 case ATH9K_CAP_TKIP_SPLIT:
3454 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3455 false : true;
3456 case ATH9K_CAP_WME_TKIPMIC:
3457 return 0;
3458 case ATH9K_CAP_PHYCOUNTERS:
3459 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3460 case ATH9K_CAP_DIVERSITY:
3461 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3462 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3463 true : false;
3464 case ATH9K_CAP_PHYDIAG:
3465 return true;
3466 case ATH9K_CAP_MCAST_KEYSRCH:
3467 switch (capability) {
3468 case 0:
3469 return true;
3470 case 1:
3471 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3472 return false;
3473 } else {
3474 return (ahp->ah_staId1Defaults &
3475 AR_STA_ID1_MCAST_KSRCH) ? true :
3476 false;
3477 }
3478 }
3479 return false;
3480 case ATH9K_CAP_TSF_ADJUST:
3481 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3482 true : false;
3483 case ATH9K_CAP_RFSILENT:
3484 if (capability == 3)
3485 return false;
3486 case ATH9K_CAP_ANT_CFG_2GHZ:
3487 *result = pCap->num_antcfg_2ghz;
3488 return true;
3489 case ATH9K_CAP_ANT_CFG_5GHZ:
3490 *result = pCap->num_antcfg_5ghz;
3491 return true;
3492 case ATH9K_CAP_TXPOW:
3493 switch (capability) {
3494 case 0:
3495 return 0;
3496 case 1:
3497 *result = ah->ah_powerLimit;
3498 return 0;
3499 case 2:
3500 *result = ah->ah_maxPowerLevel;
3501 return 0;
3502 case 3:
3503 *result = ah->ah_tpScale;
3504 return 0;
3505 }
3506 return false;
3507 default:
3508 return false;
3509 }
3510 }
3511
3512 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3513 u32 capability, u32 setting, int *status)
3514 {
3515 struct ath_hal_5416 *ahp = AH5416(ah);
3516 u32 v;
3517
3518 switch (type) {
3519 case ATH9K_CAP_TKIP_MIC:
3520 if (setting)
3521 ahp->ah_staId1Defaults |=
3522 AR_STA_ID1_CRPT_MIC_ENABLE;
3523 else
3524 ahp->ah_staId1Defaults &=
3525 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3526 return true;
3527 case ATH9K_CAP_DIVERSITY:
3528 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3529 if (setting)
3530 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3531 else
3532 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3533 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3534 return true;
3535 case ATH9K_CAP_MCAST_KEYSRCH:
3536 if (setting)
3537 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3538 else
3539 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3540 return true;
3541 case ATH9K_CAP_TSF_ADJUST:
3542 if (setting)
3543 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3544 else
3545 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3546 return true;
3547 default:
3548 return false;
3549 }
3550 }
3551
3552 /****************************/
3553 /* GPIO / RFKILL / Antennae */
3554 /****************************/
3555
3556 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3557 u32 gpio, u32 type)
3558 {
3559 int addr;
3560 u32 gpio_shift, tmp;
3561
3562 if (gpio > 11)
3563 addr = AR_GPIO_OUTPUT_MUX3;
3564 else if (gpio > 5)
3565 addr = AR_GPIO_OUTPUT_MUX2;
3566 else
3567 addr = AR_GPIO_OUTPUT_MUX1;
3568
3569 gpio_shift = (gpio % 6) * 5;
3570
3571 if (AR_SREV_9280_20_OR_LATER(ah)
3572 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3573 REG_RMW(ah, addr, (type << gpio_shift),
3574 (0x1f << gpio_shift));
3575 } else {
3576 tmp = REG_READ(ah, addr);
3577 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3578 tmp &= ~(0x1f << gpio_shift);
3579 tmp |= (type << gpio_shift);
3580 REG_WRITE(ah, addr, tmp);
3581 }
3582 }
3583
3584 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3585 {
3586 u32 gpio_shift;
3587
3588 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3589
3590 gpio_shift = gpio << 1;
3591
3592 REG_RMW(ah,
3593 AR_GPIO_OE_OUT,
3594 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3595 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3596 }
3597
3598 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3599 {
3600 if (gpio >= ah->ah_caps.num_gpio_pins)
3601 return 0xffffffff;
3602
3603 if (AR_SREV_9280_10_OR_LATER(ah)) {
3604 return (MS
3605 (REG_READ(ah, AR_GPIO_IN_OUT),
3606 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
3607 } else {
3608 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
3609 AR_GPIO_BIT(gpio)) != 0;
3610 }
3611 }
3612
3613 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3614 u32 ah_signal_type)
3615 {
3616 u32 gpio_shift;
3617
3618 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3619
3620 gpio_shift = 2 * gpio;
3621
3622 REG_RMW(ah,
3623 AR_GPIO_OE_OUT,
3624 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3625 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3626 }
3627
3628 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3629 {
3630 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3631 AR_GPIO_BIT(gpio));
3632 }
3633
3634 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3635 void ath9k_enable_rfkill(struct ath_hal *ah)
3636 {
3637 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3638 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3639
3640 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3641 AR_GPIO_INPUT_MUX2_RFSILENT);
3642
3643 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3644 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3645 }
3646 #endif
3647
3648 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
3649 {
3650 struct ath9k_channel *chan = ah->ah_curchan;
3651 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3652 u16 ant_config;
3653 u32 halNumAntConfig;
3654
3655 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3656 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3657
3658 if (cfg < halNumAntConfig) {
3659 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3660 cfg, &ant_config)) {
3661 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3662 return 0;
3663 }
3664 }
3665
3666 return -EINVAL;
3667 }
3668
3669 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3670 {
3671 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3672 }
3673
3674 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3675 {
3676 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3677 }
3678
3679 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3680 enum ath9k_ant_setting settings,
3681 struct ath9k_channel *chan,
3682 u8 *tx_chainmask,
3683 u8 *rx_chainmask,
3684 u8 *antenna_cfgd)
3685 {
3686 struct ath_hal_5416 *ahp = AH5416(ah);
3687 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3688
3689 if (AR_SREV_9280(ah)) {
3690 if (!tx_chainmask_cfg) {
3691
3692 tx_chainmask_cfg = *tx_chainmask;
3693 rx_chainmask_cfg = *rx_chainmask;
3694 }
3695
3696 switch (settings) {
3697 case ATH9K_ANT_FIXED_A:
3698 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3699 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3700 *antenna_cfgd = true;
3701 break;
3702 case ATH9K_ANT_FIXED_B:
3703 if (ah->ah_caps.tx_chainmask >
3704 ATH9K_ANTENNA1_CHAINMASK) {
3705 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3706 }
3707 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3708 *antenna_cfgd = true;
3709 break;
3710 case ATH9K_ANT_VARIABLE:
3711 *tx_chainmask = tx_chainmask_cfg;
3712 *rx_chainmask = rx_chainmask_cfg;
3713 *antenna_cfgd = true;
3714 break;
3715 default:
3716 break;
3717 }
3718 } else {
3719 ahp->ah_diversityControl = settings;
3720 }
3721
3722 return true;
3723 }
3724
3725 /*********************/
3726 /* General Operation */
3727 /*********************/
3728
3729 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3730 {
3731 u32 bits = REG_READ(ah, AR_RX_FILTER);
3732 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3733
3734 if (phybits & AR_PHY_ERR_RADAR)
3735 bits |= ATH9K_RX_FILTER_PHYRADAR;
3736 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3737 bits |= ATH9K_RX_FILTER_PHYERR;
3738
3739 return bits;
3740 }
3741
3742 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3743 {
3744 u32 phybits;
3745
3746 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3747 phybits = 0;
3748 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3749 phybits |= AR_PHY_ERR_RADAR;
3750 if (bits & ATH9K_RX_FILTER_PHYERR)
3751 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3752 REG_WRITE(ah, AR_PHY_ERR, phybits);
3753
3754 if (phybits)
3755 REG_WRITE(ah, AR_RXCFG,
3756 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3757 else
3758 REG_WRITE(ah, AR_RXCFG,
3759 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3760 }
3761
3762 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3763 {
3764 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3765 }
3766
3767 bool ath9k_hw_disable(struct ath_hal *ah)
3768 {
3769 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3770 return false;
3771
3772 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3773 }
3774
3775 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3776 {
3777 struct ath9k_channel *chan = ah->ah_curchan;
3778
3779 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3780
3781 if (ath9k_hw_set_txpower(ah, chan,
3782 ath9k_regd_get_ctl(ah, chan),
3783 ath9k_regd_get_antenna_allowed(ah, chan),
3784 chan->maxRegTxPower * 2,
3785 min((u32) MAX_RATE_POWER,
3786 (u32) ah->ah_powerLimit)) != 0)
3787 return false;
3788
3789 return true;
3790 }
3791
3792 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3793 {
3794 struct ath_hal_5416 *ahp = AH5416(ah);
3795
3796 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3797 }
3798
3799 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3800 {
3801 struct ath_hal_5416 *ahp = AH5416(ah);
3802
3803 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3804
3805 return true;
3806 }
3807
3808 void ath9k_hw_setopmode(struct ath_hal *ah)
3809 {
3810 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3811 }
3812
3813 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3814 {
3815 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3816 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3817 }
3818
3819 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3820 {
3821 struct ath_hal_5416 *ahp = AH5416(ah);
3822
3823 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3824 }
3825
3826 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3827 {
3828 struct ath_hal_5416 *ahp = AH5416(ah);
3829
3830 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3831
3832 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3833 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3834
3835 return true;
3836 }
3837
3838 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3839 {
3840 struct ath_hal_5416 *ahp = AH5416(ah);
3841
3842 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3843 ahp->ah_assocId = assocId;
3844
3845 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3846 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3847 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3848 }
3849
3850 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3851 {
3852 u64 tsf;
3853
3854 tsf = REG_READ(ah, AR_TSF_U32);
3855 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3856
3857 return tsf;
3858 }
3859
3860 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3861 {
3862 int count;
3863
3864 count = 0;
3865 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3866 count++;
3867 if (count > 10) {
3868 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3869 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3870 break;
3871 }
3872 udelay(10);
3873 }
3874 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3875 }
3876
3877 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3878 {
3879 struct ath_hal_5416 *ahp = AH5416(ah);
3880
3881 if (setting)
3882 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3883 else
3884 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3885
3886 return true;
3887 }
3888
3889 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3890 {
3891 struct ath_hal_5416 *ahp = AH5416(ah);
3892
3893 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3894 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3895 ahp->ah_slottime = (u32) -1;
3896 return false;
3897 } else {
3898 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3899 ahp->ah_slottime = us;
3900 return true;
3901 }
3902 }
3903
3904 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3905 {
3906 u32 macmode;
3907
3908 if (mode == ATH9K_HT_MACMODE_2040 &&
3909 !ah->ah_config.cwm_ignore_extcca)
3910 macmode = AR_2040_JOINED_RX_CLEAR;
3911 else
3912 macmode = 0;
3913
3914 REG_WRITE(ah, AR_2040_MODE, macmode);
3915 }
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK