kernel/2.6.29.6-aldebaran-rt/drivers/net/wireless/ath5k/desc.c

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
   4  * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
   5  *
   6  * Permission to use, copy, modify, and distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 /******************************\
  21  Hardware Descriptor Functions
  22 \******************************/
  23
  24 #include "ath5k.h"
  25 #include "reg.h"
  26 #include "debug.h"
  27 #include "base.h"
  28
  29 /*
  30  * TX Descriptors
  31  */
  32
  33 /*
  34  * Initialize the 2-word tx control descriptor on 5210/5211
  35  */
  36 static int
  37 ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
  38         unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
  39         unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
  40         unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
  41         unsigned int rtscts_rate, unsigned int rtscts_duration)
  42 {
  43         u32 frame_type;
  44         struct ath5k_hw_2w_tx_ctl *tx_ctl;
  45         unsigned int frame_len;
  46
  47         tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
  48
  49         /*
  50          * Validate input
  51          * - Zero retries don't make sense.
  52          * - A zero rate will put the HW into a mode where it continously sends
  53          *   noise on the channel, so it is important to avoid this.
  54          */
  55         if (unlikely(tx_tries0 == 0)) {
  56                 ATH5K_ERR(ah->ah_sc, "zero retries\n");
  57                 WARN_ON(1);
  58                 return -EINVAL;
  59         }
  60         if (unlikely(tx_rate0 == 0)) {
  61                 ATH5K_ERR(ah->ah_sc, "zero rate\n");
  62                 WARN_ON(1);
  63                 return -EINVAL;
  64         }
  65
  66         /* Clear descriptor */
  67         memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
  68
  69         /* Setup control descriptor */
  70
  71         /* Verify and set frame length */
  72
  73         /* remove padding we might have added before */
  74         frame_len = pkt_len - ath5k_pad_size(hdr_len) + FCS_LEN;
  75
  76         if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
  77                 return -EINVAL;
  78
  79         tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
  80
  81         /* Verify and set buffer length */
  82
  83         /* NB: beacon's BufLen must be a multiple of 4 bytes */
  84         if (type == AR5K_PKT_TYPE_BEACON)
  85                 pkt_len = roundup(pkt_len, 4);
  86
  87         if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
  88                 return -EINVAL;
  89
  90         tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
  91
  92         /*
  93          * Verify and set header length
  94          * XXX: I only found that on 5210 code, does it work on 5211 ?
  95          */
  96         if (ah->ah_version == AR5K_AR5210) {
  97                 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
  98                         return -EINVAL;
  99                 tx_ctl->tx_control_0 |=
 100                         AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
 101         }
 102
 103         /*Diferences between 5210-5211*/
 104         if (ah->ah_version == AR5K_AR5210) {
 105                 switch (type) {
 106                 case AR5K_PKT_TYPE_BEACON:
 107                 case AR5K_PKT_TYPE_PROBE_RESP:
 108                         frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
 109                 case AR5K_PKT_TYPE_PIFS:
 110                         frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
 111                 default:
 112                         frame_type = type /*<< 2 ?*/;
 113                 }
 114
 115                 tx_ctl->tx_control_0 |=
 116                 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
 117                 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
 118
 119         } else {
 120                 tx_ctl->tx_control_0 |=
 121                         AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
 122                         AR5K_REG_SM(antenna_mode,
 123                                 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
 124                 tx_ctl->tx_control_1 |=
 125                         AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
 126         }
 127 #define _TX_FLAGS(_c, _flag)                                    \
 128         if (flags & AR5K_TXDESC_##_flag) {                      \
 129                 tx_ctl->tx_control_##_c |=                      \
 130                         AR5K_2W_TX_DESC_CTL##_c##_##_flag;      \
 131         }
 132
 133         _TX_FLAGS(0, CLRDMASK);
 134         _TX_FLAGS(0, VEOL);
 135         _TX_FLAGS(0, INTREQ);
 136         _TX_FLAGS(0, RTSENA);
 137         _TX_FLAGS(1, NOACK);
 138
 139 #undef _TX_FLAGS
 140
 141         /*
 142          * WEP crap
 143          */
 144         if (key_index != AR5K_TXKEYIX_INVALID) {
 145                 tx_ctl->tx_control_0 |=
 146                         AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
 147                 tx_ctl->tx_control_1 |=
 148                         AR5K_REG_SM(key_index,
 149                         AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
 150         }
 151
 152         /*
 153          * RTS/CTS Duration [5210 ?]
 154          */
 155         if ((ah->ah_version == AR5K_AR5210) &&
 156                         (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
 157                 tx_ctl->tx_control_1 |= rtscts_duration &
 158                                 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
 159
 160         return 0;
 161 }
 162
 163 /*
 164  * Initialize the 4-word tx control descriptor on 5212
 165  */
 166 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
 167         struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
 168         enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
 169         unsigned int tx_tries0, unsigned int key_index,
 170         unsigned int antenna_mode, unsigned int flags,
 171         unsigned int rtscts_rate,
 172         unsigned int rtscts_duration)
 173 {
 174         struct ath5k_hw_4w_tx_ctl *tx_ctl;
 175         unsigned int frame_len;
 176
 177         ATH5K_TRACE(ah->ah_sc);
 178         tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
 179
 180         /*
 181          * Validate input
 182          * - Zero retries don't make sense.
 183          * - A zero rate will put the HW into a mode where it continously sends
 184          *   noise on the channel, so it is important to avoid this.
 185          */
 186         if (unlikely(tx_tries0 == 0)) {
 187                 ATH5K_ERR(ah->ah_sc, "zero retries\n");
 188                 WARN_ON(1);
 189                 return -EINVAL;
 190         }
 191         if (unlikely(tx_rate0 == 0)) {
 192                 ATH5K_ERR(ah->ah_sc, "zero rate\n");
 193                 WARN_ON(1);
 194                 return -EINVAL;
 195         }
 196
 197         /* Clear descriptor */
 198         memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
 199
 200         /* Setup control descriptor */
 201
 202         /* Verify and set frame length */
 203
 204         /* remove padding we might have added before */
 205         frame_len = pkt_len - ath5k_pad_size(hdr_len) + FCS_LEN;
 206
 207         if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
 208                 return -EINVAL;
 209
 210         tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
 211
 212         /* Verify and set buffer length */
 213
 214         /* NB: beacon's BufLen must be a multiple of 4 bytes */
 215         if (type == AR5K_PKT_TYPE_BEACON)
 216                 pkt_len = roundup(pkt_len, 4);
 217
 218         if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
 219                 return -EINVAL;
 220
 221         tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
 222
 223         tx_ctl->tx_control_0 |=
 224                 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
 225                 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
 226         tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
 227                                         AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
 228         tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
 229                                         AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
 230         tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
 231
 232 #define _TX_FLAGS(_c, _flag)                                    \
 233         if (flags & AR5K_TXDESC_##_flag) {                      \
 234                 tx_ctl->tx_control_##_c |=                      \
 235                         AR5K_4W_TX_DESC_CTL##_c##_##_flag;      \
 236         }
 237
 238         _TX_FLAGS(0, CLRDMASK);
 239         _TX_FLAGS(0, VEOL);
 240         _TX_FLAGS(0, INTREQ);
 241         _TX_FLAGS(0, RTSENA);
 242         _TX_FLAGS(0, CTSENA);
 243         _TX_FLAGS(1, NOACK);
 244
 245 #undef _TX_FLAGS
 246
 247         /*
 248          * WEP crap
 249          */
 250         if (key_index != AR5K_TXKEYIX_INVALID) {
 251                 tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
 252                 tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
 253                                 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
 254         }
 255
 256         /*
 257          * RTS/CTS
 258          */
 259         if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
 260                 if ((flags & AR5K_TXDESC_RTSENA) &&
 261                                 (flags & AR5K_TXDESC_CTSENA))
 262                         return -EINVAL;
 263                 tx_ctl->tx_control_2 |= rtscts_duration &
 264                                 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
 265                 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
 266                                 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
 267         }
 268
 269         return 0;
 270 }
 271
 272 /*
 273  * Initialize a 4-word multi rate retry tx control descriptor on 5212
 274  */
 275 static int
 276 ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
 277         unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
 278         u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3)
 279 {
 280         struct ath5k_hw_4w_tx_ctl *tx_ctl;
 281
 282         /*
 283          * Rates can be 0 as long as the retry count is 0 too.
 284          * A zero rate and nonzero retry count will put the HW into a mode where
 285          * it continously sends noise on the channel, so it is important to
 286          * avoid this.
 287          */
 288         if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
 289                      (tx_rate2 == 0 && tx_tries2 != 0) ||
 290                      (tx_rate3 == 0 && tx_tries3 != 0))) {
 291                 ATH5K_ERR(ah->ah_sc, "zero rate\n");
 292                 WARN_ON(1);
 293                 return -EINVAL;
 294         }
 295
 296         if (ah->ah_version == AR5K_AR5212) {
 297                 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
 298
 299 #define _XTX_TRIES(_n)                                                  \
 300         if (tx_tries##_n) {                                             \
 301                 tx_ctl->tx_control_2 |=                                 \
 302                     AR5K_REG_SM(tx_tries##_n,                           \
 303                     AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n);               \
 304                 tx_ctl->tx_control_3 |=                                 \
 305                     AR5K_REG_SM(tx_rate##_n,                            \
 306                     AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n);                \
 307         }
 308
 309                 _XTX_TRIES(1);
 310                 _XTX_TRIES(2);
 311                 _XTX_TRIES(3);
 312
 313 #undef _XTX_TRIES
 314
 315                 return 1;
 316         }
 317
 318         return 0;
 319 }
 320
 321 /* no mrr support for cards older than 5212 */
 322 static int
 323 ath5k_hw_setup_no_mrr(struct ath5k_hw *ah, struct ath5k_desc *desc,
 324         unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
 325         u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3)
 326 {
 327         return 0;
 328 }
 329
 330 /*
 331  * Proccess the tx status descriptor on 5210/5211
 332  */
 333 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
 334                 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
 335 {
 336         struct ath5k_hw_2w_tx_ctl *tx_ctl;
 337         struct ath5k_hw_tx_status *tx_status;
 338
 339         ATH5K_TRACE(ah->ah_sc);
 340
 341         tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
 342         tx_status = &desc->ud.ds_tx5210.tx_stat;
 343
 344         /* No frame has been send or error */
 345         if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
 346                 return -EINPROGRESS;
 347
 348         /*
 349          * Get descriptor status
 350          */
 351         ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
 352                 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
 353         ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
 354                 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
 355         ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
 356                 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
 357         /*TODO: ts->ts_virtcol + test*/
 358         ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
 359                 AR5K_DESC_TX_STATUS1_SEQ_NUM);
 360         ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
 361                 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
 362         ts->ts_antenna = 1;
 363         ts->ts_status = 0;
 364         ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0,
 365                 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
 366         ts->ts_retry[0] = ts->ts_longretry;
 367         ts->ts_final_idx = 0;
 368
 369         if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
 370                 if (tx_status->tx_status_0 &
 371                                 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
 372                         ts->ts_status |= AR5K_TXERR_XRETRY;
 373
 374                 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
 375                         ts->ts_status |= AR5K_TXERR_FIFO;
 376
 377                 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
 378                         ts->ts_status |= AR5K_TXERR_FILT;
 379         }
 380
 381         return 0;
 382 }
 383
 384 /*
 385  * Proccess a tx status descriptor on 5212
 386  */
 387 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
 388                 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
 389 {
 390         struct ath5k_hw_4w_tx_ctl *tx_ctl;
 391         struct ath5k_hw_tx_status *tx_status;
 392
 393         ATH5K_TRACE(ah->ah_sc);
 394
 395         tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
 396         tx_status = &desc->ud.ds_tx5212.tx_stat;
 397
 398         /* No frame has been send or error */
 399         if (unlikely(!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE)))
 400                 return -EINPROGRESS;
 401
 402         /*
 403          * Get descriptor status
 404          */
 405         ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
 406                 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
 407         ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
 408                 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
 409         ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
 410                 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
 411         ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
 412                 AR5K_DESC_TX_STATUS1_SEQ_NUM);
 413         ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
 414                 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
 415         ts->ts_antenna = (tx_status->tx_status_1 &
 416                 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
 417         ts->ts_status = 0;
 418
 419         ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
 420                         AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX);
 421
 422         /* The longretry counter has the number of un-acked retries
 423          * for the final rate. To get the total number of retries
 424          * we have to add the retry counters for the other rates
 425          * as well
 426          */
 427         ts->ts_retry[ts->ts_final_idx] = ts->ts_longretry;
 428         switch (ts->ts_final_idx) {
 429         case 3:
 430                 ts->ts_rate[3] = AR5K_REG_MS(tx_ctl->tx_control_3,
 431                         AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
 432
 433                 ts->ts_retry[2] = AR5K_REG_MS(tx_ctl->tx_control_2,
 434                         AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
 435                 ts->ts_longretry += ts->ts_retry[2];
 436                 /* fall through */
 437         case 2:
 438                 ts->ts_rate[2] = AR5K_REG_MS(tx_ctl->tx_control_3,
 439                         AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
 440
 441                 ts->ts_retry[1] = AR5K_REG_MS(tx_ctl->tx_control_2,
 442                         AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
 443                 ts->ts_longretry += ts->ts_retry[1];
 444                 /* fall through */
 445         case 1:
 446                 ts->ts_rate[1] = AR5K_REG_MS(tx_ctl->tx_control_3,
 447                         AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
 448
 449                 ts->ts_retry[0] = AR5K_REG_MS(tx_ctl->tx_control_2,
 450                         AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
 451                 ts->ts_longretry += ts->ts_retry[0];
 452                 /* fall through */
 453         case 0:
 454                 ts->ts_rate[0] = tx_ctl->tx_control_3 &
 455                         AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
 456                 break;
 457         }
 458
 459         /* TX error */
 460         if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
 461                 if (tx_status->tx_status_0 &
 462                                 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
 463                         ts->ts_status |= AR5K_TXERR_XRETRY;
 464
 465                 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
 466                         ts->ts_status |= AR5K_TXERR_FIFO;
 467
 468                 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
 469                         ts->ts_status |= AR5K_TXERR_FILT;
 470         }
 471
 472         return 0;
 473 }
 474
 475 /*
 476  * RX Descriptors
 477  */
 478
 479 /*
 480  * Initialize an rx control descriptor
 481  */
 482 static int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
 483                         u32 size, unsigned int flags)
 484 {
 485         struct ath5k_hw_rx_ctl *rx_ctl;
 486
 487         ATH5K_TRACE(ah->ah_sc);
 488         rx_ctl = &desc->ud.ds_rx.rx_ctl;
 489
 490         /*
 491          * Clear the descriptor
 492          * If we don't clean the status descriptor,
 493          * while scanning we get too many results,
 494          * most of them virtual, after some secs
 495          * of scanning system hangs. M.F.
 496         */
 497         memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
 498
 499         /* Setup descriptor */
 500         rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
 501         if (unlikely(rx_ctl->rx_control_1 != size))
 502                 return -EINVAL;
 503
 504         if (flags & AR5K_RXDESC_INTREQ)
 505                 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
 506
 507         return 0;
 508 }
 509
 510 /*
 511  * Proccess the rx status descriptor on 5210/5211
 512  */
 513 static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
 514                 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
 515 {
 516         struct ath5k_hw_rx_status *rx_status;
 517
 518         rx_status = &desc->ud.ds_rx.u.rx_stat;
 519
 520         /* No frame received / not ready */
 521         if (unlikely(!(rx_status->rx_status_1 &
 522         AR5K_5210_RX_DESC_STATUS1_DONE)))
 523                 return -EINPROGRESS;
 524
 525         /*
 526          * Frame receive status
 527          */
 528         rs->rs_datalen = rx_status->rx_status_0 &
 529                 AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
 530         rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
 531                 AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
 532         rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
 533                 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
 534         rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
 535                 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA);
 536         rs->rs_more = !!(rx_status->rx_status_0 &
 537                 AR5K_5210_RX_DESC_STATUS0_MORE);
 538         /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
 539         rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
 540                 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
 541         rs->rs_status = 0;
 542         rs->rs_phyerr = 0;
 543
 544         /*
 545          * Key table status
 546          */
 547         if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID)
 548                 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
 549                         AR5K_5210_RX_DESC_STATUS1_KEY_INDEX);
 550         else
 551                 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
 552
 553         /*
 554          * Receive/descriptor errors
 555          */
 556         if (!(rx_status->rx_status_1 &
 557         AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
 558                 if (rx_status->rx_status_1 &
 559                                 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
 560                         rs->rs_status |= AR5K_RXERR_CRC;
 561
 562                 if (rx_status->rx_status_1 &
 563                                 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
 564                         rs->rs_status |= AR5K_RXERR_FIFO;
 565
 566                 if (rx_status->rx_status_1 &
 567                                 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
 568                         rs->rs_status |= AR5K_RXERR_PHY;
 569                         rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
 570                                 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
 571                 }
 572
 573                 if (rx_status->rx_status_1 &
 574                                 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
 575                         rs->rs_status |= AR5K_RXERR_DECRYPT;
 576         }
 577
 578         return 0;
 579 }
 580
 581 /*
 582  * Proccess the rx status descriptor on 5212
 583  */
 584 static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
 585                 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
 586 {
 587         struct ath5k_hw_rx_status *rx_status;
 588         struct ath5k_hw_rx_error *rx_err;
 589
 590         ATH5K_TRACE(ah->ah_sc);
 591         rx_status = &desc->ud.ds_rx.u.rx_stat;
 592
 593         /* Overlay on error */
 594         rx_err = &desc->ud.ds_rx.u.rx_err;
 595
 596         /* No frame received / not ready */
 597         if (unlikely(!(rx_status->rx_status_1 &
 598         AR5K_5212_RX_DESC_STATUS1_DONE)))
 599                 return -EINPROGRESS;
 600
 601         /*
 602          * Frame receive status
 603          */
 604         rs->rs_datalen = rx_status->rx_status_0 &
 605                 AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
 606         rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
 607                 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
 608         rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
 609                 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
 610         rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
 611                 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA);
 612         rs->rs_more = !!(rx_status->rx_status_0 &
 613                 AR5K_5212_RX_DESC_STATUS0_MORE);
 614         rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
 615                 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
 616         rs->rs_status = 0;
 617         rs->rs_phyerr = 0;
 618
 619         /*
 620          * Key table status
 621          */
 622         if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
 623                 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
 624                                 AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
 625         else
 626                 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
 627
 628         /*
 629          * Receive/descriptor errors
 630          */
 631         if (!(rx_status->rx_status_1 &
 632         AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
 633                 if (rx_status->rx_status_1 &
 634                                 AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
 635                         rs->rs_status |= AR5K_RXERR_CRC;
 636
 637                 if (rx_status->rx_status_1 &
 638                                 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
 639                         rs->rs_status |= AR5K_RXERR_PHY;
 640                         rs->rs_phyerr |= AR5K_REG_MS(rx_err->rx_error_1,
 641                                            AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
 642                 }
 643
 644                 if (rx_status->rx_status_1 &
 645                                 AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
 646                         rs->rs_status |= AR5K_RXERR_DECRYPT;
 647
 648                 if (rx_status->rx_status_1 &
 649                                 AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
 650                         rs->rs_status |= AR5K_RXERR_MIC;
 651         }
 652
 653         return 0;
 654 }
 655
 656 /*
 657  * Init function pointers inside ath5k_hw struct
 658  */
 659 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
 660 {
 661
 662         if (ah->ah_version != AR5K_AR5210 &&
 663                 ah->ah_version != AR5K_AR5211 &&
 664                 ah->ah_version != AR5K_AR5212)
 665                         return -ENOTSUPP;
 666
 667         /* XXX: What is this magic value and where is it used ? */
 668         if (ah->ah_version == AR5K_AR5212)
 669                 ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
 670         else if (ah->ah_version == AR5K_AR5211)
 671                 ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
 672
 673         if (ah->ah_version == AR5K_AR5212) {
 674                 ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
 675                 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
 676                 ah->ah_setup_mrr_tx_desc = ath5k_hw_setup_mrr_tx_desc;
 677                 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
 678         } else {
 679                 ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
 680                 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
 681                 ah->ah_setup_mrr_tx_desc = ath5k_hw_setup_no_mrr;
 682                 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
 683         }
 684
 685         if (ah->ah_version == AR5K_AR5212)
 686                 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
 687         else if (ah->ah_version <= AR5K_AR5211)
 688                 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
 689
 690         return 0;
 691 }
 692