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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / net / wan / farsync.c
blob48a2c9d28950fc875a72334623343300bda21181
1 /*
2 * FarSync WAN driver for Linux (2.6.x kernel version)
3 *
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
5 *
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
7 * www.farsite.co.uk
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>
15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/version.h>
21 #include <linux/pci.h>
22 #include <linux/ioport.h>
23 #include <linux/init.h>
24 #include <linux/if.h>
25 #include <linux/hdlc.h>
26 #include <asm/io.h>
27 #include <asm/uaccess.h>
28
29 #include "farsync.h"
30
31 /*
32 * Module info
33 */
34 MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");
35 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
36 MODULE_LICENSE("GPL");
37
38 /* Driver configuration and global parameters
39 * ==========================================
40 */
41
42 /* Number of ports (per card) and cards supported
43 */
44 #define FST_MAX_PORTS 4
45 #define FST_MAX_CARDS 32
46
47 /* Default parameters for the link
48 */
49 #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
50 * useful */
51 #define FST_TXQ_DEPTH 16 /* This one is for the buffering
52 * of frames on the way down to the card
53 * so that we can keep the card busy
54 * and maximise throughput
55 */
56 #define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
57 * network layer */
58 #define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
59 * control from network layer */
60 #define FST_MAX_MTU 8000 /* Huge but possible */
61 #define FST_DEF_MTU 1500 /* Common sane value */
62
63 #define FST_TX_TIMEOUT (2*HZ)
64
65 #ifdef ARPHRD_RAWHDLC
66 #define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
67 #else
68 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
69 #endif
70
71 /*
72 * Modules parameters and associated varaibles
73 */
74 static int fst_txq_low = FST_LOW_WATER_MARK;
75 static int fst_txq_high = FST_HIGH_WATER_MARK;
76 static int fst_max_reads = 7;
77 static int fst_excluded_cards = 0;
78 static int fst_excluded_list[FST_MAX_CARDS];
79
80 module_param(fst_txq_low, int, 0);
81 module_param(fst_txq_high, int, 0);
82 module_param(fst_max_reads, int, 0);
83 module_param(fst_excluded_cards, int, 0);
84 module_param_array(fst_excluded_list, int, NULL, 0);
85
86 /* Card shared memory layout
87 * =========================
88 */
89 #pragma pack(1)
90
91 /* This information is derived in part from the FarSite FarSync Smc.h
92 * file. Unfortunately various name clashes and the non-portability of the
93 * bit field declarations in that file have meant that I have chosen to
94 * recreate the information here.
95 *
96 * The SMC (Shared Memory Configuration) has a version number that is
97 * incremented every time there is a significant change. This number can
98 * be used to check that we have not got out of step with the firmware
99 * contained in the .CDE files.
100 */
101 #define SMC_VERSION 24
102
103 #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
104
105 #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
106 * configuration structure */
107 #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
108 * buffers */
109
110 #define LEN_TX_BUFFER 8192 /* Size of packet buffers */
111 #define LEN_RX_BUFFER 8192
112
113 #define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
114 #define LEN_SMALL_RX_BUFFER 256
115
116 #define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
117 #define NUM_RX_BUFFER 8
118
119 /* Interrupt retry time in milliseconds */
120 #define INT_RETRY_TIME 2
121
122 /* The Am186CH/CC processors support a SmartDMA mode using circular pools
123 * of buffer descriptors. The structure is almost identical to that used
124 * in the LANCE Ethernet controllers. Details available as PDF from the
125 * AMD web site: http://www.amd.com/products/epd/processors/\
126 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
127 */
128 struct txdesc { /* Transmit descriptor */
129 volatile u16 ladr; /* Low order address of packet. This is a
130 * linear address in the Am186 memory space
131 */
132 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
133 * bits must be zero
134 */
135 volatile u8 bits; /* Status and config */
136 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.
137 * Transmit terminal count interrupt enable in
138 * top bit.
139 */
140 u16 unused; /* Not used in Tx */
141 };
142
143 struct rxdesc { /* Receive descriptor */
144 volatile u16 ladr; /* Low order address of packet */
145 volatile u8 hadr; /* High order address */
146 volatile u8 bits; /* Status and config */
147 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.
148 * Receive terminal count interrupt enable in
149 * top bit.
150 */
151 volatile u16 mcnt; /* Message byte count (15 bits) */
152 };
153
154 /* Convert a length into the 15 bit 2's complement */
155 /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
156 /* Since we need to set the high bit to enable the completion interrupt this
157 * can be made a lot simpler
158 */
159 #define cnv_bcnt(len) (-(len))
160
161 /* Status and config bits for the above */
162 #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
163 #define TX_STP 0x02 /* Tx: start of packet */
164 #define TX_ENP 0x01 /* Tx: end of packet */
165 #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
166 #define RX_FRAM 0x20 /* Rx: framing error */
167 #define RX_OFLO 0x10 /* Rx: overflow error */
168 #define RX_CRC 0x08 /* Rx: CRC error */
169 #define RX_HBUF 0x04 /* Rx: buffer error */
170 #define RX_STP 0x02 /* Rx: start of packet */
171 #define RX_ENP 0x01 /* Rx: end of packet */
172
173 /* Interrupts from the card are caused by various events which are presented
174 * in a circular buffer as several events may be processed on one physical int
175 */
176 #define MAX_CIRBUFF 32
177
178 struct cirbuff {
179 u8 rdindex; /* read, then increment and wrap */
180 u8 wrindex; /* write, then increment and wrap */
181 u8 evntbuff[MAX_CIRBUFF];
182 };
183
184 /* Interrupt event codes.
185 * Where appropriate the two low order bits indicate the port number
186 */
187 #define CTLA_CHG 0x18 /* Control signal changed */
188 #define CTLB_CHG 0x19
189 #define CTLC_CHG 0x1A
190 #define CTLD_CHG 0x1B
191
192 #define INIT_CPLT 0x20 /* Initialisation complete */
193 #define INIT_FAIL 0x21 /* Initialisation failed */
194
195 #define ABTA_SENT 0x24 /* Abort sent */
196 #define ABTB_SENT 0x25
197 #define ABTC_SENT 0x26
198 #define ABTD_SENT 0x27
199
200 #define TXA_UNDF 0x28 /* Transmission underflow */
201 #define TXB_UNDF 0x29
202 #define TXC_UNDF 0x2A
203 #define TXD_UNDF 0x2B
204
205 #define F56_INT 0x2C
206 #define M32_INT 0x2D
207
208 #define TE1_ALMA 0x30
209
210 /* Port physical configuration. See farsync.h for field values */
211 struct port_cfg {
212 u16 lineInterface; /* Physical interface type */
213 u8 x25op; /* Unused at present */
214 u8 internalClock; /* 1 => internal clock, 0 => external */
215 u8 transparentMode; /* 1 => on, 0 => off */
216 u8 invertClock; /* 0 => normal, 1 => inverted */
217 u8 padBytes[6]; /* Padding */
218 u32 lineSpeed; /* Speed in bps */
219 };
220
221 /* TE1 port physical configuration */
222 struct su_config {
223 u32 dataRate;
224 u8 clocking;
225 u8 framing;
226 u8 structure;
227 u8 interface;
228 u8 coding;
229 u8 lineBuildOut;
230 u8 equalizer;
231 u8 transparentMode;
232 u8 loopMode;
233 u8 range;
234 u8 txBufferMode;
235 u8 rxBufferMode;
236 u8 startingSlot;
237 u8 losThreshold;
238 u8 enableIdleCode;
239 u8 idleCode;
240 u8 spare[44];
241 };
242
243 /* TE1 Status */
244 struct su_status {
245 u32 receiveBufferDelay;
246 u32 framingErrorCount;
247 u32 codeViolationCount;
248 u32 crcErrorCount;
249 u32 lineAttenuation;
250 u8 portStarted;
251 u8 lossOfSignal;
252 u8 receiveRemoteAlarm;
253 u8 alarmIndicationSignal;
254 u8 spare[40];
255 };
256
257 /* Finally sling all the above together into the shared memory structure.
258 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
259 * evolving under NT for some time so I guess we're stuck with it.
260 * The structure starts at offset SMC_BASE.
261 * See farsync.h for some field values.
262 */
263 struct fst_shared {
264 /* DMA descriptor rings */
265 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
266 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
267
268 /* Obsolete small buffers */
269 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
270 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
271
272 u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
273 * 0xFF => halted
274 */
275
276 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
277 * set to 0xEE by host to acknowledge interrupt
278 */
279
280 u16 smcVersion; /* Must match SMC_VERSION */
281
282 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
283 * version, RR = revision and BB = build
284 */
285
286 u16 txa_done; /* Obsolete completion flags */
287 u16 rxa_done;
288 u16 txb_done;
289 u16 rxb_done;
290 u16 txc_done;
291 u16 rxc_done;
292 u16 txd_done;
293 u16 rxd_done;
294
295 u16 mailbox[4]; /* Diagnostics mailbox. Not used */
296
297 struct cirbuff interruptEvent; /* interrupt causes */
298
299 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */
300 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */
301
302 struct port_cfg portConfig[FST_MAX_PORTS];
303
304 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
305
306 u16 cableStatus; /* lsb: 0=> present, 1=> absent */
307
308 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */
309 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */
310
311 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */
312 u16 cardMailbox[4]; /* Not used */
313
314 /* Number of times the card thinks the host has
315 * missed an interrupt by not acknowledging
316 * within 2mS (I guess NT has problems)
317 */
318 u32 interruptRetryCount;
319
320 /* Driver private data used as an ID. We'll not
321 * use this as I'd rather keep such things
322 * in main memory rather than on the PCI bus
323 */
324 u32 portHandle[FST_MAX_PORTS];
325
326 /* Count of Tx underflows for stats */
327 u32 transmitBufferUnderflow[FST_MAX_PORTS];
328
329 /* Debounced V.24 control input status */
330 u32 v24DebouncedSts[FST_MAX_PORTS];
331
332 /* Adapter debounce timers. Don't touch */
333 u32 ctsTimer[FST_MAX_PORTS];
334 u32 ctsTimerRun[FST_MAX_PORTS];
335 u32 dcdTimer[FST_MAX_PORTS];
336 u32 dcdTimerRun[FST_MAX_PORTS];
337
338 u32 numberOfPorts; /* Number of ports detected at startup */
339
340 u16 _reserved[64];
341
342 u16 cardMode; /* Bit-mask to enable features:
343 * Bit 0: 1 enables LED identify mode
344 */
345
346 u16 portScheduleOffset;
347
348 struct su_config suConfig; /* TE1 Bits */
349 struct su_status suStatus;
350
351 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of
352 * the structure and marks the end of shared
353 * memory. Adapter code initializes it as
354 * END_SIG.
355 */
356 };
357
358 /* endOfSmcSignature value */
359 #define END_SIG 0x12345678
360
361 /* Mailbox values. (portMailbox) */
362 #define NOP 0 /* No operation */
363 #define ACK 1 /* Positive acknowledgement to PC driver */
364 #define NAK 2 /* Negative acknowledgement to PC driver */
365 #define STARTPORT 3 /* Start an HDLC port */
366 #define STOPPORT 4 /* Stop an HDLC port */
367 #define ABORTTX 5 /* Abort the transmitter for a port */
368 #define SETV24O 6 /* Set V24 outputs */
369
370 /* PLX Chip Register Offsets */
371 #define CNTRL_9052 0x50 /* Control Register */
372 #define CNTRL_9054 0x6c /* Control Register */
373
374 #define INTCSR_9052 0x4c /* Interrupt control/status register */
375 #define INTCSR_9054 0x68 /* Interrupt control/status register */
376
377 /* 9054 DMA Registers */
378 /*
379 * Note that we will be using DMA Channel 0 for copying rx data
380 * and Channel 1 for copying tx data
381 */
382 #define DMAMODE0 0x80
383 #define DMAPADR0 0x84
384 #define DMALADR0 0x88
385 #define DMASIZ0 0x8c
386 #define DMADPR0 0x90
387 #define DMAMODE1 0x94
388 #define DMAPADR1 0x98
389 #define DMALADR1 0x9c
390 #define DMASIZ1 0xa0
391 #define DMADPR1 0xa4
392 #define DMACSR0 0xa8
393 #define DMACSR1 0xa9
394 #define DMAARB 0xac
395 #define DMATHR 0xb0
396 #define DMADAC0 0xb4
397 #define DMADAC1 0xb8
398 #define DMAMARBR 0xac
399
400 #define FST_MIN_DMA_LEN 64
401 #define FST_RX_DMA_INT 0x01
402 #define FST_TX_DMA_INT 0x02
403 #define FST_CARD_INT 0x04
404
405 /* Larger buffers are positioned in memory at offset BFM_BASE */
406 struct buf_window {
407 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
408 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
409 };
410
411 /* Calculate offset of a buffer object within the shared memory window */
412 #define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
413
414 #pragma pack()
415
416 /* Device driver private information
417 * =================================
418 */
419 /* Per port (line or channel) information
420 */
421 struct fst_port_info {
422 struct net_device *dev; /* Device struct - must be first */
423 struct fst_card_info *card; /* Card we're associated with */
424 int index; /* Port index on the card */
425 int hwif; /* Line hardware (lineInterface copy) */
426 int run; /* Port is running */
427 int mode; /* Normal or FarSync raw */
428 int rxpos; /* Next Rx buffer to use */
429 int txpos; /* Next Tx buffer to use */
430 int txipos; /* Next Tx buffer to check for free */
431 int start; /* Indication of start/stop to network */
432 /*
433 * A sixteen entry transmit queue
434 */
435 int txqs; /* index to get next buffer to tx */
436 int txqe; /* index to queue next packet */
437 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */
438 int rxqdepth;
439 };
440
441 /* Per card information
442 */
443 struct fst_card_info {
444 char __iomem *mem; /* Card memory mapped to kernel space */
445 char __iomem *ctlmem; /* Control memory for PCI cards */
446 unsigned int phys_mem; /* Physical memory window address */
447 unsigned int phys_ctlmem; /* Physical control memory address */
448 unsigned int irq; /* Interrupt request line number */
449 unsigned int nports; /* Number of serial ports */
450 unsigned int type; /* Type index of card */
451 unsigned int state; /* State of card */
452 spinlock_t card_lock; /* Lock for SMP access */
453 unsigned short pci_conf; /* PCI card config in I/O space */
454 /* Per port info */
455 struct fst_port_info ports[FST_MAX_PORTS];
456 struct pci_dev *device; /* Information about the pci device */
457 int card_no; /* Inst of the card on the system */
458 int family; /* TxP or TxU */
459 int dmarx_in_progress;
460 int dmatx_in_progress;
461 unsigned long int_count;
462 unsigned long int_time_ave;
463 void *rx_dma_handle_host;
464 dma_addr_t rx_dma_handle_card;
465 void *tx_dma_handle_host;
466 dma_addr_t tx_dma_handle_card;
467 struct sk_buff *dma_skb_rx;
468 struct fst_port_info *dma_port_rx;
469 struct fst_port_info *dma_port_tx;
470 int dma_len_rx;
471 int dma_len_tx;
472 int dma_txpos;
473 int dma_rxpos;
474 };
475
476 /* Convert an HDLC device pointer into a port info pointer and similar */
477 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
478 #define port_to_dev(P) ((P)->dev)
479
480
481 /*
482 * Shared memory window access macros
483 *
484 * We have a nice memory based structure above, which could be directly
485 * mapped on i386 but might not work on other architectures unless we use
486 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
487 * physical offsets so we have to convert. The only saving grace is that
488 * this should all collapse back to a simple indirection eventually.
489 */
490 #define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
491
492 #define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
493 #define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
494 #define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
495
496 #define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
497 #define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
498 #define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
499
500 /*
501 * Debug support
502 */
503 #if FST_DEBUG
504
505 static int fst_debug_mask = { FST_DEBUG };
506
507 /* Most common debug activity is to print something if the corresponding bit
508 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
509 * support variable numbers of macro parameters. The inverted if prevents us
510 * eating someone else's else clause.
511 */
512 #define dbg(F,fmt,A...) if ( ! ( fst_debug_mask & (F))) \
513 ; \
514 else \
515 printk ( KERN_DEBUG FST_NAME ": " fmt, ## A )
516
517 #else
518 #define dbg(X...) /* NOP */
519 #endif
520
521 /* Printing short cuts
522 */
523 #define printk_err(fmt,A...) printk ( KERN_ERR FST_NAME ": " fmt, ## A )
524 #define printk_warn(fmt,A...) printk ( KERN_WARNING FST_NAME ": " fmt, ## A )
525 #define printk_info(fmt,A...) printk ( KERN_INFO FST_NAME ": " fmt, ## A )
526
527 /*
528 * PCI ID lookup table
529 */
530 static struct pci_device_id fst_pci_dev_id[] __devinitdata = {
531 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,
532 PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
533
534 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,
535 PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
536
537 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,
538 PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
539
540 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,
541 PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
542
543 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,
544 PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
545
546 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,
547 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
548
549 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,
550 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
551 {0,} /* End */
552 };
553
554 MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
555
556 /*
557 * Device Driver Work Queues
558 *
559 * So that we don't spend too much time processing events in the
560 * Interrupt Service routine, we will declare a work queue per Card
561 * and make the ISR schedule a task in the queue for later execution.
562 * In the 2.4 Kernel we used to use the immediate queue for BH's
563 * Now that they are gone, tasklets seem to be much better than work
564 * queues.
565 */
566
567 static void do_bottom_half_tx(struct fst_card_info *card);
568 static void do_bottom_half_rx(struct fst_card_info *card);
569 static void fst_process_tx_work_q(unsigned long work_q);
570 static void fst_process_int_work_q(unsigned long work_q);
571
572 static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0);
573 static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0);
574
575 static struct fst_card_info *fst_card_array[FST_MAX_CARDS];
576 static spinlock_t fst_work_q_lock;
577 static u64 fst_work_txq;
578 static u64 fst_work_intq;
579
580 static void
581 fst_q_work_item(u64 * queue, int card_index)
582 {
583 unsigned long flags;
584 u64 mask;
585
586 /*
587 * Grab the queue exclusively
588 */
589 spin_lock_irqsave(&fst_work_q_lock, flags);
590
591 /*
592 * Making an entry in the queue is simply a matter of setting
593 * a bit for the card indicating that there is work to do in the
594 * bottom half for the card. Note the limitation of 64 cards.
595 * That ought to be enough
596 */
597 mask = 1 << card_index;
598 *queue |= mask;
599 spin_unlock_irqrestore(&fst_work_q_lock, flags);
600 }
601
602 static void
603 fst_process_tx_work_q(unsigned long /*void **/work_q)
604 {
605 unsigned long flags;
606 u64 work_txq;
607 int i;
608
609 /*
610 * Grab the queue exclusively
611 */
612 dbg(DBG_TX, "fst_process_tx_work_q\n");
613 spin_lock_irqsave(&fst_work_q_lock, flags);
614 work_txq = fst_work_txq;
615 fst_work_txq = 0;
616 spin_unlock_irqrestore(&fst_work_q_lock, flags);
617
618 /*
619 * Call the bottom half for each card with work waiting
620 */
621 for (i = 0; i < FST_MAX_CARDS; i++) {
622 if (work_txq & 0x01) {
623 if (fst_card_array[i] != NULL) {
624 dbg(DBG_TX, "Calling tx bh for card %d\n", i);
625 do_bottom_half_tx(fst_card_array[i]);
626 }
627 }
628 work_txq = work_txq >> 1;
629 }
630 }
631
632 static void
633 fst_process_int_work_q(unsigned long /*void **/work_q)
634 {
635 unsigned long flags;
636 u64 work_intq;
637 int i;
638
639 /*
640 * Grab the queue exclusively
641 */
642 dbg(DBG_INTR, "fst_process_int_work_q\n");
643 spin_lock_irqsave(&fst_work_q_lock, flags);
644 work_intq = fst_work_intq;
645 fst_work_intq = 0;
646 spin_unlock_irqrestore(&fst_work_q_lock, flags);
647
648 /*
649 * Call the bottom half for each card with work waiting
650 */
651 for (i = 0; i < FST_MAX_CARDS; i++) {
652 if (work_intq & 0x01) {
653 if (fst_card_array[i] != NULL) {
654 dbg(DBG_INTR,
655 "Calling rx & tx bh for card %d\n", i);
656 do_bottom_half_rx(fst_card_array[i]);
657 do_bottom_half_tx(fst_card_array[i]);
658 }
659 }
660 work_intq = work_intq >> 1;
661 }
662 }
663
664 /* Card control functions
665 * ======================
666 */
667 /* Place the processor in reset state
668 *
669 * Used to be a simple write to card control space but a glitch in the latest
670 * AMD Am186CH processor means that we now have to do it by asserting and de-
671 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
672 * at offset 9052_CNTRL. Note the updates for the TXU.
673 */
674 static inline void
675 fst_cpureset(struct fst_card_info *card)
676 {
677 unsigned char interrupt_line_register;
678 unsigned long j = jiffies + 1;
679 unsigned int regval;
680
681 if (card->family == FST_FAMILY_TXU) {
682 if (pci_read_config_byte
683 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
684 dbg(DBG_ASS,
685 "Error in reading interrupt line register\n");
686 }
687 /*
688 * Assert PLX software reset and Am186 hardware reset
689 * and then deassert the PLX software reset but 186 still in reset
690 */
691 outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
692 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
693 /*
694 * We are delaying here to allow the 9054 to reset itself
695 */
696 j = jiffies + 1;
697 while (jiffies < j)
698 /* Do nothing */ ;
699 outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
700 /*
701 * We are delaying here to allow the 9054 to reload its eeprom
702 */
703 j = jiffies + 1;
704 while (jiffies < j)
705 /* Do nothing */ ;
706 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
707
708 if (pci_write_config_byte
709 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
710 dbg(DBG_ASS,
711 "Error in writing interrupt line register\n");
712 }
713
714 } else {
715 regval = inl(card->pci_conf + CNTRL_9052);
716
717 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
718 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
719 }
720 }
721
722 /* Release the processor from reset
723 */
724 static inline void
725 fst_cpurelease(struct fst_card_info *card)
726 {
727 if (card->family == FST_FAMILY_TXU) {
728 /*
729 * Force posted writes to complete
730 */
731 (void) readb(card->mem);
732
733 /*
734 * Release LRESET DO = 1
735 * Then release Local Hold, DO = 1
736 */
737 outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
738 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
739 } else {
740 (void) readb(card->ctlmem);
741 }
742 }
743
744 /* Clear the cards interrupt flag
745 */
746 static inline void
747 fst_clear_intr(struct fst_card_info *card)
748 {
749 if (card->family == FST_FAMILY_TXU) {
750 (void) readb(card->ctlmem);
751 } else {
752 /* Poke the appropriate PLX chip register (same as enabling interrupts)
753 */
754 outw(0x0543, card->pci_conf + INTCSR_9052);
755 }
756 }
757
758 /* Enable card interrupts
759 */
760 static inline void
761 fst_enable_intr(struct fst_card_info *card)
762 {
763 if (card->family == FST_FAMILY_TXU) {
764 outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
765 } else {
766 outw(0x0543, card->pci_conf + INTCSR_9052);
767 }
768 }
769
770 /* Disable card interrupts
771 */
772 static inline void
773 fst_disable_intr(struct fst_card_info *card)
774 {
775 if (card->family == FST_FAMILY_TXU) {
776 outl(0x00000000, card->pci_conf + INTCSR_9054);
777 } else {
778 outw(0x0000, card->pci_conf + INTCSR_9052);
779 }
780 }
781
782 /* Process the result of trying to pass a received frame up the stack
783 */
784 static void
785 fst_process_rx_status(int rx_status, char *name)
786 {
787 switch (rx_status) {
788 case NET_RX_SUCCESS:
789 {
790 /*
791 * Nothing to do here
792 */
793 break;
794 }
795
796 case NET_RX_CN_LOW:
797 {
798 dbg(DBG_ASS, "%s: Receive Low Congestion\n", name);
799 break;
800 }
801
802 case NET_RX_CN_MOD:
803 {
804 dbg(DBG_ASS, "%s: Receive Moderate Congestion\n", name);
805 break;
806 }
807
808 case NET_RX_CN_HIGH:
809 {
810 dbg(DBG_ASS, "%s: Receive High Congestion\n", name);
811 break;
812 }
813
814 case NET_RX_DROP:
815 {
816 dbg(DBG_ASS, "%s: Received packet dropped\n", name);
817 break;
818 }
819 }
820 }
821
822 /* Initilaise DMA for PLX 9054
823 */
824 static inline void
825 fst_init_dma(struct fst_card_info *card)
826 {
827 /*
828 * This is only required for the PLX 9054
829 */
830 if (card->family == FST_FAMILY_TXU) {
831 pci_set_master(card->device);
832 outl(0x00020441, card->pci_conf + DMAMODE0);
833 outl(0x00020441, card->pci_conf + DMAMODE1);
834 outl(0x0, card->pci_conf + DMATHR);
835 }
836 }
837
838 /* Tx dma complete interrupt
839 */
840 static void
841 fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
842 int len, int txpos)
843 {
844 struct net_device *dev = port_to_dev(port);
845
846 /*
847 * Everything is now set, just tell the card to go
848 */
849 dbg(DBG_TX, "fst_tx_dma_complete\n");
850 FST_WRB(card, txDescrRing[port->index][txpos].bits,
851 DMA_OWN | TX_STP | TX_ENP);
852 dev->stats.tx_packets++;
853 dev->stats.tx_bytes += len;
854 dev->trans_start = jiffies;
855 }
856
857 /*
858 * Mark it for our own raw sockets interface
859 */
860 static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev)
861 {
862 skb->dev = dev;
863 skb_reset_mac_header(skb);
864 skb->pkt_type = PACKET_HOST;
865 return htons(ETH_P_CUST);
866 }
867
868 /* Rx dma complete interrupt
869 */
870 static void
871 fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
872 int len, struct sk_buff *skb, int rxp)
873 {
874 struct net_device *dev = port_to_dev(port);
875 int pi;
876 int rx_status;
877
878 dbg(DBG_TX, "fst_rx_dma_complete\n");
879 pi = port->index;
880 memcpy(skb_put(skb, len), card->rx_dma_handle_host, len);
881
882 /* Reset buffer descriptor */
883 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
884
885 /* Update stats */
886 dev->stats.rx_packets++;
887 dev->stats.rx_bytes += len;
888
889 /* Push upstream */
890 dbg(DBG_RX, "Pushing the frame up the stack\n");
891 if (port->mode == FST_RAW)
892 skb->protocol = farsync_type_trans(skb, dev);
893 else
894 skb->protocol = hdlc_type_trans(skb, dev);
895 rx_status = netif_rx(skb);
896 fst_process_rx_status(rx_status, port_to_dev(port)->name);
897 if (rx_status == NET_RX_DROP)
898 dev->stats.rx_dropped++;
899 }
900
901 /*
902 * Receive a frame through the DMA
903 */
904 static inline void
905 fst_rx_dma(struct fst_card_info *card, unsigned char *skb,
906 unsigned char *mem, int len)
907 {
908 /*
909 * This routine will setup the DMA and start it
910 */
911
912 dbg(DBG_RX, "In fst_rx_dma %p %p %d\n", skb, mem, len);
913 if (card->dmarx_in_progress) {
914 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
915 }
916
917 outl((unsigned long) skb, card->pci_conf + DMAPADR0); /* Copy to here */
918 outl((unsigned long) mem, card->pci_conf + DMALADR0); /* from here */
919 outl(len, card->pci_conf + DMASIZ0); /* for this length */
920 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */
921
922 /*
923 * We use the dmarx_in_progress flag to flag the channel as busy
924 */
925 card->dmarx_in_progress = 1;
926 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */
927 }
928
929 /*
930 * Send a frame through the DMA
931 */
932 static inline void
933 fst_tx_dma(struct fst_card_info *card, unsigned char *skb,
934 unsigned char *mem, int len)
935 {
936 /*
937 * This routine will setup the DMA and start it.
938 */
939
940 dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len);
941 if (card->dmatx_in_progress) {
942 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
943 }
944
945 outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */
946 outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */
947 outl(len, card->pci_conf + DMASIZ1); /* for this length */
948 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */
949
950 /*
951 * We use the dmatx_in_progress to flag the channel as busy
952 */
953 card->dmatx_in_progress = 1;
954 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */
955 }
956
957 /* Issue a Mailbox command for a port.
958 * Note we issue them on a fire and forget basis, not expecting to see an
959 * error and not waiting for completion.
960 */
961 static void
962 fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
963 {
964 struct fst_card_info *card;
965 unsigned short mbval;
966 unsigned long flags;
967 int safety;
968
969 card = port->card;
970 spin_lock_irqsave(&card->card_lock, flags);
971 mbval = FST_RDW(card, portMailbox[port->index][0]);
972
973 safety = 0;
974 /* Wait for any previous command to complete */
975 while (mbval > NAK) {
976 spin_unlock_irqrestore(&card->card_lock, flags);
977 schedule_timeout_uninterruptible(1);
978 spin_lock_irqsave(&card->card_lock, flags);
979
980 if (++safety > 2000) {
981 printk_err("Mailbox safety timeout\n");
982 break;
983 }
984
985 mbval = FST_RDW(card, portMailbox[port->index][0]);
986 }
987 if (safety > 0) {
988 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
989 }
990 if (mbval == NAK) {
991 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
992 }
993
994 FST_WRW(card, portMailbox[port->index][0], cmd);
995
996 if (cmd == ABORTTX || cmd == STARTPORT) {
997 port->txpos = 0;
998 port->txipos = 0;
999 port->start = 0;
1000 }
1001
1002 spin_unlock_irqrestore(&card->card_lock, flags);
1003 }
1004
1005 /* Port output signals control
1006 */
1007 static inline void
1008 fst_op_raise(struct fst_port_info *port, unsigned int outputs)
1009 {
1010 outputs |= FST_RDL(port->card, v24OpSts[port->index]);
1011 FST_WRL(port->card, v24OpSts[port->index], outputs);
1012
1013 if (port->run)
1014 fst_issue_cmd(port, SETV24O);
1015 }
1016
1017 static inline void
1018 fst_op_lower(struct fst_port_info *port, unsigned int outputs)
1019 {
1020 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);
1021 FST_WRL(port->card, v24OpSts[port->index], outputs);
1022
1023 if (port->run)
1024 fst_issue_cmd(port, SETV24O);
1025 }
1026
1027 /*
1028 * Setup port Rx buffers
1029 */
1030 static void
1031 fst_rx_config(struct fst_port_info *port)
1032 {
1033 int i;
1034 int pi;
1035 unsigned int offset;
1036 unsigned long flags;
1037 struct fst_card_info *card;
1038
1039 pi = port->index;
1040 card = port->card;
1041 spin_lock_irqsave(&card->card_lock, flags);
1042 for (i = 0; i < NUM_RX_BUFFER; i++) {
1043 offset = BUF_OFFSET(rxBuffer[pi][i][0]);
1044
1045 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset);
1046 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16));
1047 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));
1048 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);
1049 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);
1050 }
1051 port->rxpos = 0;
1052 spin_unlock_irqrestore(&card->card_lock, flags);
1053 }
1054
1055 /*
1056 * Setup port Tx buffers
1057 */
1058 static void
1059 fst_tx_config(struct fst_port_info *port)
1060 {
1061 int i;
1062 int pi;
1063 unsigned int offset;
1064 unsigned long flags;
1065 struct fst_card_info *card;
1066
1067 pi = port->index;
1068 card = port->card;
1069 spin_lock_irqsave(&card->card_lock, flags);
1070 for (i = 0; i < NUM_TX_BUFFER; i++) {
1071 offset = BUF_OFFSET(txBuffer[pi][i][0]);
1072
1073 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset);
1074 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16));
1075 FST_WRW(card, txDescrRing[pi][i].bcnt, 0);
1076 FST_WRB(card, txDescrRing[pi][i].bits, 0);
1077 }
1078 port->txpos = 0;
1079 port->txipos = 0;
1080 port->start = 0;
1081 spin_unlock_irqrestore(&card->card_lock, flags);
1082 }
1083
1084 /* TE1 Alarm change interrupt event
1085 */
1086 static void
1087 fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)
1088 {
1089 u8 los;
1090 u8 rra;
1091 u8 ais;
1092
1093 los = FST_RDB(card, suStatus.lossOfSignal);
1094 rra = FST_RDB(card, suStatus.receiveRemoteAlarm);
1095 ais = FST_RDB(card, suStatus.alarmIndicationSignal);
1096
1097 if (los) {
1098 /*
1099 * Lost the link
1100 */
1101 if (netif_carrier_ok(port_to_dev(port))) {
1102 dbg(DBG_INTR, "Net carrier off\n");
1103 netif_carrier_off(port_to_dev(port));
1104 }
1105 } else {
1106 /*
1107 * Link available
1108 */
1109 if (!netif_carrier_ok(port_to_dev(port))) {
1110 dbg(DBG_INTR, "Net carrier on\n");
1111 netif_carrier_on(port_to_dev(port));
1112 }
1113 }
1114
1115 if (los)
1116 dbg(DBG_INTR, "Assert LOS Alarm\n");
1117 else
1118 dbg(DBG_INTR, "De-assert LOS Alarm\n");
1119 if (rra)
1120 dbg(DBG_INTR, "Assert RRA Alarm\n");
1121 else
1122 dbg(DBG_INTR, "De-assert RRA Alarm\n");
1123
1124 if (ais)
1125 dbg(DBG_INTR, "Assert AIS Alarm\n");
1126 else
1127 dbg(DBG_INTR, "De-assert AIS Alarm\n");
1128 }
1129
1130 /* Control signal change interrupt event
1131 */
1132 static void
1133 fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)
1134 {
1135 int signals;
1136
1137 signals = FST_RDL(card, v24DebouncedSts[port->index]);
1138
1139 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
1140 ? IPSTS_INDICATE : IPSTS_DCD)) {
1141 if (!netif_carrier_ok(port_to_dev(port))) {
1142 dbg(DBG_INTR, "DCD active\n");
1143 netif_carrier_on(port_to_dev(port));
1144 }
1145 } else {
1146 if (netif_carrier_ok(port_to_dev(port))) {
1147 dbg(DBG_INTR, "DCD lost\n");
1148 netif_carrier_off(port_to_dev(port));
1149 }
1150 }
1151 }
1152
1153 /* Log Rx Errors
1154 */
1155 static void
1156 fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1157 unsigned char dmabits, int rxp, unsigned short len)
1158 {
1159 struct net_device *dev = port_to_dev(port);
1160
1161 /*
1162 * Increment the appropriate error counter
1163 */
1164 dev->stats.rx_errors++;
1165 if (dmabits & RX_OFLO) {
1166 dev->stats.rx_fifo_errors++;
1167 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
1168 card->card_no, port->index, rxp);
1169 }
1170 if (dmabits & RX_CRC) {
1171 dev->stats.rx_crc_errors++;
1172 dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
1173 card->card_no, port->index);
1174 }
1175 if (dmabits & RX_FRAM) {
1176 dev->stats.rx_frame_errors++;
1177 dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
1178 card->card_no, port->index);
1179 }
1180 if (dmabits == (RX_STP | RX_ENP)) {
1181 dev->stats.rx_length_errors++;
1182 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
1183 len, card->card_no, port->index);
1184 }
1185 }
1186
1187 /* Rx Error Recovery
1188 */
1189 static void
1190 fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1191 unsigned char dmabits, int rxp, unsigned short len)
1192 {
1193 int i;
1194 int pi;
1195
1196 pi = port->index;
1197 /*
1198 * Discard buffer descriptors until we see the start of the
1199 * next frame. Note that for long frames this could be in
1200 * a subsequent interrupt.
1201 */
1202 i = 0;
1203 while ((dmabits & (DMA_OWN | RX_STP)) == 0) {
1204 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1205 rxp = (rxp+1) % NUM_RX_BUFFER;
1206 if (++i > NUM_RX_BUFFER) {
1207 dbg(DBG_ASS, "intr_rx: Discarding more bufs"
1208 " than we have\n");
1209 break;
1210 }
1211 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1212 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);
1213 }
1214 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);
1215
1216 /* Discard the terminal buffer */
1217 if (!(dmabits & DMA_OWN)) {
1218 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1219 rxp = (rxp+1) % NUM_RX_BUFFER;
1220 }
1221 port->rxpos = rxp;
1222 return;
1223
1224 }
1225
1226 /* Rx complete interrupt
1227 */
1228 static void
1229 fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1230 {
1231 unsigned char dmabits;
1232 int pi;
1233 int rxp;
1234 int rx_status;
1235 unsigned short len;
1236 struct sk_buff *skb;
1237 struct net_device *dev = port_to_dev(port);
1238
1239 /* Check we have a buffer to process */
1240 pi = port->index;
1241 rxp = port->rxpos;
1242 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1243 if (dmabits & DMA_OWN) {
1244 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",
1245 pi, rxp);
1246 return;
1247 }
1248 if (card->dmarx_in_progress) {
1249 return;
1250 }
1251
1252 /* Get buffer length */
1253 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);
1254 /* Discard the CRC */
1255 len -= 2;
1256 if (len == 0) {
1257 /*
1258 * This seems to happen on the TE1 interface sometimes
1259 * so throw the frame away and log the event.
1260 */
1261 printk_err("Frame received with 0 length. Card %d Port %d\n",
1262 card->card_no, port->index);
1263 /* Return descriptor to card */
1264 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1265
1266 rxp = (rxp+1) % NUM_RX_BUFFER;
1267 port->rxpos = rxp;
1268 return;
1269 }
1270
1271 /* Check buffer length and for other errors. We insist on one packet
1272 * in one buffer. This simplifies things greatly and since we've
1273 * allocated 8K it shouldn't be a real world limitation
1274 */
1275 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);
1276 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {
1277 fst_log_rx_error(card, port, dmabits, rxp, len);
1278 fst_recover_rx_error(card, port, dmabits, rxp, len);
1279 return;
1280 }
1281
1282 /* Allocate SKB */
1283 if ((skb = dev_alloc_skb(len)) == NULL) {
1284 dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
1285
1286 dev->stats.rx_dropped++;
1287
1288 /* Return descriptor to card */
1289 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1290
1291 rxp = (rxp+1) % NUM_RX_BUFFER;
1292 port->rxpos = rxp;
1293 return;
1294 }
1295
1296 /*
1297 * We know the length we need to receive, len.
1298 * It's not worth using the DMA for reads of less than
1299 * FST_MIN_DMA_LEN
1300 */
1301
1302 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) {
1303 memcpy_fromio(skb_put(skb, len),
1304 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),
1305 len);
1306
1307 /* Reset buffer descriptor */
1308 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1309
1310 /* Update stats */
1311 dev->stats.rx_packets++;
1312 dev->stats.rx_bytes += len;
1313
1314 /* Push upstream */
1315 dbg(DBG_RX, "Pushing frame up the stack\n");
1316 if (port->mode == FST_RAW)
1317 skb->protocol = farsync_type_trans(skb, dev);
1318 else
1319 skb->protocol = hdlc_type_trans(skb, dev);
1320 rx_status = netif_rx(skb);
1321 fst_process_rx_status(rx_status, port_to_dev(port)->name);
1322 if (rx_status == NET_RX_DROP)
1323 dev->stats.rx_dropped++;
1324 } else {
1325 card->dma_skb_rx = skb;
1326 card->dma_port_rx = port;
1327 card->dma_len_rx = len;
1328 card->dma_rxpos = rxp;
1329 fst_rx_dma(card, (char *) card->rx_dma_handle_card,
1330 (char *) BUF_OFFSET(rxBuffer[pi][rxp][0]), len);
1331 }
1332 if (rxp != port->rxpos) {
1333 dbg(DBG_ASS, "About to increment rxpos by more than 1\n");
1334 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);
1335 }
1336 rxp = (rxp+1) % NUM_RX_BUFFER;
1337 port->rxpos = rxp;
1338 }
1339
1340 /*
1341 * The bottom halfs to the ISR
1342 *
1343 */
1344
1345 static void
1346 do_bottom_half_tx(struct fst_card_info *card)
1347 {
1348 struct fst_port_info *port;
1349 int pi;
1350 int txq_length;
1351 struct sk_buff *skb;
1352 unsigned long flags;
1353 struct net_device *dev;
1354
1355 /*
1356 * Find a free buffer for the transmit
1357 * Step through each port on this card
1358 */
1359
1360 dbg(DBG_TX, "do_bottom_half_tx\n");
1361 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1362 if (!port->run)
1363 continue;
1364
1365 dev = port_to_dev(port);
1366 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
1367 DMA_OWN)
1368 && !(card->dmatx_in_progress)) {
1369 /*
1370 * There doesn't seem to be a txdone event per-se
1371 * We seem to have to deduce it, by checking the DMA_OWN
1372 * bit on the next buffer we think we can use
1373 */
1374 spin_lock_irqsave(&card->card_lock, flags);
1375 if ((txq_length = port->txqe - port->txqs) < 0) {
1376 /*
1377 * This is the case where one has wrapped and the
1378 * maths gives us a negative number
1379 */
1380 txq_length = txq_length + FST_TXQ_DEPTH;
1381 }
1382 spin_unlock_irqrestore(&card->card_lock, flags);
1383 if (txq_length > 0) {
1384 /*
1385 * There is something to send
1386 */
1387 spin_lock_irqsave(&card->card_lock, flags);
1388 skb = port->txq[port->txqs];
1389 port->txqs++;
1390 if (port->txqs == FST_TXQ_DEPTH) {
1391 port->txqs = 0;
1392 }
1393 spin_unlock_irqrestore(&card->card_lock, flags);
1394 /*
1395 * copy the data and set the required indicators on the
1396 * card.
1397 */
1398 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,
1399 cnv_bcnt(skb->len));
1400 if ((skb->len < FST_MIN_DMA_LEN)
1401 || (card->family == FST_FAMILY_TXP)) {
1402 /* Enqueue the packet with normal io */
1403 memcpy_toio(card->mem +
1404 BUF_OFFSET(txBuffer[pi]
1405 [port->
1406 txpos][0]),
1407 skb->data, skb->len);
1408 FST_WRB(card,
1409 txDescrRing[pi][port->txpos].
1410 bits,
1411 DMA_OWN | TX_STP | TX_ENP);
1412 dev->stats.tx_packets++;
1413 dev->stats.tx_bytes += skb->len;
1414 dev->trans_start = jiffies;
1415 } else {
1416 /* Or do it through dma */
1417 memcpy(card->tx_dma_handle_host,
1418 skb->data, skb->len);
1419 card->dma_port_tx = port;
1420 card->dma_len_tx = skb->len;
1421 card->dma_txpos = port->txpos;
1422 fst_tx_dma(card,
1423 (char *) card->
1424 tx_dma_handle_card,
1425 (char *)
1426 BUF_OFFSET(txBuffer[pi]
1427 [port->txpos][0]),
1428 skb->len);
1429 }
1430 if (++port->txpos >= NUM_TX_BUFFER)
1431 port->txpos = 0;
1432 /*
1433 * If we have flow control on, can we now release it?
1434 */
1435 if (port->start) {
1436 if (txq_length < fst_txq_low) {
1437 netif_wake_queue(port_to_dev
1438 (port));
1439 port->start = 0;
1440 }
1441 }
1442 dev_kfree_skb(skb);
1443 } else {
1444 /*
1445 * Nothing to send so break out of the while loop
1446 */
1447 break;
1448 }
1449 }
1450 }
1451 }
1452
1453 static void
1454 do_bottom_half_rx(struct fst_card_info *card)
1455 {
1456 struct fst_port_info *port;
1457 int pi;
1458 int rx_count = 0;
1459
1460 /* Check for rx completions on all ports on this card */
1461 dbg(DBG_RX, "do_bottom_half_rx\n");
1462 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1463 if (!port->run)
1464 continue;
1465
1466 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)
1467 & DMA_OWN) && !(card->dmarx_in_progress)) {
1468 if (rx_count > fst_max_reads) {
1469 /*
1470 * Don't spend forever in receive processing
1471 * Schedule another event
1472 */
1473 fst_q_work_item(&fst_work_intq, card->card_no);
1474 tasklet_schedule(&fst_int_task);
1475 break; /* Leave the loop */
1476 }
1477 fst_intr_rx(card, port);
1478 rx_count++;
1479 }
1480 }
1481 }
1482
1483 /*
1484 * The interrupt service routine
1485 * Dev_id is our fst_card_info pointer
1486 */
1487 static irqreturn_t
1488 fst_intr(int dummy, void *dev_id)
1489 {
1490 struct fst_card_info *card = dev_id;
1491 struct fst_port_info *port;
1492 int rdidx; /* Event buffer indices */
1493 int wridx;
1494 int event; /* Actual event for processing */
1495 unsigned int dma_intcsr = 0;
1496 unsigned int do_card_interrupt;
1497 unsigned int int_retry_count;
1498
1499 /*
1500 * Check to see if the interrupt was for this card
1501 * return if not
1502 * Note that the call to clear the interrupt is important
1503 */
1504 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card);
1505 if (card->state != FST_RUNNING) {
1506 printk_err
1507 ("Interrupt received for card %d in a non running state (%d)\n",
1508 card->card_no, card->state);
1509
1510 /*
1511 * It is possible to really be running, i.e. we have re-loaded
1512 * a running card
1513 * Clear and reprime the interrupt source
1514 */
1515 fst_clear_intr(card);
1516 return IRQ_HANDLED;
1517 }
1518
1519 /* Clear and reprime the interrupt source */
1520 fst_clear_intr(card);
1521
1522 /*
1523 * Is the interrupt for this card (handshake == 1)
1524 */
1525 do_card_interrupt = 0;
1526 if (FST_RDB(card, interruptHandshake) == 1) {
1527 do_card_interrupt += FST_CARD_INT;
1528 /* Set the software acknowledge */
1529 FST_WRB(card, interruptHandshake, 0xEE);
1530 }
1531 if (card->family == FST_FAMILY_TXU) {
1532 /*
1533 * Is it a DMA Interrupt
1534 */
1535 dma_intcsr = inl(card->pci_conf + INTCSR_9054);
1536 if (dma_intcsr & 0x00200000) {
1537 /*
1538 * DMA Channel 0 (Rx transfer complete)
1539 */
1540 dbg(DBG_RX, "DMA Rx xfer complete\n");
1541 outb(0x8, card->pci_conf + DMACSR0);
1542 fst_rx_dma_complete(card, card->dma_port_rx,
1543 card->dma_len_rx, card->dma_skb_rx,
1544 card->dma_rxpos);
1545 card->dmarx_in_progress = 0;
1546 do_card_interrupt += FST_RX_DMA_INT;
1547 }
1548 if (dma_intcsr & 0x00400000) {
1549 /*
1550 * DMA Channel 1 (Tx transfer complete)
1551 */
1552 dbg(DBG_TX, "DMA Tx xfer complete\n");
1553 outb(0x8, card->pci_conf + DMACSR1);
1554 fst_tx_dma_complete(card, card->dma_port_tx,
1555 card->dma_len_tx, card->dma_txpos);
1556 card->dmatx_in_progress = 0;
1557 do_card_interrupt += FST_TX_DMA_INT;
1558 }
1559 }
1560
1561 /*
1562 * Have we been missing Interrupts
1563 */
1564 int_retry_count = FST_RDL(card, interruptRetryCount);
1565 if (int_retry_count) {
1566 dbg(DBG_ASS, "Card %d int_retry_count is %d\n",
1567 card->card_no, int_retry_count);
1568 FST_WRL(card, interruptRetryCount, 0);
1569 }
1570
1571 if (!do_card_interrupt) {
1572 return IRQ_HANDLED;
1573 }
1574
1575 /* Scehdule the bottom half of the ISR */
1576 fst_q_work_item(&fst_work_intq, card->card_no);
1577 tasklet_schedule(&fst_int_task);
1578
1579 /* Drain the event queue */
1580 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;
1581 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;
1582 while (rdidx != wridx) {
1583 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);
1584 port = &card->ports[event & 0x03];
1585
1586 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);
1587
1588 switch (event) {
1589 case TE1_ALMA:
1590 dbg(DBG_INTR, "TE1 Alarm intr\n");
1591 if (port->run)
1592 fst_intr_te1_alarm(card, port);
1593 break;
1594
1595 case CTLA_CHG:
1596 case CTLB_CHG:
1597 case CTLC_CHG:
1598 case CTLD_CHG:
1599 if (port->run)
1600 fst_intr_ctlchg(card, port);
1601 break;
1602
1603 case ABTA_SENT:
1604 case ABTB_SENT:
1605 case ABTC_SENT:
1606 case ABTD_SENT:
1607 dbg(DBG_TX, "Abort complete port %d\n", port->index);
1608 break;
1609
1610 case TXA_UNDF:
1611 case TXB_UNDF:
1612 case TXC_UNDF:
1613 case TXD_UNDF:
1614 /* Difficult to see how we'd get this given that we
1615 * always load up the entire packet for DMA.
1616 */
1617 dbg(DBG_TX, "Tx underflow port %d\n", port->index);
1618 port_to_dev(port)->stats.tx_errors++;
1619 port_to_dev(port)->stats.tx_fifo_errors++;
1620 dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
1621 card->card_no, port->index);
1622 break;
1623
1624 case INIT_CPLT:
1625 dbg(DBG_INIT, "Card init OK intr\n");
1626 break;
1627
1628 case INIT_FAIL:
1629 dbg(DBG_INIT, "Card init FAILED intr\n");
1630 card->state = FST_IFAILED;
1631 break;
1632
1633 default:
1634 printk_err("intr: unknown card event %d. ignored\n",
1635 event);
1636 break;
1637 }
1638
1639 /* Bump and wrap the index */
1640 if (++rdidx >= MAX_CIRBUFF)
1641 rdidx = 0;
1642 }
1643 FST_WRB(card, interruptEvent.rdindex, rdidx);
1644 return IRQ_HANDLED;
1645 }
1646
1647 /* Check that the shared memory configuration is one that we can handle
1648 * and that some basic parameters are correct
1649 */
1650 static void
1651 check_started_ok(struct fst_card_info *card)
1652 {
1653 int i;
1654
1655 /* Check structure version and end marker */
1656 if (FST_RDW(card, smcVersion) != SMC_VERSION) {
1657 printk_err("Bad shared memory version %d expected %d\n",
1658 FST_RDW(card, smcVersion), SMC_VERSION);
1659 card->state = FST_BADVERSION;
1660 return;
1661 }
1662 if (FST_RDL(card, endOfSmcSignature) != END_SIG) {
1663 printk_err("Missing shared memory signature\n");
1664 card->state = FST_BADVERSION;
1665 return;
1666 }
1667 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1668 if ((i = FST_RDB(card, taskStatus)) == 0x01) {
1669 card->state = FST_RUNNING;
1670 } else if (i == 0xFF) {
1671 printk_err("Firmware initialisation failed. Card halted\n");
1672 card->state = FST_HALTED;
1673 return;
1674 } else if (i != 0x00) {
1675 printk_err("Unknown firmware status 0x%x\n", i);
1676 card->state = FST_HALTED;
1677 return;
1678 }
1679
1680 /* Finally check the number of ports reported by firmware against the
1681 * number we assumed at card detection. Should never happen with
1682 * existing firmware etc so we just report it for the moment.
1683 */
1684 if (FST_RDL(card, numberOfPorts) != card->nports) {
1685 printk_warn("Port count mismatch on card %d."
1686 " Firmware thinks %d we say %d\n", card->card_no,
1687 FST_RDL(card, numberOfPorts), card->nports);
1688 }
1689 }
1690
1691 static int
1692 set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,
1693 struct fstioc_info *info)
1694 {
1695 int err;
1696 unsigned char my_framing;
1697
1698 /* Set things according to the user set valid flags
1699 * Several of the old options have been invalidated/replaced by the
1700 * generic hdlc package.
1701 */
1702 err = 0;
1703 if (info->valid & FSTVAL_PROTO) {
1704 if (info->proto == FST_RAW)
1705 port->mode = FST_RAW;
1706 else
1707 port->mode = FST_GEN_HDLC;
1708 }
1709
1710 if (info->valid & FSTVAL_CABLE)
1711 err = -EINVAL;
1712
1713 if (info->valid & FSTVAL_SPEED)
1714 err = -EINVAL;
1715
1716 if (info->valid & FSTVAL_PHASE)
1717 FST_WRB(card, portConfig[port->index].invertClock,
1718 info->invertClock);
1719 if (info->valid & FSTVAL_MODE)
1720 FST_WRW(card, cardMode, info->cardMode);
1721 if (info->valid & FSTVAL_TE1) {
1722 FST_WRL(card, suConfig.dataRate, info->lineSpeed);
1723 FST_WRB(card, suConfig.clocking, info->clockSource);
1724 my_framing = FRAMING_E1;
1725 if (info->framing == E1)
1726 my_framing = FRAMING_E1;
1727 if (info->framing == T1)
1728 my_framing = FRAMING_T1;
1729 if (info->framing == J1)
1730 my_framing = FRAMING_J1;
1731 FST_WRB(card, suConfig.framing, my_framing);
1732 FST_WRB(card, suConfig.structure, info->structure);
1733 FST_WRB(card, suConfig.interface, info->interface);
1734 FST_WRB(card, suConfig.coding, info->coding);
1735 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);
1736 FST_WRB(card, suConfig.equalizer, info->equalizer);
1737 FST_WRB(card, suConfig.transparentMode, info->transparentMode);
1738 FST_WRB(card, suConfig.loopMode, info->loopMode);
1739 FST_WRB(card, suConfig.range, info->range);
1740 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);
1741 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);
1742 FST_WRB(card, suConfig.startingSlot, info->startingSlot);
1743 FST_WRB(card, suConfig.losThreshold, info->losThreshold);
1744 if (info->idleCode)
1745 FST_WRB(card, suConfig.enableIdleCode, 1);
1746 else
1747 FST_WRB(card, suConfig.enableIdleCode, 0);
1748 FST_WRB(card, suConfig.idleCode, info->idleCode);
1749 #if FST_DEBUG
1750 if (info->valid & FSTVAL_TE1) {
1751 printk("Setting TE1 data\n");
1752 printk("Line Speed = %d\n", info->lineSpeed);
1753 printk("Start slot = %d\n", info->startingSlot);
1754 printk("Clock source = %d\n", info->clockSource);
1755 printk("Framing = %d\n", my_framing);
1756 printk("Structure = %d\n", info->structure);
1757 printk("interface = %d\n", info->interface);
1758 printk("Coding = %d\n", info->coding);
1759 printk("Line build out = %d\n", info->lineBuildOut);
1760 printk("Equaliser = %d\n", info->equalizer);
1761 printk("Transparent mode = %d\n",
1762 info->transparentMode);
1763 printk("Loop mode = %d\n", info->loopMode);
1764 printk("Range = %d\n", info->range);
1765 printk("Tx Buffer mode = %d\n", info->txBufferMode);
1766 printk("Rx Buffer mode = %d\n", info->rxBufferMode);
1767 printk("LOS Threshold = %d\n", info->losThreshold);
1768 printk("Idle Code = %d\n", info->idleCode);
1769 }
1770 #endif
1771 }
1772 #if FST_DEBUG
1773 if (info->valid & FSTVAL_DEBUG) {
1774 fst_debug_mask = info->debug;
1775 }
1776 #endif
1777
1778 return err;
1779 }
1780
1781 static void
1782 gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,
1783 struct fstioc_info *info)
1784 {
1785 int i;
1786
1787 memset(info, 0, sizeof (struct fstioc_info));
1788
1789 i = port->index;
1790 info->kernelVersion = LINUX_VERSION_CODE;
1791 info->nports = card->nports;
1792 info->type = card->type;
1793 info->state = card->state;
1794 info->proto = FST_GEN_HDLC;
1795 info->index = i;
1796 #if FST_DEBUG
1797 info->debug = fst_debug_mask;
1798 #endif
1799
1800 /* Only mark information as valid if card is running.
1801 * Copy the data anyway in case it is useful for diagnostics
1802 */
1803 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)
1804 #if FST_DEBUG
1805 | FSTVAL_DEBUG
1806 #endif
1807 ;
1808
1809 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);
1810 info->internalClock = FST_RDB(card, portConfig[i].internalClock);
1811 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);
1812 info->invertClock = FST_RDB(card, portConfig[i].invertClock);
1813 info->v24IpSts = FST_RDL(card, v24IpSts[i]);
1814 info->v24OpSts = FST_RDL(card, v24OpSts[i]);
1815 info->clockStatus = FST_RDW(card, clockStatus[i]);
1816 info->cableStatus = FST_RDW(card, cableStatus);
1817 info->cardMode = FST_RDW(card, cardMode);
1818 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);
1819
1820 /*
1821 * The T2U can report cable presence for both A or B
1822 * in bits 0 and 1 of cableStatus. See which port we are and
1823 * do the mapping.
1824 */
1825 if (card->family == FST_FAMILY_TXU) {
1826 if (port->index == 0) {
1827 /*
1828 * Port A
1829 */
1830 info->cableStatus = info->cableStatus & 1;
1831 } else {
1832 /*
1833 * Port B
1834 */
1835 info->cableStatus = info->cableStatus >> 1;
1836 info->cableStatus = info->cableStatus & 1;
1837 }
1838 }
1839 /*
1840 * Some additional bits if we are TE1
1841 */
1842 if (card->type == FST_TYPE_TE1) {
1843 info->lineSpeed = FST_RDL(card, suConfig.dataRate);
1844 info->clockSource = FST_RDB(card, suConfig.clocking);
1845 info->framing = FST_RDB(card, suConfig.framing);
1846 info->structure = FST_RDB(card, suConfig.structure);
1847 info->interface = FST_RDB(card, suConfig.interface);
1848 info->coding = FST_RDB(card, suConfig.coding);
1849 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);
1850 info->equalizer = FST_RDB(card, suConfig.equalizer);
1851 info->loopMode = FST_RDB(card, suConfig.loopMode);
1852 info->range = FST_RDB(card, suConfig.range);
1853 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);
1854 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);
1855 info->startingSlot = FST_RDB(card, suConfig.startingSlot);
1856 info->losThreshold = FST_RDB(card, suConfig.losThreshold);
1857 if (FST_RDB(card, suConfig.enableIdleCode))
1858 info->idleCode = FST_RDB(card, suConfig.idleCode);
1859 else
1860 info->idleCode = 0;
1861 info->receiveBufferDelay =
1862 FST_RDL(card, suStatus.receiveBufferDelay);
1863 info->framingErrorCount =
1864 FST_RDL(card, suStatus.framingErrorCount);
1865 info->codeViolationCount =
1866 FST_RDL(card, suStatus.codeViolationCount);
1867 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);
1868 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);
1869 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);
1870 info->receiveRemoteAlarm =
1871 FST_RDB(card, suStatus.receiveRemoteAlarm);
1872 info->alarmIndicationSignal =
1873 FST_RDB(card, suStatus.alarmIndicationSignal);
1874 }
1875 }
1876
1877 static int
1878 fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,
1879 struct ifreq *ifr)
1880 {
1881 sync_serial_settings sync;
1882 int i;
1883
1884 if (ifr->ifr_settings.size != sizeof (sync)) {
1885 return -ENOMEM;
1886 }
1887
1888 if (copy_from_user
1889 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) {
1890 return -EFAULT;
1891 }
1892
1893 if (sync.loopback)
1894 return -EINVAL;
1895
1896 i = port->index;
1897
1898 switch (ifr->ifr_settings.type) {
1899 case IF_IFACE_V35:
1900 FST_WRW(card, portConfig[i].lineInterface, V35);
1901 port->hwif = V35;
1902 break;
1903
1904 case IF_IFACE_V24:
1905 FST_WRW(card, portConfig[i].lineInterface, V24);
1906 port->hwif = V24;
1907 break;
1908
1909 case IF_IFACE_X21:
1910 FST_WRW(card, portConfig[i].lineInterface, X21);
1911 port->hwif = X21;
1912 break;
1913
1914 case IF_IFACE_X21D:
1915 FST_WRW(card, portConfig[i].lineInterface, X21D);
1916 port->hwif = X21D;
1917 break;
1918
1919 case IF_IFACE_T1:
1920 FST_WRW(card, portConfig[i].lineInterface, T1);
1921 port->hwif = T1;
1922 break;
1923
1924 case IF_IFACE_E1:
1925 FST_WRW(card, portConfig[i].lineInterface, E1);
1926 port->hwif = E1;
1927 break;
1928
1929 case IF_IFACE_SYNC_SERIAL:
1930 break;
1931
1932 default:
1933 return -EINVAL;
1934 }
1935
1936 switch (sync.clock_type) {
1937 case CLOCK_EXT:
1938 FST_WRB(card, portConfig[i].internalClock, EXTCLK);
1939 break;
1940
1941 case CLOCK_INT:
1942 FST_WRB(card, portConfig[i].internalClock, INTCLK);
1943 break;
1944
1945 default:
1946 return -EINVAL;
1947 }
1948 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);
1949 return 0;
1950 }
1951
1952 static int
1953 fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,
1954 struct ifreq *ifr)
1955 {
1956 sync_serial_settings sync;
1957 int i;
1958
1959 /* First check what line type is set, we'll default to reporting X.21
1960 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1961 * changed
1962 */
1963 switch (port->hwif) {
1964 case E1:
1965 ifr->ifr_settings.type = IF_IFACE_E1;
1966 break;
1967 case T1:
1968 ifr->ifr_settings.type = IF_IFACE_T1;
1969 break;
1970 case V35:
1971 ifr->ifr_settings.type = IF_IFACE_V35;
1972 break;
1973 case V24:
1974 ifr->ifr_settings.type = IF_IFACE_V24;
1975 break;
1976 case X21D:
1977 ifr->ifr_settings.type = IF_IFACE_X21D;
1978 break;
1979 case X21:
1980 default:
1981 ifr->ifr_settings.type = IF_IFACE_X21;
1982 break;
1983 }
1984 if (ifr->ifr_settings.size == 0) {
1985 return 0; /* only type requested */
1986 }
1987 if (ifr->ifr_settings.size < sizeof (sync)) {
1988 return -ENOMEM;
1989 }
1990
1991 i = port->index;
1992 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);
1993 /* Lucky card and linux use same encoding here */
1994 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
1995 INTCLK ? CLOCK_INT : CLOCK_EXT;
1996 sync.loopback = 0;
1997
1998 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) {
1999 return -EFAULT;
2000 }
2001
2002 ifr->ifr_settings.size = sizeof (sync);
2003 return 0;
2004 }
2005
2006 static int
2007 fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2008 {
2009 struct fst_card_info *card;
2010 struct fst_port_info *port;
2011 struct fstioc_write wrthdr;
2012 struct fstioc_info info;
2013 unsigned long flags;
2014 void *buf;
2015
2016 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data);
2017
2018 port = dev_to_port(dev);
2019 card = port->card;
2020
2021 if (!capable(CAP_NET_ADMIN))
2022 return -EPERM;
2023
2024 switch (cmd) {
2025 case FSTCPURESET:
2026 fst_cpureset(card);
2027 card->state = FST_RESET;
2028 return 0;
2029
2030 case FSTCPURELEASE:
2031 fst_cpurelease(card);
2032 card->state = FST_STARTING;
2033 return 0;
2034
2035 case FSTWRITE: /* Code write (download) */
2036
2037 /* First copy in the header with the length and offset of data
2038 * to write
2039 */
2040 if (ifr->ifr_data == NULL) {
2041 return -EINVAL;
2042 }
2043 if (copy_from_user(&wrthdr, ifr->ifr_data,
2044 sizeof (struct fstioc_write))) {
2045 return -EFAULT;
2046 }
2047
2048 /* Sanity check the parameters. We don't support partial writes
2049 * when going over the top
2050 */
2051 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE
2052 || wrthdr.size + wrthdr.offset > FST_MEMSIZE) {
2053 return -ENXIO;
2054 }
2055
2056 /* Now copy the data to the card. */
2057
2058 buf = kmalloc(wrthdr.size, GFP_KERNEL);
2059 if (!buf)
2060 return -ENOMEM;
2061
2062 if (copy_from_user(buf,
2063 ifr->ifr_data + sizeof (struct fstioc_write),
2064 wrthdr.size)) {
2065 kfree(buf);
2066 return -EFAULT;
2067 }
2068
2069 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size);
2070 kfree(buf);
2071
2072 /* Writes to the memory of a card in the reset state constitute
2073 * a download
2074 */
2075 if (card->state == FST_RESET) {
2076 card->state = FST_DOWNLOAD;
2077 }
2078 return 0;
2079
2080 case FSTGETCONF:
2081
2082 /* If card has just been started check the shared memory config
2083 * version and marker
2084 */
2085 if (card->state == FST_STARTING) {
2086 check_started_ok(card);
2087
2088 /* If everything checked out enable card interrupts */
2089 if (card->state == FST_RUNNING) {
2090 spin_lock_irqsave(&card->card_lock, flags);
2091 fst_enable_intr(card);
2092 FST_WRB(card, interruptHandshake, 0xEE);
2093 spin_unlock_irqrestore(&card->card_lock, flags);
2094 }
2095 }
2096
2097 if (ifr->ifr_data == NULL) {
2098 return -EINVAL;
2099 }
2100
2101 gather_conf_info(card, port, &info);
2102
2103 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) {
2104 return -EFAULT;
2105 }
2106 return 0;
2107
2108 case FSTSETCONF:
2109
2110 /*
2111 * Most of the settings have been moved to the generic ioctls
2112 * this just covers debug and board ident now
2113 */
2114
2115 if (card->state != FST_RUNNING) {
2116 printk_err
2117 ("Attempt to configure card %d in non-running state (%d)\n",
2118 card->card_no, card->state);
2119 return -EIO;
2120 }
2121 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) {
2122 return -EFAULT;
2123 }
2124
2125 return set_conf_from_info(card, port, &info);
2126
2127 case SIOCWANDEV:
2128 switch (ifr->ifr_settings.type) {
2129 case IF_GET_IFACE:
2130 return fst_get_iface(card, port, ifr);
2131
2132 case IF_IFACE_SYNC_SERIAL:
2133 case IF_IFACE_V35:
2134 case IF_IFACE_V24:
2135 case IF_IFACE_X21:
2136 case IF_IFACE_X21D:
2137 case IF_IFACE_T1:
2138 case IF_IFACE_E1:
2139 return fst_set_iface(card, port, ifr);
2140
2141 case IF_PROTO_RAW:
2142 port->mode = FST_RAW;
2143 return 0;
2144
2145 case IF_GET_PROTO:
2146 if (port->mode == FST_RAW) {
2147 ifr->ifr_settings.type = IF_PROTO_RAW;
2148 return 0;
2149 }
2150 return hdlc_ioctl(dev, ifr, cmd);
2151
2152 default:
2153 port->mode = FST_GEN_HDLC;
2154 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",
2155 ifr->ifr_settings.type);
2156 return hdlc_ioctl(dev, ifr, cmd);
2157 }
2158
2159 default:
2160 /* Not one of ours. Pass through to HDLC package */
2161 return hdlc_ioctl(dev, ifr, cmd);
2162 }
2163 }
2164
2165 static void
2166 fst_openport(struct fst_port_info *port)
2167 {
2168 int signals;
2169 int txq_length;
2170
2171 /* Only init things if card is actually running. This allows open to
2172 * succeed for downloads etc.
2173 */
2174 if (port->card->state == FST_RUNNING) {
2175 if (port->run) {
2176 dbg(DBG_OPEN, "open: found port already running\n");
2177
2178 fst_issue_cmd(port, STOPPORT);
2179 port->run = 0;
2180 }
2181
2182 fst_rx_config(port);
2183 fst_tx_config(port);
2184 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);
2185
2186 fst_issue_cmd(port, STARTPORT);
2187 port->run = 1;
2188
2189 signals = FST_RDL(port->card, v24DebouncedSts[port->index]);
2190 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
2191 ? IPSTS_INDICATE : IPSTS_DCD))
2192 netif_carrier_on(port_to_dev(port));
2193 else
2194 netif_carrier_off(port_to_dev(port));
2195
2196 txq_length = port->txqe - port->txqs;
2197 port->txqe = 0;
2198 port->txqs = 0;
2199 }
2200
2201 }
2202
2203 static void
2204 fst_closeport(struct fst_port_info *port)
2205 {
2206 if (port->card->state == FST_RUNNING) {
2207 if (port->run) {
2208 port->run = 0;
2209 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);
2210
2211 fst_issue_cmd(port, STOPPORT);
2212 } else {
2213 dbg(DBG_OPEN, "close: port not running\n");
2214 }
2215 }
2216 }
2217
2218 static int
2219 fst_open(struct net_device *dev)
2220 {
2221 int err;
2222 struct fst_port_info *port;
2223
2224 port = dev_to_port(dev);
2225 if (!try_module_get(THIS_MODULE))
2226 return -EBUSY;
2227
2228 if (port->mode != FST_RAW) {
2229 err = hdlc_open(dev);
2230 if (err)
2231 return err;
2232 }
2233
2234 fst_openport(port);
2235 netif_wake_queue(dev);
2236 return 0;
2237 }
2238
2239 static int
2240 fst_close(struct net_device *dev)
2241 {
2242 struct fst_port_info *port;
2243 struct fst_card_info *card;
2244 unsigned char tx_dma_done;
2245 unsigned char rx_dma_done;
2246
2247 port = dev_to_port(dev);
2248 card = port->card;
2249
2250 tx_dma_done = inb(card->pci_conf + DMACSR1);
2251 rx_dma_done = inb(card->pci_conf + DMACSR0);
2252 dbg(DBG_OPEN,
2253 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2254 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,
2255 rx_dma_done);
2256
2257 netif_stop_queue(dev);
2258 fst_closeport(dev_to_port(dev));
2259 if (port->mode != FST_RAW) {
2260 hdlc_close(dev);
2261 }
2262 module_put(THIS_MODULE);
2263 return 0;
2264 }
2265
2266 static int
2267 fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity)
2268 {
2269 /*
2270 * Setting currently fixed in FarSync card so we check and forget
2271 */
2272 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)
2273 return -EINVAL;
2274 return 0;
2275 }
2276
2277 static void
2278 fst_tx_timeout(struct net_device *dev)
2279 {
2280 struct fst_port_info *port;
2281 struct fst_card_info *card;
2282
2283 port = dev_to_port(dev);
2284 card = port->card;
2285 dev->stats.tx_errors++;
2286 dev->stats.tx_aborted_errors++;
2287 dbg(DBG_ASS, "Tx timeout card %d port %d\n",
2288 card->card_no, port->index);
2289 fst_issue_cmd(port, ABORTTX);
2290
2291 dev->trans_start = jiffies;
2292 netif_wake_queue(dev);
2293 port->start = 0;
2294 }
2295
2296 static int
2297 fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2298 {
2299 struct fst_card_info *card;
2300 struct fst_port_info *port;
2301 unsigned long flags;
2302 int txq_length;
2303
2304 port = dev_to_port(dev);
2305 card = port->card;
2306 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);
2307
2308 /* Drop packet with error if we don't have carrier */
2309 if (!netif_carrier_ok(dev)) {
2310 dev_kfree_skb(skb);
2311 dev->stats.tx_errors++;
2312 dev->stats.tx_carrier_errors++;
2313 dbg(DBG_ASS,
2314 "Tried to transmit but no carrier on card %d port %d\n",
2315 card->card_no, port->index);
2316 return 0;
2317 }
2318
2319 /* Drop it if it's too big! MTU failure ? */
2320 if (skb->len > LEN_TX_BUFFER) {
2321 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
2322 LEN_TX_BUFFER);
2323 dev_kfree_skb(skb);
2324 dev->stats.tx_errors++;
2325 return 0;
2326 }
2327
2328 /*
2329 * We are always going to queue the packet
2330 * so that the bottom half is the only place we tx from
2331 * Check there is room in the port txq
2332 */
2333 spin_lock_irqsave(&card->card_lock, flags);
2334 if ((txq_length = port->txqe - port->txqs) < 0) {
2335 /*
2336 * This is the case where the next free has wrapped but the
2337 * last used hasn't
2338 */
2339 txq_length = txq_length + FST_TXQ_DEPTH;
2340 }
2341 spin_unlock_irqrestore(&card->card_lock, flags);
2342 if (txq_length > fst_txq_high) {
2343 /*
2344 * We have got enough buffers in the pipeline. Ask the network
2345 * layer to stop sending frames down
2346 */
2347 netif_stop_queue(dev);
2348 port->start = 1; /* I'm using this to signal stop sent up */
2349 }
2350
2351 if (txq_length == FST_TXQ_DEPTH - 1) {
2352 /*
2353 * This shouldn't have happened but such is life
2354 */
2355 dev_kfree_skb(skb);
2356 dev->stats.tx_errors++;
2357 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
2358 card->card_no, port->index);
2359 return 0;
2360 }
2361
2362 /*
2363 * queue the buffer
2364 */
2365 spin_lock_irqsave(&card->card_lock, flags);
2366 port->txq[port->txqe] = skb;
2367 port->txqe++;
2368 if (port->txqe == FST_TXQ_DEPTH)
2369 port->txqe = 0;
2370 spin_unlock_irqrestore(&card->card_lock, flags);
2371
2372 /* Scehdule the bottom half which now does transmit processing */
2373 fst_q_work_item(&fst_work_txq, card->card_no);
2374 tasklet_schedule(&fst_tx_task);
2375
2376 return 0;
2377 }
2378
2379 /*
2380 * Card setup having checked hardware resources.
2381 * Should be pretty bizarre if we get an error here (kernel memory
2382 * exhaustion is one possibility). If we do see a problem we report it
2383 * via a printk and leave the corresponding interface and all that follow
2384 * disabled.
2385 */
2386 static char *type_strings[] __devinitdata = {
2387 "no hardware", /* Should never be seen */
2388 "FarSync T2P",
2389 "FarSync T4P",
2390 "FarSync T1U",
2391 "FarSync T2U",
2392 "FarSync T4U",
2393 "FarSync TE1"
2394 };
2395
2396 static void __devinit
2397 fst_init_card(struct fst_card_info *card)
2398 {
2399 int i;
2400 int err;
2401
2402 /* We're working on a number of ports based on the card ID. If the
2403 * firmware detects something different later (should never happen)
2404 * we'll have to revise it in some way then.
2405 */
2406 for (i = 0; i < card->nports; i++) {
2407 err = register_hdlc_device(card->ports[i].dev);
2408 if (err < 0) {
2409 int j;
2410 printk_err ("Cannot register HDLC device for port %d"
2411 " (errno %d)\n", i, -err );
2412 for (j = i; j < card->nports; j++) {
2413 free_netdev(card->ports[j].dev);
2414 card->ports[j].dev = NULL;
2415 }
2416 card->nports = i;
2417 break;
2418 }
2419 }
2420
2421 printk_info("%s-%s: %s IRQ%d, %d ports\n",
2422 port_to_dev(&card->ports[0])->name,
2423 port_to_dev(&card->ports[card->nports - 1])->name,
2424 type_strings[card->type], card->irq, card->nports);
2425 }
2426
2427 /*
2428 * Initialise card when detected.
2429 * Returns 0 to indicate success, or errno otherwise.
2430 */
2431 static int __devinit
2432 fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2433 {
2434 static int firsttime_done = 0;
2435 static int no_of_cards_added = 0;
2436 struct fst_card_info *card;
2437 int err = 0;
2438 int i;
2439
2440 if (!firsttime_done) {
2441 printk_info("FarSync WAN driver " FST_USER_VERSION
2442 " (c) 2001-2004 FarSite Communications Ltd.\n");
2443 firsttime_done = 1;
2444 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);
2445 }
2446
2447 /*
2448 * We are going to be clever and allow certain cards not to be
2449 * configured. An exclude list can be provided in /etc/modules.conf
2450 */
2451 if (fst_excluded_cards != 0) {
2452 /*
2453 * There are cards to exclude
2454 *
2455 */
2456 for (i = 0; i < fst_excluded_cards; i++) {
2457 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) {
2458 printk_info("FarSync PCI device %d not assigned\n",
2459 (pdev->devfn) >> 3);
2460 return -EBUSY;
2461 }
2462 }
2463 }
2464
2465 /* Allocate driver private data */
2466 card = kzalloc(sizeof (struct fst_card_info), GFP_KERNEL);
2467 if (card == NULL) {
2468 printk_err("FarSync card found but insufficient memory for"
2469 " driver storage\n");
2470 return -ENOMEM;
2471 }
2472
2473 /* Try to enable the device */
2474 if ((err = pci_enable_device(pdev)) != 0) {
2475 printk_err("Failed to enable card. Err %d\n", -err);
2476 kfree(card);
2477 return err;
2478 }
2479
2480 if ((err = pci_request_regions(pdev, "FarSync")) !=0) {
2481 printk_err("Failed to allocate regions. Err %d\n", -err);
2482 pci_disable_device(pdev);
2483 kfree(card);
2484 return err;
2485 }
2486
2487 /* Get virtual addresses of memory regions */
2488 card->pci_conf = pci_resource_start(pdev, 1);
2489 card->phys_mem = pci_resource_start(pdev, 2);
2490 card->phys_ctlmem = pci_resource_start(pdev, 3);
2491 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) {
2492 printk_err("Physical memory remap failed\n");
2493 pci_release_regions(pdev);
2494 pci_disable_device(pdev);
2495 kfree(card);
2496 return -ENODEV;
2497 }
2498 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) {
2499 printk_err("Control memory remap failed\n");
2500 pci_release_regions(pdev);
2501 pci_disable_device(pdev);
2502 kfree(card);
2503 return -ENODEV;
2504 }
2505 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);
2506
2507 /* Register the interrupt handler */
2508 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) {
2509 printk_err("Unable to register interrupt %d\n", card->irq);
2510 pci_release_regions(pdev);
2511 pci_disable_device(pdev);
2512 iounmap(card->ctlmem);
2513 iounmap(card->mem);
2514 kfree(card);
2515 return -ENODEV;
2516 }
2517
2518 /* Record info we need */
2519 card->irq = pdev->irq;
2520 card->type = ent->driver_data;
2521 card->family = ((ent->driver_data == FST_TYPE_T2P) ||
2522 (ent->driver_data == FST_TYPE_T4P))
2523 ? FST_FAMILY_TXP : FST_FAMILY_TXU;
2524 if ((ent->driver_data == FST_TYPE_T1U) ||
2525 (ent->driver_data == FST_TYPE_TE1))
2526 card->nports = 1;
2527 else
2528 card->nports = ((ent->driver_data == FST_TYPE_T2P) ||
2529 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;
2530
2531 card->state = FST_UNINIT;
2532 spin_lock_init ( &card->card_lock );
2533
2534 for ( i = 0 ; i < card->nports ; i++ ) {
2535 struct net_device *dev = alloc_hdlcdev(&card->ports[i]);
2536 hdlc_device *hdlc;
2537 if (!dev) {
2538 while (i--)
2539 free_netdev(card->ports[i].dev);
2540 printk_err ("FarSync: out of memory\n");
2541 free_irq(card->irq, card);
2542 pci_release_regions(pdev);
2543 pci_disable_device(pdev);
2544 iounmap(card->ctlmem);
2545 iounmap(card->mem);
2546 kfree(card);
2547 return -ENODEV;
2548 }
2549 card->ports[i].dev = dev;
2550 card->ports[i].card = card;
2551 card->ports[i].index = i;
2552 card->ports[i].run = 0;
2553
2554 hdlc = dev_to_hdlc(dev);
2555
2556 /* Fill in the net device info */
2557 /* Since this is a PCI setup this is purely
2558 * informational. Give them the buffer addresses
2559 * and basic card I/O.
2560 */
2561 dev->mem_start = card->phys_mem
2562 + BUF_OFFSET ( txBuffer[i][0][0]);
2563 dev->mem_end = card->phys_mem
2564 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]);
2565 dev->base_addr = card->pci_conf;
2566 dev->irq = card->irq;
2567
2568 dev->tx_queue_len = FST_TX_QUEUE_LEN;
2569 dev->open = fst_open;
2570 dev->stop = fst_close;
2571 dev->do_ioctl = fst_ioctl;
2572 dev->watchdog_timeo = FST_TX_TIMEOUT;
2573 dev->tx_timeout = fst_tx_timeout;
2574 hdlc->attach = fst_attach;
2575 hdlc->xmit = fst_start_xmit;
2576 }
2577
2578 card->device = pdev;
2579
2580 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,
2581 card->nports, card->irq);
2582 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",
2583 card->pci_conf, card->phys_mem, card->phys_ctlmem);
2584
2585 /* Reset the card's processor */
2586 fst_cpureset(card);
2587 card->state = FST_RESET;
2588
2589 /* Initialise DMA (if required) */
2590 fst_init_dma(card);
2591
2592 /* Record driver data for later use */
2593 pci_set_drvdata(pdev, card);
2594
2595 /* Remainder of card setup */
2596 fst_card_array[no_of_cards_added] = card;
2597 card->card_no = no_of_cards_added++; /* Record instance and bump it */
2598 fst_init_card(card);
2599 if (card->family == FST_FAMILY_TXU) {
2600 /*
2601 * Allocate a dma buffer for transmit and receives
2602 */
2603 card->rx_dma_handle_host =
2604 pci_alloc_consistent(card->device, FST_MAX_MTU,
2605 &card->rx_dma_handle_card);
2606 if (card->rx_dma_handle_host == NULL) {
2607 printk_err("Could not allocate rx dma buffer\n");
2608 fst_disable_intr(card);
2609 pci_release_regions(pdev);
2610 pci_disable_device(pdev);
2611 iounmap(card->ctlmem);
2612 iounmap(card->mem);
2613 kfree(card);
2614 return -ENOMEM;
2615 }
2616 card->tx_dma_handle_host =
2617 pci_alloc_consistent(card->device, FST_MAX_MTU,
2618 &card->tx_dma_handle_card);
2619 if (card->tx_dma_handle_host == NULL) {
2620 printk_err("Could not allocate tx dma buffer\n");
2621 fst_disable_intr(card);
2622 pci_release_regions(pdev);
2623 pci_disable_device(pdev);
2624 iounmap(card->ctlmem);
2625 iounmap(card->mem);
2626 kfree(card);
2627 return -ENOMEM;
2628 }
2629 }
2630 return 0; /* Success */
2631 }
2632
2633 /*
2634 * Cleanup and close down a card
2635 */
2636 static void __devexit
2637 fst_remove_one(struct pci_dev *pdev)
2638 {
2639 struct fst_card_info *card;
2640 int i;
2641
2642 card = pci_get_drvdata(pdev);
2643
2644 for (i = 0; i < card->nports; i++) {
2645 struct net_device *dev = port_to_dev(&card->ports[i]);
2646 unregister_hdlc_device(dev);
2647 }
2648
2649 fst_disable_intr(card);
2650 free_irq(card->irq, card);
2651
2652 iounmap(card->ctlmem);
2653 iounmap(card->mem);
2654 pci_release_regions(pdev);
2655 if (card->family == FST_FAMILY_TXU) {
2656 /*
2657 * Free dma buffers
2658 */
2659 pci_free_consistent(card->device, FST_MAX_MTU,
2660 card->rx_dma_handle_host,
2661 card->rx_dma_handle_card);
2662 pci_free_consistent(card->device, FST_MAX_MTU,
2663 card->tx_dma_handle_host,
2664 card->tx_dma_handle_card);
2665 }
2666 fst_card_array[card->card_no] = NULL;
2667 }
2668
2669 static struct pci_driver fst_driver = {
2670 .name = FST_NAME,
2671 .id_table = fst_pci_dev_id,
2672 .probe = fst_add_one,
2673 .remove = __devexit_p(fst_remove_one),
2674 .suspend = NULL,
2675 .resume = NULL,
2676 };
2677
2678 static int __init
2679 fst_init(void)
2680 {
2681 int i;
2682
2683 for (i = 0; i < FST_MAX_CARDS; i++)
2684 fst_card_array[i] = NULL;
2685 spin_lock_init(&fst_work_q_lock);
2686 return pci_register_driver(&fst_driver);
2687 }
2688
2689 static void __exit
2690 fst_cleanup_module(void)
2691 {
2692 printk_info("FarSync WAN driver unloading\n");
2693 pci_unregister_driver(&fst_driver);
2694 }
2695
2696 module_init(fst_init);
2697 module_exit(fst_cleanup_module);
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK