?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / net / tokenring / 3c359.c
blob43853e3b210e42977100f1c1b3828a3dfa9fe623
1 /*
2 * 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
3 *
4 * Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC
5 *
6 * Base Driver Olympic:
7 * Written 1999 Peter De Schrijver & Mike Phillips
8 *
9 * This software may be used and distributed according to the terms
10 * of the GNU General Public License, incorporated herein by reference.
11 *
12 * 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world.
13 *
14 * 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel.
15 * 3/05/01 - Last clean up stuff before submission.
16 * 2/15/01 - Finally, update to new pci api.
17 *
18 * To Do:
19 */
20
21 /*
22 * Technical Card Details
23 *
24 * All access to data is done with 16/8 bit transfers. The transfer
25 * method really sucks. You can only read or write one location at a time.
26 *
27 * Also, the microcode for the card must be uploaded if the card does not have
28 * the flashrom on board. This is a 28K bloat in the driver when compiled
29 * as a module.
30 *
31 * Rx is very simple, status into a ring of descriptors, dma data transfer,
32 * interrupts to tell us when a packet is received.
33 *
34 * Tx is a little more interesting. Similar scenario, descriptor and dma data
35 * transfers, but we don't have to interrupt the card to tell it another packet
36 * is ready for transmission, we are just doing simple memory writes, not io or mmio
37 * writes. The card can be set up to simply poll on the next
38 * descriptor pointer and when this value is non-zero will automatically download
39 * the next packet. The card then interrupts us when the packet is done.
40 *
41 */
42
43 #define XL_DEBUG 0
44
45 #include <linux/jiffies.h>
46 #include <linux/module.h>
47 #include <linux/kernel.h>
48 #include <linux/errno.h>
49 #include <linux/timer.h>
50 #include <linux/in.h>
51 #include <linux/ioport.h>
52 #include <linux/string.h>
53 #include <linux/proc_fs.h>
54 #include <linux/ptrace.h>
55 #include <linux/skbuff.h>
56 #include <linux/interrupt.h>
57 #include <linux/delay.h>
58 #include <linux/netdevice.h>
59 #include <linux/trdevice.h>
60 #include <linux/stddef.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/spinlock.h>
64 #include <linux/bitops.h>
65
66 #include <net/checksum.h>
67
68 #include <asm/io.h>
69 #include <asm/system.h>
70
71 #include "3c359.h"
72
73 static char version[] __devinitdata =
74 "3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ;
75
76 MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ;
77 MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver \n") ;
78
79 /* Module paramters */
80
81 /* Ring Speed 0,4,16
82 * 0 = Autosense
83 * 4,16 = Selected speed only, no autosense
84 * This allows the card to be the first on the ring
85 * and become the active monitor.
86 *
87 * WARNING: Some hubs will allow you to insert
88 * at the wrong speed.
89 *
90 * The adapter will _not_ fail to open if there are no
91 * active monitors on the ring, it will simply open up in
92 * its last known ringspeed if no ringspeed is specified.
93 */
94
95 static int ringspeed[XL_MAX_ADAPTERS] = {0,} ;
96
97 module_param_array(ringspeed, int, NULL, 0);
98 MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ;
99
100 /* Packet buffer size */
101
102 static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ;
103
104 module_param_array(pkt_buf_sz, int, NULL, 0) ;
105 MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ;
106 /* Message Level */
107
108 static int message_level[XL_MAX_ADAPTERS] = {0,} ;
109
110 module_param_array(message_level, int, NULL, 0) ;
111 MODULE_PARM_DESC(message_level, "3c359: Level of reported messages") ;
112 /*
113 * This is a real nasty way of doing this, but otherwise you
114 * will be stuck with 1555 lines of hex #'s in the code.
115 */
116
117 #include "3c359_microcode.h"
118
119 static struct pci_device_id xl_pci_tbl[] =
120 {
121 {PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, },
122 { } /* terminate list */
123 };
124 MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ;
125
126 static int xl_init(struct net_device *dev);
127 static int xl_open(struct net_device *dev);
128 static int xl_open_hw(struct net_device *dev) ;
129 static int xl_hw_reset(struct net_device *dev);
130 static int xl_xmit(struct sk_buff *skb, struct net_device *dev);
131 static void xl_dn_comp(struct net_device *dev);
132 static int xl_close(struct net_device *dev);
133 static void xl_set_rx_mode(struct net_device *dev);
134 static irqreturn_t xl_interrupt(int irq, void *dev_id);
135 static int xl_set_mac_address(struct net_device *dev, void *addr) ;
136 static void xl_arb_cmd(struct net_device *dev);
137 static void xl_asb_cmd(struct net_device *dev) ;
138 static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ;
139 static void xl_wait_misr_flags(struct net_device *dev) ;
140 static int xl_change_mtu(struct net_device *dev, int mtu);
141 static void xl_srb_bh(struct net_device *dev) ;
142 static void xl_asb_bh(struct net_device *dev) ;
143 static void xl_reset(struct net_device *dev) ;
144 static void xl_freemem(struct net_device *dev) ;
145
146
147 /* EEProm Access Functions */
148 static u16 xl_ee_read(struct net_device *dev, int ee_addr) ;
149 static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ;
150
151 /* Debugging functions */
152 #if XL_DEBUG
153 static void print_tx_state(struct net_device *dev) ;
154 static void print_rx_state(struct net_device *dev) ;
155
156 static void print_tx_state(struct net_device *dev)
157 {
158
159 struct xl_private *xl_priv = netdev_priv(dev);
160 struct xl_tx_desc *txd ;
161 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
162 int i ;
163
164 printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d \n",xl_priv->tx_ring_head,
165 xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ;
166 printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len \n");
167 for (i = 0; i < 16; i++) {
168 txd = &(xl_priv->xl_tx_ring[i]) ;
169 printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(txd),
170 txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ;
171 }
172
173 printk("DNLISTPTR = %04x \n", readl(xl_mmio + MMIO_DNLISTPTR) );
174
175 printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
176 printk("Queue status = %0x \n",netif_running(dev) ) ;
177 }
178
179 static void print_rx_state(struct net_device *dev)
180 {
181
182 struct xl_private *xl_priv = netdev_priv(dev);
183 struct xl_rx_desc *rxd ;
184 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
185 int i ;
186
187 printk("rx_ring_tail: %d \n", xl_priv->rx_ring_tail) ;
188 printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len \n");
189 for (i = 0; i < 16; i++) {
190 /* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */
191 rxd = &(xl_priv->xl_rx_ring[i]) ;
192 printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(rxd),
193 rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ;
194 }
195
196 printk("UPLISTPTR = %04x \n", readl(xl_mmio + MMIO_UPLISTPTR) );
197
198 printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
199 printk("Queue status = %0x \n",netif_running(dev) ) ;
200 }
201 #endif
202
203 /*
204 * Read values from the on-board EEProm. This looks very strange
205 * but you have to wait for the EEProm to get/set the value before
206 * passing/getting the next value from the nic. As with all requests
207 * on this nic it has to be done in two stages, a) tell the nic which
208 * memory address you want to access and b) pass/get the value from the nic.
209 * With the EEProm, you have to wait before and inbetween access a) and b).
210 * As this is only read at initialization time and the wait period is very
211 * small we shouldn't have to worry about scheduling issues.
212 */
213
214 static u16 xl_ee_read(struct net_device *dev, int ee_addr)
215 {
216 struct xl_private *xl_priv = netdev_priv(dev);
217 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
218
219 /* Wait for EEProm to not be busy */
220 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
221 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
222
223 /* Tell EEProm what we want to do and where */
224 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
225 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
226
227 /* Wait for EEProm to not be busy */
228 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
229 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
230
231 /* Tell EEProm what we want to do and where */
232 writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
233 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
234
235 /* Finally read the value from the EEProm */
236 writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
237 return readw(xl_mmio + MMIO_MACDATA) ;
238 }
239
240 /*
241 * Write values to the onboard eeprom. As with eeprom read you need to
242 * set which location to write, wait, value to write, wait, with the
243 * added twist of having to enable eeprom writes as well.
244 */
245
246 static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value)
247 {
248 struct xl_private *xl_priv = netdev_priv(dev);
249 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
250
251 /* Wait for EEProm to not be busy */
252 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
253 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
254
255 /* Enable write/erase */
256 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
257 writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ;
258
259 /* Wait for EEProm to not be busy */
260 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
261 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
262
263 /* Put the value we want to write into EEDATA */
264 writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
265 writew(ee_value, xl_mmio + MMIO_MACDATA) ;
266
267 /* Tell EEProm to write eevalue into ee_addr */
268 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
269 writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ;
270
271 /* Wait for EEProm to not be busy, to ensure write gets done */
272 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
273 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
274
275 return ;
276 }
277
278 static int __devinit xl_probe(struct pci_dev *pdev,
279 const struct pci_device_id *ent)
280 {
281 struct net_device *dev ;
282 struct xl_private *xl_priv ;
283 static int card_no = -1 ;
284 int i ;
285
286 card_no++ ;
287
288 if (pci_enable_device(pdev)) {
289 return -ENODEV ;
290 }
291
292 pci_set_master(pdev);
293
294 if ((i = pci_request_regions(pdev,"3c359"))) {
295 return i ;
296 } ;
297
298 /*
299 * Allowing init_trdev to allocate the private data will align
300 * xl_private on a 32 bytes boundary which we need for the rx/tx
301 * descriptors
302 */
303
304 dev = alloc_trdev(sizeof(struct xl_private)) ;
305 if (!dev) {
306 pci_release_regions(pdev) ;
307 return -ENOMEM ;
308 }
309 xl_priv = netdev_priv(dev);
310
311 #if XL_DEBUG
312 printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n",
313 pdev, dev, netdev_priv(dev), (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start);
314 #endif
315
316 dev->irq=pdev->irq;
317 dev->base_addr=pci_resource_start(pdev,0) ;
318 xl_priv->xl_card_name = pci_name(pdev);
319 xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE);
320 xl_priv->pdev = pdev ;
321
322 if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) )
323 xl_priv->pkt_buf_sz = PKT_BUF_SZ ;
324 else
325 xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ;
326
327 dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ;
328 xl_priv->xl_ring_speed = ringspeed[card_no] ;
329 xl_priv->xl_message_level = message_level[card_no] ;
330 xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ;
331 xl_priv->xl_copy_all_options = 0 ;
332
333 if((i = xl_init(dev))) {
334 iounmap(xl_priv->xl_mmio) ;
335 free_netdev(dev) ;
336 pci_release_regions(pdev) ;
337 return i ;
338 }
339
340 dev->open=&xl_open;
341 dev->hard_start_xmit=&xl_xmit;
342 dev->change_mtu=&xl_change_mtu;
343 dev->stop=&xl_close;
344 dev->do_ioctl=NULL;
345 dev->set_multicast_list=&xl_set_rx_mode;
346 dev->set_mac_address=&xl_set_mac_address ;
347 SET_NETDEV_DEV(dev, &pdev->dev);
348
349 pci_set_drvdata(pdev,dev) ;
350 if ((i = register_netdev(dev))) {
351 printk(KERN_ERR "3C359, register netdev failed\n") ;
352 pci_set_drvdata(pdev,NULL) ;
353 iounmap(xl_priv->xl_mmio) ;
354 free_netdev(dev) ;
355 pci_release_regions(pdev) ;
356 return i ;
357 }
358
359 printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ;
360
361 return 0;
362 }
363
364
365 static int __devinit xl_init(struct net_device *dev)
366 {
367 struct xl_private *xl_priv = netdev_priv(dev);
368
369 printk(KERN_INFO "%s \n", version);
370 printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n",
371 xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq);
372
373 spin_lock_init(&xl_priv->xl_lock) ;
374
375 return xl_hw_reset(dev) ;
376
377 }
378
379
380 /*
381 * Hardware reset. This needs to be a separate entity as we need to reset the card
382 * when we change the EEProm settings.
383 */
384
385 static int xl_hw_reset(struct net_device *dev)
386 {
387 struct xl_private *xl_priv = netdev_priv(dev);
388 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
389 unsigned long t ;
390 u16 i ;
391 u16 result_16 ;
392 u8 result_8 ;
393 u16 start ;
394 int j ;
395
396 /*
397 * Reset the card. If the card has got the microcode on board, we have
398 * missed the initialization interrupt, so we must always do this.
399 */
400
401 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
402
403 /*
404 * Must wait for cmdInProgress bit (12) to clear before continuing with
405 * card configuration.
406 */
407
408 t=jiffies;
409 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
410 schedule();
411 if (time_after(jiffies, t + 40 * HZ)) {
412 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name);
413 return -ENODEV;
414 }
415 }
416
417 /*
418 * Enable pmbar by setting bit in CPAttention
419 */
420
421 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
422 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
423 result_8 = result_8 | CPA_PMBARVIS ;
424 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
425 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
426
427 /*
428 * Read cpHold bit in pmbar, if cleared we have got Flashrom on board.
429 * If not, we need to upload the microcode to the card
430 */
431
432 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
433
434 #if XL_DEBUG
435 printk(KERN_INFO "Read from PMBAR = %04x \n", readw(xl_mmio + MMIO_MACDATA)) ;
436 #endif
437
438 if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) {
439
440 /* Set PmBar, privateMemoryBase bits (8:2) to 0 */
441
442 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
443 result_16 = readw(xl_mmio + MMIO_MACDATA) ;
444 result_16 = result_16 & ~((0x7F) << 2) ;
445 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
446 writew(result_16,xl_mmio + MMIO_MACDATA) ;
447
448 /* Set CPAttention, memWrEn bit */
449
450 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
451 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
452 result_8 = result_8 | CPA_MEMWREN ;
453 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
454 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
455
456 /*
457 * Now to write the microcode into the shared ram
458 * The microcode must finish at position 0xFFFF, so we must subtract
459 * to get the start position for the code
460 */
461
462 start = (0xFFFF - (mc_size) + 1 ) ; /* Looks strange but ensures compiler only uses 16 bit unsigned int for this */
463
464 printk(KERN_INFO "3C359: Uploading Microcode: ");
465
466 for (i = start, j = 0; j < mc_size; i++, j++) {
467 writel(MEM_BYTE_WRITE | 0XD0000 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
468 writeb(microcode[j],xl_mmio + MMIO_MACDATA) ;
469 if (j % 1024 == 0)
470 printk(".");
471 }
472 printk("\n") ;
473
474 for (i=0;i < 16; i++) {
475 writel( (MEM_BYTE_WRITE | 0xDFFF0) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
476 writeb(microcode[mc_size - 16 + i], xl_mmio + MMIO_MACDATA) ;
477 }
478
479 /*
480 * Have to write the start address of the upload to FFF4, but
481 * the address must be >> 4. You do not want to know how long
482 * it took me to discover this.
483 */
484
485 writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
486 writew(start >> 4, xl_mmio + MMIO_MACDATA);
487
488 /* Clear the CPAttention, memWrEn Bit */
489
490 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
491 result_8 = readb(xl_mmio + MMIO_MACDATA) ;
492 result_8 = result_8 & ~CPA_MEMWREN ;
493 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
494 writeb(result_8, xl_mmio + MMIO_MACDATA) ;
495
496 /* Clear the cpHold bit in pmbar */
497
498 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
499 result_16 = readw(xl_mmio + MMIO_MACDATA) ;
500 result_16 = result_16 & ~PMB_CPHOLD ;
501 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
502 writew(result_16,xl_mmio + MMIO_MACDATA) ;
503
504
505 } /* If microcode upload required */
506
507 /*
508 * The card should now go though a self test procedure and get itself ready
509 * to be opened, we must wait for an srb response with the initialization
510 * information.
511 */
512
513 #if XL_DEBUG
514 printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name);
515 #endif
516
517 writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ;
518
519 t=jiffies;
520 while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) {
521 schedule();
522 if (time_after(jiffies, t + 15 * HZ)) {
523 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
524 return -ENODEV;
525 }
526 }
527
528 /*
529 * Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh,
530 * DnPriReqThresh, read the tech docs if you want to know what
531 * values they need to be.
532 */
533
534 writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
535 writew(0xD000, xl_mmio + MMIO_MACDATA) ;
536
537 writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
538 writew(0X0020, xl_mmio + MMIO_MACDATA) ;
539
540 writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ;
541
542 writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ;
543 writeb(0x04, xl_mmio + DNPRIREQTHRESH) ;
544
545 /*
546 * Read WRBR to provide the location of the srb block, have to use byte reads not word reads.
547 * Tech docs have this wrong !!!!
548 */
549
550 writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
551 xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ;
552 writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
553 xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ;
554
555 #if XL_DEBUG
556 writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
557 if ( readw(xl_mmio + MMIO_MACDATA) & 2) {
558 printk(KERN_INFO "Default ring speed 4 mbps \n") ;
559 } else {
560 printk(KERN_INFO "Default ring speed 16 mbps \n") ;
561 }
562 printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb);
563 #endif
564
565 return 0;
566 }
567
568 static int xl_open(struct net_device *dev)
569 {
570 struct xl_private *xl_priv=netdev_priv(dev);
571 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
572 u8 i ;
573 __le16 hwaddr[3] ; /* Should be u8[6] but we get word return values */
574 int open_err ;
575
576 u16 switchsettings, switchsettings_eeprom ;
577
578 if(request_irq(dev->irq, &xl_interrupt, IRQF_SHARED , "3c359", dev)) {
579 return -EAGAIN;
580 }
581
582 /*
583 * Read the information from the EEPROM that we need.
584 */
585
586 hwaddr[0] = cpu_to_le16(xl_ee_read(dev,0x10));
587 hwaddr[1] = cpu_to_le16(xl_ee_read(dev,0x11));
588 hwaddr[2] = cpu_to_le16(xl_ee_read(dev,0x12));
589
590 /* Ring speed */
591
592 switchsettings_eeprom = xl_ee_read(dev,0x08) ;
593 switchsettings = switchsettings_eeprom ;
594
595 if (xl_priv->xl_ring_speed != 0) {
596 if (xl_priv->xl_ring_speed == 4)
597 switchsettings = switchsettings | 0x02 ;
598 else
599 switchsettings = switchsettings & ~0x02 ;
600 }
601
602 /* Only write EEProm if there has been a change */
603 if (switchsettings != switchsettings_eeprom) {
604 xl_ee_write(dev,0x08,switchsettings) ;
605 /* Hardware reset after changing EEProm */
606 xl_hw_reset(dev) ;
607 }
608
609 memcpy(dev->dev_addr,hwaddr,dev->addr_len) ;
610
611 open_err = xl_open_hw(dev) ;
612
613 /*
614 * This really needs to be cleaned up with better error reporting.
615 */
616
617 if (open_err != 0) { /* Something went wrong with the open command */
618 if (open_err & 0x07) { /* Wrong speed, retry at different speed */
619 printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed \n", dev->name) ;
620 switchsettings = switchsettings ^ 2 ;
621 xl_ee_write(dev,0x08,switchsettings) ;
622 xl_hw_reset(dev) ;
623 open_err = xl_open_hw(dev) ;
624 if (open_err != 0) {
625 printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name);
626 free_irq(dev->irq,dev) ;
627 return -ENODEV ;
628 }
629 } else {
630 printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ;
631 free_irq(dev->irq,dev) ;
632 return -ENODEV ;
633 }
634 }
635
636 /*
637 * Now to set up the Rx and Tx buffer structures
638 */
639 /* These MUST be on 8 byte boundaries */
640 xl_priv->xl_tx_ring = kzalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL);
641 if (xl_priv->xl_tx_ring == NULL) {
642 printk(KERN_WARNING "%s: Not enough memory to allocate tx buffers.\n",
643 dev->name);
644 free_irq(dev->irq,dev);
645 return -ENOMEM;
646 }
647 xl_priv->xl_rx_ring = kzalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL);
648 if (xl_priv->xl_rx_ring == NULL) {
649 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n",
650 dev->name);
651 free_irq(dev->irq,dev);
652 kfree(xl_priv->xl_tx_ring);
653 return -ENOMEM;
654 }
655
656 /* Setup Rx Ring */
657 for (i=0 ; i < XL_RX_RING_SIZE ; i++) {
658 struct sk_buff *skb ;
659
660 skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
661 if (skb==NULL)
662 break ;
663
664 skb->dev = dev ;
665 xl_priv->xl_rx_ring[i].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
666 xl_priv->xl_rx_ring[i].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
667 xl_priv->rx_ring_skb[i] = skb ;
668 }
669
670 if (i==0) {
671 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled \n",dev->name) ;
672 free_irq(dev->irq,dev) ;
673 kfree(xl_priv->xl_tx_ring);
674 kfree(xl_priv->xl_rx_ring);
675 return -EIO ;
676 }
677
678 xl_priv->rx_ring_no = i ;
679 xl_priv->rx_ring_tail = 0 ;
680 xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ;
681 for (i=0;i<(xl_priv->rx_ring_no-1);i++) {
682 xl_priv->xl_rx_ring[i].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1)));
683 }
684 xl_priv->xl_rx_ring[i].upnextptr = 0 ;
685
686 writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ;
687
688 /* Setup Tx Ring */
689
690 xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ;
691
692 xl_priv->tx_ring_head = 1 ;
693 xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */
694 xl_priv->free_ring_entries = XL_TX_RING_SIZE ;
695
696 /*
697 * Setup the first dummy DPD entry for polling to start working.
698 */
699
700 xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY;
701 xl_priv->xl_tx_ring[0].buffer = 0 ;
702 xl_priv->xl_tx_ring[0].buffer_length = 0 ;
703 xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
704
705 writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ;
706 writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ;
707 writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ;
708 writel(DNENABLE, xl_mmio + MMIO_COMMAND) ;
709 writeb(0x40, xl_mmio + MMIO_DNPOLL) ;
710
711 /*
712 * Enable interrupts on the card
713 */
714
715 writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
716 writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
717
718 netif_start_queue(dev) ;
719 return 0;
720
721 }
722
723 static int xl_open_hw(struct net_device *dev)
724 {
725 struct xl_private *xl_priv=netdev_priv(dev);
726 u8 __iomem *xl_mmio = xl_priv->xl_mmio ;
727 u16 vsoff ;
728 char ver_str[33];
729 int open_err ;
730 int i ;
731 unsigned long t ;
732
733 /*
734 * Okay, let's build up the Open.NIC srb command
735 *
736 */
737
738 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
739 writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ;
740
741 /*
742 * Use this as a test byte, if it comes back with the same value, the command didn't work
743 */
744
745 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
746 writeb(0xff,xl_mmio + MMIO_MACDATA) ;
747
748 /* Open options */
749 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
750 writeb(0x00, xl_mmio + MMIO_MACDATA) ;
751 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
752 writeb(0x00, xl_mmio + MMIO_MACDATA) ;
753
754 /*
755 * Node address, be careful here, the docs say you can just put zeros here and it will use
756 * the hardware address, it doesn't, you must include the node address in the open command.
757 */
758
759 if (xl_priv->xl_laa[0]) { /* If using a LAA address */
760 for (i=10;i<16;i++) {
761 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
762 writeb(xl_priv->xl_laa[i-10],xl_mmio + MMIO_MACDATA) ;
763 }
764 memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ;
765 } else { /* Regular hardware address */
766 for (i=10;i<16;i++) {
767 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
768 writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ;
769 }
770 }
771
772 /* Default everything else to 0 */
773 for (i = 16; i < 34; i++) {
774 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
775 writeb(0x00,xl_mmio + MMIO_MACDATA) ;
776 }
777
778 /*
779 * Set the csrb bit in the MISR register
780 */
781
782 xl_wait_misr_flags(dev) ;
783 writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
784 writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
785 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
786 writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ;
787
788 /*
789 * Now wait for the command to run
790 */
791
792 t=jiffies;
793 while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
794 schedule();
795 if (time_after(jiffies, t + 40 * HZ)) {
796 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
797 break ;
798 }
799 }
800
801 /*
802 * Let's interpret the open response
803 */
804
805 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
806 if (readb(xl_mmio + MMIO_MACDATA)!=0) {
807 open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ;
808 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
809 open_err |= readb(xl_mmio + MMIO_MACDATA) ;
810 return open_err ;
811 } else {
812 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
813 xl_priv->asb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
814 printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ;
815 printk("ASB: %04x",xl_priv->asb ) ;
816 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
817 printk(", SRB: %04x",swab16(readw(xl_mmio + MMIO_MACDATA)) ) ;
818
819 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
820 xl_priv->arb = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
821 printk(", ARB: %04x \n",xl_priv->arb ) ;
822 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
823 vsoff = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
824
825 /*
826 * Interesting, sending the individual characters directly to printk was causing klogd to use
827 * use 100% of processor time, so we build up the string and print that instead.
828 */
829
830 for (i=0;i<0x20;i++) {
831 writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
832 ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ;
833 }
834 ver_str[i] = '\0' ;
835 printk(KERN_INFO "%s: Microcode version String: %s \n",dev->name,ver_str);
836 }
837
838 /*
839 * Issue the AckInterrupt
840 */
841 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
842
843 return 0 ;
844 }
845
846 /*
847 * There are two ways of implementing rx on the 359 NIC, either
848 * interrupt driven or polling. We are going to uses interrupts,
849 * it is the easier way of doing things.
850 *
851 * The Rx works with a ring of Rx descriptors. At initialise time the ring
852 * entries point to the next entry except for the last entry in the ring
853 * which points to 0. The card is programmed with the location of the first
854 * available descriptor and keeps reading the next_ptr until next_ptr is set
855 * to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr
856 * of 0. As the Rx interrupt is received we copy the frame up to the protocol layers
857 * and then point the end of the ring to our current position and point our current
858 * position to 0, therefore making the current position the last position on the ring.
859 * The last position on the ring therefore loops continually loops around the rx ring.
860 *
861 * rx_ring_tail is the position on the ring to process next. (Think of a snake, the head
862 * expands as the card adds new packets and we go around eating the tail processing the
863 * packets.)
864 *
865 * Undoubtably it could be streamlined and improved upon, but at the moment it works
866 * and the fast path through the routine is fine.
867 *
868 * adv_rx_ring could be inlined to increase performance, but its called a *lot* of times
869 * in xl_rx so would increase the size of the function significantly.
870 */
871
872 static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */
873 {
874 struct xl_private *xl_priv=netdev_priv(dev);
875 int n = xl_priv->rx_ring_tail;
876 int prev_ring_loc;
877
878 prev_ring_loc = (n + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1);
879 xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * n));
880 xl_priv->xl_rx_ring[n].framestatus = 0;
881 xl_priv->xl_rx_ring[n].upnextptr = 0;
882 xl_priv->rx_ring_tail++;
883 xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1);
884 }
885
886 static void xl_rx(struct net_device *dev)
887 {
888 struct xl_private *xl_priv=netdev_priv(dev);
889 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
890 struct sk_buff *skb, *skb2 ;
891 int frame_length = 0, copy_len = 0 ;
892 int temp_ring_loc ;
893
894 /*
895 * Receive the next frame, loop around the ring until all frames
896 * have been received.
897 */
898
899 while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */
900
901 if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */
902
903 /*
904 * This is a pain, you need to go through all the descriptors until the last one
905 * for this frame to find the framelength
906 */
907
908 temp_ring_loc = xl_priv->rx_ring_tail ;
909
910 while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) {
911 temp_ring_loc++ ;
912 temp_ring_loc &= (XL_RX_RING_SIZE-1) ;
913 }
914
915 frame_length = le32_to_cpu(xl_priv->xl_rx_ring[temp_ring_loc].framestatus) & 0x7FFF;
916
917 skb = dev_alloc_skb(frame_length) ;
918
919 if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */
920 printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ;
921 while (xl_priv->rx_ring_tail != temp_ring_loc)
922 adv_rx_ring(dev) ;
923
924 adv_rx_ring(dev) ; /* One more time just for luck :) */
925 dev->stats.rx_dropped++ ;
926
927 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
928 return ;
929 }
930
931 while (xl_priv->rx_ring_tail != temp_ring_loc) {
932 copy_len = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen) & 0x7FFF;
933 frame_length -= copy_len ;
934 pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
935 skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
936 skb_put(skb, copy_len),
937 copy_len);
938 pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
939 adv_rx_ring(dev) ;
940 }
941
942 /* Now we have found the last fragment */
943 pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
944 skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail],
945 skb_put(skb,copy_len), frame_length);
946 /* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */
947 pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE);
948 adv_rx_ring(dev) ;
949 skb->protocol = tr_type_trans(skb,dev) ;
950 netif_rx(skb) ;
951
952 } else { /* Single Descriptor Used, simply swap buffers over, fast path */
953
954 frame_length = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus) & 0x7FFF;
955
956 skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
957
958 if (skb==NULL) { /* Still need to fix the rx ring */
959 printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer \n",dev->name) ;
960 adv_rx_ring(dev) ;
961 dev->stats.rx_dropped++ ;
962 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
963 return ;
964 }
965
966 skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ;
967 pci_unmap_single(xl_priv->pdev, le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
968 skb_put(skb2, frame_length) ;
969 skb2->protocol = tr_type_trans(skb2,dev) ;
970
971 xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ;
972 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE));
973 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG;
974 adv_rx_ring(dev) ;
975 dev->stats.rx_packets++ ;
976 dev->stats.rx_bytes += frame_length ;
977
978 netif_rx(skb2) ;
979 } /* if multiple buffers */
980 } /* while packet to do */
981
982 /* Clear the updComplete interrupt */
983 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
984 return ;
985 }
986
987 /*
988 * This is ruthless, it doesn't care what state the card is in it will
989 * completely reset the adapter.
990 */
991
992 static void xl_reset(struct net_device *dev)
993 {
994 struct xl_private *xl_priv=netdev_priv(dev);
995 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
996 unsigned long t;
997
998 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
999
1000 /*
1001 * Must wait for cmdInProgress bit (12) to clear before continuing with
1002 * card configuration.
1003 */
1004
1005 t=jiffies;
1006 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1007 if (time_after(jiffies, t + 40 * HZ)) {
1008 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
1009 break ;
1010 }
1011 }
1012
1013 }
1014
1015 static void xl_freemem(struct net_device *dev)
1016 {
1017 struct xl_private *xl_priv=netdev_priv(dev);
1018 int i ;
1019
1020 for (i=0;i<XL_RX_RING_SIZE;i++) {
1021 dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ;
1022 pci_unmap_single(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE);
1023 xl_priv->rx_ring_tail++ ;
1024 xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1;
1025 }
1026
1027 /* unmap ring */
1028 pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ;
1029
1030 pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ;
1031
1032 kfree(xl_priv->xl_rx_ring) ;
1033 kfree(xl_priv->xl_tx_ring) ;
1034
1035 return ;
1036 }
1037
1038 static irqreturn_t xl_interrupt(int irq, void *dev_id)
1039 {
1040 struct net_device *dev = (struct net_device *)dev_id;
1041 struct xl_private *xl_priv =netdev_priv(dev);
1042 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1043 u16 intstatus, macstatus ;
1044
1045 intstatus = readw(xl_mmio + MMIO_INTSTATUS) ;
1046
1047 if (!(intstatus & 1)) /* We didn't generate the interrupt */
1048 return IRQ_NONE;
1049
1050 spin_lock(&xl_priv->xl_lock) ;
1051
1052 /*
1053 * Process the interrupt
1054 */
1055 /*
1056 * Something fishy going on here, we shouldn't get 0001 ints, not fatal though.
1057 */
1058 if (intstatus == 0x0001) {
1059 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1060 printk(KERN_INFO "%s: 00001 int received \n",dev->name) ;
1061 } else {
1062 if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) {
1063
1064 /*
1065 * Host Error.
1066 * It may be possible to recover from this, but usually it means something
1067 * is seriously fubar, so we just close the adapter.
1068 */
1069
1070 if (intstatus & HOSTERRINT) {
1071 printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x \n",dev->name,intstatus) ;
1072 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
1073 printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
1074 netif_stop_queue(dev) ;
1075 xl_freemem(dev) ;
1076 free_irq(dev->irq,dev);
1077 xl_reset(dev) ;
1078 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1079 spin_unlock(&xl_priv->xl_lock) ;
1080 return IRQ_HANDLED;
1081 } /* Host Error */
1082
1083 if (intstatus & SRBRINT ) { /* Srbc interrupt */
1084 writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1085 if (xl_priv->srb_queued)
1086 xl_srb_bh(dev) ;
1087 } /* SRBR Interrupt */
1088
1089 if (intstatus & TXUNDERRUN) { /* Issue DnReset command */
1090 writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1091 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */
1092 /* !!! FIX-ME !!!!
1093 Must put a timeout check here ! */
1094 /* Empty Loop */
1095 }
1096 printk(KERN_WARNING "%s: TX Underrun received \n",dev->name) ;
1097 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1098 } /* TxUnderRun */
1099
1100 if (intstatus & ARBCINT ) { /* Arbc interrupt */
1101 xl_arb_cmd(dev) ;
1102 } /* Arbc */
1103
1104 if (intstatus & ASBFINT) {
1105 if (xl_priv->asb_queued == 1) {
1106 xl_asb_cmd(dev) ;
1107 } else if (xl_priv->asb_queued == 2) {
1108 xl_asb_bh(dev) ;
1109 } else {
1110 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1111 }
1112 } /* Asbf */
1113
1114 if (intstatus & UPCOMPINT ) /* UpComplete */
1115 xl_rx(dev) ;
1116
1117 if (intstatus & DNCOMPINT ) /* DnComplete */
1118 xl_dn_comp(dev) ;
1119
1120 if (intstatus & HARDERRINT ) { /* Hardware error */
1121 writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1122 macstatus = readw(xl_mmio + MMIO_MACDATA) ;
1123 printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name);
1124 if (macstatus & (1<<14))
1125 printk(KERN_WARNING "tchk error: Unrecoverable error \n") ;
1126 if (macstatus & (1<<3))
1127 printk(KERN_WARNING "eint error: Internal watchdog timer expired \n") ;
1128 if (macstatus & (1<<2))
1129 printk(KERN_WARNING "aint error: Host tried to perform invalid operation \n") ;
1130 printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ;
1131 printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
1132 netif_stop_queue(dev) ;
1133 xl_freemem(dev) ;
1134 free_irq(dev->irq,dev);
1135 unregister_netdev(dev) ;
1136 free_netdev(dev) ;
1137 xl_reset(dev) ;
1138 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1139 spin_unlock(&xl_priv->xl_lock) ;
1140 return IRQ_HANDLED;
1141 }
1142 } else {
1143 printk(KERN_WARNING "%s: Received Unknown interrupt : %04x \n", dev->name, intstatus) ;
1144 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1145 }
1146 }
1147
1148 /* Turn interrupts back on */
1149
1150 writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
1151 writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
1152
1153 spin_unlock(&xl_priv->xl_lock) ;
1154 return IRQ_HANDLED;
1155 }
1156
1157 /*
1158 * Tx - Polling configuration
1159 */
1160
1161 static int xl_xmit(struct sk_buff *skb, struct net_device *dev)
1162 {
1163 struct xl_private *xl_priv=netdev_priv(dev);
1164 struct xl_tx_desc *txd ;
1165 int tx_head, tx_tail, tx_prev ;
1166 unsigned long flags ;
1167
1168 spin_lock_irqsave(&xl_priv->xl_lock,flags) ;
1169
1170 netif_stop_queue(dev) ;
1171
1172 if (xl_priv->free_ring_entries > 1 ) {
1173 /*
1174 * Set up the descriptor for the packet
1175 */
1176 tx_head = xl_priv->tx_ring_head ;
1177 tx_tail = xl_priv->tx_ring_tail ;
1178
1179 txd = &(xl_priv->xl_tx_ring[tx_head]) ;
1180 txd->dnnextptr = 0 ;
1181 txd->framestartheader = cpu_to_le32(skb->len) | TXDNINDICATE;
1182 txd->buffer = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE));
1183 txd->buffer_length = cpu_to_le32(skb->len) | TXDNFRAGLAST;
1184 xl_priv->tx_ring_skb[tx_head] = skb ;
1185 dev->stats.tx_packets++ ;
1186 dev->stats.tx_bytes += skb->len ;
1187
1188 /*
1189 * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1
1190 * to ensure no negative numbers in unsigned locations.
1191 */
1192
1193 tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ;
1194
1195 xl_priv->tx_ring_head++ ;
1196 xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ;
1197 xl_priv->free_ring_entries-- ;
1198
1199 xl_priv->xl_tx_ring[tx_prev].dnnextptr = cpu_to_le32(xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head));
1200
1201 /* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */
1202 /* readl(xl_mmio + MMIO_DNLISTPTR) ; */
1203
1204 netif_wake_queue(dev) ;
1205
1206 spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
1207
1208 return 0;
1209 } else {
1210 spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
1211 return 1;
1212 }
1213
1214 }
1215
1216 /*
1217 * The NIC has told us that a packet has been downloaded onto the card, we must
1218 * find out which packet it has done, clear the skb and information for the packet
1219 * then advance around the ring for all tranmitted packets
1220 */
1221
1222 static void xl_dn_comp(struct net_device *dev)
1223 {
1224 struct xl_private *xl_priv=netdev_priv(dev);
1225 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1226 struct xl_tx_desc *txd ;
1227
1228
1229 if (xl_priv->tx_ring_tail == 255) {/* First time */
1230 xl_priv->xl_tx_ring[0].framestartheader = 0 ;
1231 xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
1232 xl_priv->tx_ring_tail = 1 ;
1233 }
1234
1235 while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) {
1236 txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ;
1237 pci_unmap_single(xl_priv->pdev, le32_to_cpu(txd->buffer), xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE);
1238 txd->framestartheader = 0 ;
1239 txd->buffer = cpu_to_le32(0xdeadbeef);
1240 txd->buffer_length = 0 ;
1241 dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ;
1242 xl_priv->tx_ring_tail++ ;
1243 xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ;
1244 xl_priv->free_ring_entries++ ;
1245 }
1246
1247 netif_wake_queue(dev) ;
1248
1249 writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1250 }
1251
1252 /*
1253 * Close the adapter properly.
1254 * This srb reply cannot be handled from interrupt context as we have
1255 * to free the interrupt from the driver.
1256 */
1257
1258 static int xl_close(struct net_device *dev)
1259 {
1260 struct xl_private *xl_priv = netdev_priv(dev);
1261 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1262 unsigned long t ;
1263
1264 netif_stop_queue(dev) ;
1265
1266 /*
1267 * Close the adapter, need to stall the rx and tx queues.
1268 */
1269
1270 writew(DNSTALL, xl_mmio + MMIO_COMMAND) ;
1271 t=jiffies;
1272 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1273 schedule();
1274 if (time_after(jiffies, t + 10 * HZ)) {
1275 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name);
1276 break ;
1277 }
1278 }
1279 writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ;
1280 t=jiffies;
1281 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1282 schedule();
1283 if (time_after(jiffies, t + 10 * HZ)) {
1284 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name);
1285 break ;
1286 }
1287 }
1288 writew(UPSTALL, xl_mmio + MMIO_COMMAND) ;
1289 t=jiffies;
1290 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1291 schedule();
1292 if (time_after(jiffies, t + 10 * HZ)) {
1293 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name);
1294 break ;
1295 }
1296 }
1297
1298 /* Turn off interrupts, we will still get the indication though
1299 * so we can trap it
1300 */
1301
1302 writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ;
1303
1304 xl_srb_cmd(dev,CLOSE_NIC) ;
1305
1306 t=jiffies;
1307 while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
1308 schedule();
1309 if (time_after(jiffies, t + 10 * HZ)) {
1310 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name);
1311 break ;
1312 }
1313 }
1314 /* Read the srb response from the adapter */
1315
1316 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD);
1317 if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) {
1318 printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response \n",dev->name) ;
1319 } else {
1320 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1321 if (readb(xl_mmio + MMIO_MACDATA)==0) {
1322 printk(KERN_INFO "%s: Adapter has been closed \n",dev->name) ;
1323 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1324
1325 xl_freemem(dev) ;
1326 free_irq(dev->irq,dev) ;
1327 } else {
1328 printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ;
1329 }
1330 }
1331
1332 /* Reset the upload and download logic */
1333
1334 writew(UPRESET, xl_mmio + MMIO_COMMAND) ;
1335 t=jiffies;
1336 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1337 schedule();
1338 if (time_after(jiffies, t + 10 * HZ)) {
1339 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name);
1340 break ;
1341 }
1342 }
1343 writew(DNRESET, xl_mmio + MMIO_COMMAND) ;
1344 t=jiffies;
1345 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
1346 schedule();
1347 if (time_after(jiffies, t + 10 * HZ)) {
1348 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name);
1349 break ;
1350 }
1351 }
1352 xl_hw_reset(dev) ;
1353 return 0 ;
1354 }
1355
1356 static void xl_set_rx_mode(struct net_device *dev)
1357 {
1358 struct xl_private *xl_priv = netdev_priv(dev);
1359 struct dev_mc_list *dmi ;
1360 unsigned char dev_mc_address[4] ;
1361 u16 options ;
1362 int i ;
1363
1364 if (dev->flags & IFF_PROMISC)
1365 options = 0x0004 ;
1366 else
1367 options = 0x0000 ;
1368
1369 if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */
1370 xl_priv->xl_copy_all_options = options ;
1371 xl_srb_cmd(dev, SET_RECEIVE_MODE) ;
1372 return ;
1373 }
1374
1375 dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
1376
1377 for (i=0,dmi=dev->mc_list;i < dev->mc_count; i++,dmi = dmi->next) {
1378 dev_mc_address[0] |= dmi->dmi_addr[2] ;
1379 dev_mc_address[1] |= dmi->dmi_addr[3] ;
1380 dev_mc_address[2] |= dmi->dmi_addr[4] ;
1381 dev_mc_address[3] |= dmi->dmi_addr[5] ;
1382 }
1383
1384 if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */
1385 memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ;
1386 xl_srb_cmd(dev, SET_FUNC_ADDRESS) ;
1387 }
1388 return ;
1389 }
1390
1391
1392 /*
1393 * We issued an srb command and now we must read
1394 * the response from the completed command.
1395 */
1396
1397 static void xl_srb_bh(struct net_device *dev)
1398 {
1399 struct xl_private *xl_priv = netdev_priv(dev);
1400 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1401 u8 srb_cmd, ret_code ;
1402 int i ;
1403
1404 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1405 srb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
1406 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1407 ret_code = readb(xl_mmio + MMIO_MACDATA) ;
1408
1409 /* Ret_code is standard across all commands */
1410
1411 switch (ret_code) {
1412 case 1:
1413 printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ;
1414 break ;
1415 case 4:
1416 printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command \n",dev->name,srb_cmd) ;
1417 break ;
1418
1419 case 6:
1420 printk(KERN_INFO "%s: Command: %d - Options Invalid for command \n",dev->name,srb_cmd) ;
1421 break ;
1422
1423 case 0: /* Successful command execution */
1424 switch (srb_cmd) {
1425 case READ_LOG: /* Returns 14 bytes of data from the NIC */
1426 if(xl_priv->xl_message_level)
1427 printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ;
1428 /*
1429 * We still have to read the log even if message_level = 0 and we don't want
1430 * to see it
1431 */
1432 for (i=0;i<14;i++) {
1433 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1434 if(xl_priv->xl_message_level)
1435 printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ;
1436 }
1437 printk("\n") ;
1438 break ;
1439 case SET_FUNC_ADDRESS:
1440 if(xl_priv->xl_message_level)
1441 printk(KERN_INFO "%s: Functional Address Set \n",dev->name) ;
1442 break ;
1443 case CLOSE_NIC:
1444 if(xl_priv->xl_message_level)
1445 printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler \n",dev->name) ;
1446 break ;
1447 case SET_MULTICAST_MODE:
1448 if(xl_priv->xl_message_level)
1449 printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ;
1450 break ;
1451 case SET_RECEIVE_MODE:
1452 if(xl_priv->xl_message_level) {
1453 if (xl_priv->xl_copy_all_options == 0x0004)
1454 printk(KERN_INFO "%s: Entering promiscuous mode \n", dev->name) ;
1455 else
1456 printk(KERN_INFO "%s: Entering normal receive mode \n",dev->name) ;
1457 }
1458 break ;
1459
1460 } /* switch */
1461 break ;
1462 } /* switch */
1463 return ;
1464 }
1465
1466 static int xl_set_mac_address (struct net_device *dev, void *addr)
1467 {
1468 struct sockaddr *saddr = addr ;
1469 struct xl_private *xl_priv = netdev_priv(dev);
1470
1471 if (netif_running(dev)) {
1472 printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ;
1473 return -EIO ;
1474 }
1475
1476 memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ;
1477
1478 if (xl_priv->xl_message_level) {
1479 printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0],
1480 xl_priv->xl_laa[1], xl_priv->xl_laa[2],
1481 xl_priv->xl_laa[3], xl_priv->xl_laa[4],
1482 xl_priv->xl_laa[5]);
1483 }
1484
1485 return 0 ;
1486 }
1487
1488 static void xl_arb_cmd(struct net_device *dev)
1489 {
1490 struct xl_private *xl_priv = netdev_priv(dev);
1491 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1492 u8 arb_cmd ;
1493 u16 lan_status, lan_status_diff ;
1494
1495 writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1496 arb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
1497
1498 if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */
1499 writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1500
1501 printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, swab16(readw(xl_mmio + MMIO_MACDATA) )) ;
1502
1503 lan_status = swab16(readw(xl_mmio + MMIO_MACDATA));
1504
1505 /* Acknowledge interrupt, this tells nic we are done with the arb */
1506 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1507
1508 lan_status_diff = xl_priv->xl_lan_status ^ lan_status ;
1509
1510 if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) {
1511 if (lan_status_diff & LSC_LWF)
1512 printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name);
1513 if (lan_status_diff & LSC_ARW)
1514 printk(KERN_WARNING "%s: Auto removal error\n",dev->name);
1515 if (lan_status_diff & LSC_FPE)
1516 printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name);
1517 if (lan_status_diff & LSC_RR)
1518 printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name);
1519
1520 /* Adapter has been closed by the hardware */
1521
1522 netif_stop_queue(dev);
1523 xl_freemem(dev) ;
1524 free_irq(dev->irq,dev);
1525
1526 printk(KERN_WARNING "%s: Adapter has been closed \n", dev->name) ;
1527 } /* If serious error */
1528
1529 if (xl_priv->xl_message_level) {
1530 if (lan_status_diff & LSC_SIG_LOSS)
1531 printk(KERN_WARNING "%s: No receive signal detected \n", dev->name) ;
1532 if (lan_status_diff & LSC_HARD_ERR)
1533 printk(KERN_INFO "%s: Beaconing \n",dev->name);
1534 if (lan_status_diff & LSC_SOFT_ERR)
1535 printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame \n",dev->name);
1536 if (lan_status_diff & LSC_TRAN_BCN)
1537 printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n",dev->name);
1538 if (lan_status_diff & LSC_SS)
1539 printk(KERN_INFO "%s: Single Station on the ring \n", dev->name);
1540 if (lan_status_diff & LSC_RING_REC)
1541 printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name);
1542 if (lan_status_diff & LSC_FDX_MODE)
1543 printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name);
1544 }
1545
1546 if (lan_status_diff & LSC_CO) {
1547 if (xl_priv->xl_message_level)
1548 printk(KERN_INFO "%s: Counter Overflow \n", dev->name);
1549 /* Issue READ.LOG command */
1550 xl_srb_cmd(dev, READ_LOG) ;
1551 }
1552
1553 /* There is no command in the tech docs to issue the read_sr_counters */
1554 if (lan_status_diff & LSC_SR_CO) {
1555 if (xl_priv->xl_message_level)
1556 printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
1557 }
1558
1559 xl_priv->xl_lan_status = lan_status ;
1560
1561 } /* Lan.change.status */
1562 else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */
1563 #if XL_DEBUG
1564 printk(KERN_INFO "Received.Data \n") ;
1565 #endif
1566 writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1567 xl_priv->mac_buffer = swab16(readw(xl_mmio + MMIO_MACDATA)) ;
1568
1569 /* Now we are going to be really basic here and not do anything
1570 * with the data at all. The tech docs do not give me enough
1571 * information to calculate the buffers properly so we're
1572 * just going to tell the nic that we've dealt with the frame
1573 * anyway.
1574 */
1575
1576 /* Acknowledge interrupt, this tells nic we are done with the arb */
1577 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
1578
1579 /* Is the ASB free ? */
1580
1581 xl_priv->asb_queued = 0 ;
1582 writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1583 if (readb(xl_mmio + MMIO_MACDATA) != 0xff) {
1584 xl_priv->asb_queued = 1 ;
1585
1586 xl_wait_misr_flags(dev) ;
1587
1588 writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD);
1589 writeb(0xff, xl_mmio + MMIO_MACDATA) ;
1590 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1591 writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ;
1592 return ;
1593 /* Drop out and wait for the bottom half to be run */
1594 }
1595
1596 xl_asb_cmd(dev) ;
1597
1598 } else {
1599 printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x \n",dev->name,arb_cmd) ;
1600 }
1601
1602 /* Acknowledge the arb interrupt */
1603
1604 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
1605
1606 return ;
1607 }
1608
1609
1610 /*
1611 * There is only one asb command, but we can get called from different
1612 * places.
1613 */
1614
1615 static void xl_asb_cmd(struct net_device *dev)
1616 {
1617 struct xl_private *xl_priv = netdev_priv(dev);
1618 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1619
1620 if (xl_priv->asb_queued == 1)
1621 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1622
1623 writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1624 writeb(0x81, xl_mmio + MMIO_MACDATA) ;
1625
1626 writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1627 writew(swab16(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ;
1628
1629 xl_wait_misr_flags(dev) ;
1630
1631 writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD);
1632 writeb(0xff, xl_mmio + MMIO_MACDATA) ;
1633
1634 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1635 writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ;
1636
1637 xl_priv->asb_queued = 2 ;
1638
1639 return ;
1640 }
1641
1642 /*
1643 * This will only get called if there was an error
1644 * from the asb cmd.
1645 */
1646 static void xl_asb_bh(struct net_device *dev)
1647 {
1648 struct xl_private *xl_priv = netdev_priv(dev);
1649 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1650 u8 ret_code ;
1651
1652 writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1653 ret_code = readb(xl_mmio + MMIO_MACDATA) ;
1654 switch (ret_code) {
1655 case 0x01:
1656 printk(KERN_INFO "%s: ASB Command, unrecognized command code \n",dev->name) ;
1657 break ;
1658 case 0x26:
1659 printk(KERN_INFO "%s: ASB Command, unexpected receive buffer \n", dev->name) ;
1660 break ;
1661 case 0x40:
1662 printk(KERN_INFO "%s: ASB Command, Invalid Station ID \n", dev->name) ;
1663 break ;
1664 }
1665 xl_priv->asb_queued = 0 ;
1666 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
1667 return ;
1668 }
1669
1670 /*
1671 * Issue srb commands to the nic
1672 */
1673
1674 static void xl_srb_cmd(struct net_device *dev, int srb_cmd)
1675 {
1676 struct xl_private *xl_priv = netdev_priv(dev);
1677 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1678
1679 switch (srb_cmd) {
1680 case READ_LOG:
1681 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1682 writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ;
1683 break;
1684
1685 case CLOSE_NIC:
1686 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1687 writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ;
1688 break ;
1689
1690 case SET_RECEIVE_MODE:
1691 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1692 writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ;
1693 writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1694 writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ;
1695 break ;
1696
1697 case SET_FUNC_ADDRESS:
1698 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1699 writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ;
1700 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1701 writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ;
1702 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1703 writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ;
1704 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1705 writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ;
1706 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1707 writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ;
1708 break ;
1709 } /* switch */
1710
1711
1712 xl_wait_misr_flags(dev) ;
1713
1714 /* Write 0xff to the CSRB flag */
1715 writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1716 writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
1717 /* Set csrb bit in MISR register to process command */
1718 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1719 writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ;
1720 xl_priv->srb_queued = 1 ;
1721
1722 return ;
1723 }
1724
1725 /*
1726 * This is nasty, to use the MISR command you have to wait for 6 memory locations
1727 * to be zero. This is the way the driver does on other OS'es so we should be ok with
1728 * the empty loop.
1729 */
1730
1731 static void xl_wait_misr_flags(struct net_device *dev)
1732 {
1733 struct xl_private *xl_priv = netdev_priv(dev);
1734 u8 __iomem * xl_mmio = xl_priv->xl_mmio ;
1735
1736 int i ;
1737
1738 writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1739 if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */
1740 for (i=0; i<6; i++) {
1741 writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1742 while (readb(xl_mmio + MMIO_MACDATA) != 0 ) {} ; /* Empty Loop */
1743 }
1744 }
1745
1746 writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
1747 writeb(0x80, xl_mmio + MMIO_MACDATA) ;
1748
1749 return ;
1750 }
1751
1752 /*
1753 * Change mtu size, this should work the same as olympic
1754 */
1755
1756 static int xl_change_mtu(struct net_device *dev, int mtu)
1757 {
1758 struct xl_private *xl_priv = netdev_priv(dev);
1759 u16 max_mtu ;
1760
1761 if (xl_priv->xl_ring_speed == 4)
1762 max_mtu = 4500 ;
1763 else
1764 max_mtu = 18000 ;
1765
1766 if (mtu > max_mtu)
1767 return -EINVAL ;
1768 if (mtu < 100)
1769 return -EINVAL ;
1770
1771 dev->mtu = mtu ;
1772 xl_priv->pkt_buf_sz = mtu + TR_HLEN ;
1773
1774 return 0 ;
1775 }
1776
1777 static void __devexit xl_remove_one (struct pci_dev *pdev)
1778 {
1779 struct net_device *dev = pci_get_drvdata(pdev);
1780 struct xl_private *xl_priv=netdev_priv(dev);
1781
1782 unregister_netdev(dev);
1783 iounmap(xl_priv->xl_mmio) ;
1784 pci_release_regions(pdev) ;
1785 pci_set_drvdata(pdev,NULL) ;
1786 free_netdev(dev);
1787 return ;
1788 }
1789
1790 static struct pci_driver xl_3c359_driver = {
1791 .name = "3c359",
1792 .id_table = xl_pci_tbl,
1793 .probe = xl_probe,
1794 .remove = __devexit_p(xl_remove_one),
1795 };
1796
1797 static int __init xl_pci_init (void)
1798 {
1799 return pci_register_driver(&xl_3c359_driver);
1800 }
1801
1802
1803 static void __exit xl_pci_cleanup (void)
1804 {
1805 pci_unregister_driver (&xl_3c359_driver);
1806 }
1807
1808 module_init(xl_pci_init);
1809 module_exit(xl_pci_cleanup);
1810
1811 MODULE_LICENSE("GPL") ;
Nao low-level kernelspace/userspace library that runs on our robots, Nao-Team HTWK