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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / net / sungem.c
blobb8a24b74c17da357b9b173d01b985b6c04061a78
1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
5 *
6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
12 *
13 * TODO:
14 * - Now that the driver was significantly simplified, I need to rework
15 * the locking. I'm sure we don't need _2_ spinlocks, and we probably
16 * can avoid taking most of them for so long period of time (and schedule
17 * instead). The main issues at this point are caused by the netdev layer
18 * though:
19 *
20 * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
21 * help by net/core/dev.c, thus they can't schedule. That means they can't
22 * call napi_disable() neither, thus force gem_poll() to keep a spinlock
23 * where it could have been dropped. change_mtu especially would love also to
24 * be able to msleep instead of horrid locked delays when resetting the HW,
25 * but that read_lock() makes it impossible, unless I defer it's action to
26 * the reset task, which means it'll be asynchronous (won't take effect until
27 * the system schedules a bit).
28 *
29 * Also, it would probably be possible to also remove most of the long-life
30 * locking in open/resume code path (gem_reinit_chip) by beeing more careful
31 * about when we can start taking interrupts or get xmit() called...
32 */
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/fcntl.h>
38 #include <linux/interrupt.h>
39 #include <linux/ioport.h>
40 #include <linux/in.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/delay.h>
44 #include <linux/init.h>
45 #include <linux/errno.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/mii.h>
52 #include <linux/ethtool.h>
53 #include <linux/crc32.h>
54 #include <linux/random.h>
55 #include <linux/workqueue.h>
56 #include <linux/if_vlan.h>
57 #include <linux/bitops.h>
58 #include <linux/mutex.h>
59 #include <linux/mm.h>
60
61 #include <asm/system.h>
62 #include <asm/io.h>
63 #include <asm/byteorder.h>
64 #include <asm/uaccess.h>
65 #include <asm/irq.h>
66
67 #ifdef CONFIG_SPARC
68 #include <asm/idprom.h>
69 #include <asm/prom.h>
70 #endif
71
72 #ifdef CONFIG_PPC_PMAC
73 #include <asm/pci-bridge.h>
74 #include <asm/prom.h>
75 #include <asm/machdep.h>
76 #include <asm/pmac_feature.h>
77 #endif
78
79 #include "sungem_phy.h"
80 #include "sungem.h"
81
82 /* Stripping FCS is causing problems, disabled for now */
83 #undef STRIP_FCS
84
85 #define DEFAULT_MSG (NETIF_MSG_DRV | \
86 NETIF_MSG_PROBE | \
87 NETIF_MSG_LINK)
88
89 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
90 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
91 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
92 SUPPORTED_Pause | SUPPORTED_Autoneg)
93
94 #define DRV_NAME "sungem"
95 #define DRV_VERSION "0.98"
96 #define DRV_RELDATE "8/24/03"
97 #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
98
99 static char version[] __devinitdata =
100 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
101
102 MODULE_AUTHOR(DRV_AUTHOR);
103 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
104 MODULE_LICENSE("GPL");
105
106 #define GEM_MODULE_NAME "gem"
107 #define PFX GEM_MODULE_NAME ": "
108
109 static struct pci_device_id gem_pci_tbl[] = {
110 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
112
113 /* These models only differ from the original GEM in
114 * that their tx/rx fifos are of a different size and
115 * they only support 10/100 speeds. -DaveM
116 *
117 * Apple's GMAC does support gigabit on machines with
118 * the BCM54xx PHYs. -BenH
119 */
120 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
122 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
124 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
126 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
128 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
130 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
132 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
134 {0, }
135 };
136
137 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
138
139 static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
140 {
141 u32 cmd;
142 int limit = 10000;
143
144 cmd = (1 << 30);
145 cmd |= (2 << 28);
146 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
147 cmd |= (reg << 18) & MIF_FRAME_REGAD;
148 cmd |= (MIF_FRAME_TAMSB);
149 writel(cmd, gp->regs + MIF_FRAME);
150
151 while (--limit) {
152 cmd = readl(gp->regs + MIF_FRAME);
153 if (cmd & MIF_FRAME_TALSB)
154 break;
155
156 udelay(10);
157 }
158
159 if (!limit)
160 cmd = 0xffff;
161
162 return cmd & MIF_FRAME_DATA;
163 }
164
165 static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
166 {
167 struct gem *gp = netdev_priv(dev);
168 return __phy_read(gp, mii_id, reg);
169 }
170
171 static inline u16 phy_read(struct gem *gp, int reg)
172 {
173 return __phy_read(gp, gp->mii_phy_addr, reg);
174 }
175
176 static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
177 {
178 u32 cmd;
179 int limit = 10000;
180
181 cmd = (1 << 30);
182 cmd |= (1 << 28);
183 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
184 cmd |= (reg << 18) & MIF_FRAME_REGAD;
185 cmd |= (MIF_FRAME_TAMSB);
186 cmd |= (val & MIF_FRAME_DATA);
187 writel(cmd, gp->regs + MIF_FRAME);
188
189 while (limit--) {
190 cmd = readl(gp->regs + MIF_FRAME);
191 if (cmd & MIF_FRAME_TALSB)
192 break;
193
194 udelay(10);
195 }
196 }
197
198 static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
199 {
200 struct gem *gp = netdev_priv(dev);
201 __phy_write(gp, mii_id, reg, val & 0xffff);
202 }
203
204 static inline void phy_write(struct gem *gp, int reg, u16 val)
205 {
206 __phy_write(gp, gp->mii_phy_addr, reg, val);
207 }
208
209 static inline void gem_enable_ints(struct gem *gp)
210 {
211 /* Enable all interrupts but TXDONE */
212 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
213 }
214
215 static inline void gem_disable_ints(struct gem *gp)
216 {
217 /* Disable all interrupts, including TXDONE */
218 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
219 }
220
221 static void gem_get_cell(struct gem *gp)
222 {
223 BUG_ON(gp->cell_enabled < 0);
224 gp->cell_enabled++;
225 #ifdef CONFIG_PPC_PMAC
226 if (gp->cell_enabled == 1) {
227 mb();
228 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
229 udelay(10);
230 }
231 #endif /* CONFIG_PPC_PMAC */
232 }
233
234 /* Turn off the chip's clock */
235 static void gem_put_cell(struct gem *gp)
236 {
237 BUG_ON(gp->cell_enabled <= 0);
238 gp->cell_enabled--;
239 #ifdef CONFIG_PPC_PMAC
240 if (gp->cell_enabled == 0) {
241 mb();
242 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
243 udelay(10);
244 }
245 #endif /* CONFIG_PPC_PMAC */
246 }
247
248 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
249 {
250 if (netif_msg_intr(gp))
251 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
252 }
253
254 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
255 {
256 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
257 u32 pcs_miistat;
258
259 if (netif_msg_intr(gp))
260 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
261 gp->dev->name, pcs_istat);
262
263 if (!(pcs_istat & PCS_ISTAT_LSC)) {
264 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
265 dev->name);
266 return 0;
267 }
268
269 /* The link status bit latches on zero, so you must
270 * read it twice in such a case to see a transition
271 * to the link being up.
272 */
273 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
274 if (!(pcs_miistat & PCS_MIISTAT_LS))
275 pcs_miistat |=
276 (readl(gp->regs + PCS_MIISTAT) &
277 PCS_MIISTAT_LS);
278
279 if (pcs_miistat & PCS_MIISTAT_ANC) {
280 /* The remote-fault indication is only valid
281 * when autoneg has completed.
282 */
283 if (pcs_miistat & PCS_MIISTAT_RF)
284 printk(KERN_INFO "%s: PCS AutoNEG complete, "
285 "RemoteFault\n", dev->name);
286 else
287 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
288 dev->name);
289 }
290
291 if (pcs_miistat & PCS_MIISTAT_LS) {
292 printk(KERN_INFO "%s: PCS link is now up.\n",
293 dev->name);
294 netif_carrier_on(gp->dev);
295 } else {
296 printk(KERN_INFO "%s: PCS link is now down.\n",
297 dev->name);
298 netif_carrier_off(gp->dev);
299 /* If this happens and the link timer is not running,
300 * reset so we re-negotiate.
301 */
302 if (!timer_pending(&gp->link_timer))
303 return 1;
304 }
305
306 return 0;
307 }
308
309 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
310 {
311 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
312
313 if (netif_msg_intr(gp))
314 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
315 gp->dev->name, txmac_stat);
316
317 /* Defer timer expiration is quite normal,
318 * don't even log the event.
319 */
320 if ((txmac_stat & MAC_TXSTAT_DTE) &&
321 !(txmac_stat & ~MAC_TXSTAT_DTE))
322 return 0;
323
324 if (txmac_stat & MAC_TXSTAT_URUN) {
325 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
326 dev->name);
327 gp->net_stats.tx_fifo_errors++;
328 }
329
330 if (txmac_stat & MAC_TXSTAT_MPE) {
331 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
332 dev->name);
333 gp->net_stats.tx_errors++;
334 }
335
336 /* The rest are all cases of one of the 16-bit TX
337 * counters expiring.
338 */
339 if (txmac_stat & MAC_TXSTAT_NCE)
340 gp->net_stats.collisions += 0x10000;
341
342 if (txmac_stat & MAC_TXSTAT_ECE) {
343 gp->net_stats.tx_aborted_errors += 0x10000;
344 gp->net_stats.collisions += 0x10000;
345 }
346
347 if (txmac_stat & MAC_TXSTAT_LCE) {
348 gp->net_stats.tx_aborted_errors += 0x10000;
349 gp->net_stats.collisions += 0x10000;
350 }
351
352 /* We do not keep track of MAC_TXSTAT_FCE and
353 * MAC_TXSTAT_PCE events.
354 */
355 return 0;
356 }
357
358 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
359 * so we do the following.
360 *
361 * If any part of the reset goes wrong, we return 1 and that causes the
362 * whole chip to be reset.
363 */
364 static int gem_rxmac_reset(struct gem *gp)
365 {
366 struct net_device *dev = gp->dev;
367 int limit, i;
368 u64 desc_dma;
369 u32 val;
370
371 /* First, reset & disable MAC RX. */
372 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
373 for (limit = 0; limit < 5000; limit++) {
374 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
375 break;
376 udelay(10);
377 }
378 if (limit == 5000) {
379 printk(KERN_ERR "%s: RX MAC will not reset, resetting whole "
380 "chip.\n", dev->name);
381 return 1;
382 }
383
384 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
385 gp->regs + MAC_RXCFG);
386 for (limit = 0; limit < 5000; limit++) {
387 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
388 break;
389 udelay(10);
390 }
391 if (limit == 5000) {
392 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
393 "chip.\n", dev->name);
394 return 1;
395 }
396
397 /* Second, disable RX DMA. */
398 writel(0, gp->regs + RXDMA_CFG);
399 for (limit = 0; limit < 5000; limit++) {
400 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
401 break;
402 udelay(10);
403 }
404 if (limit == 5000) {
405 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
406 "chip.\n", dev->name);
407 return 1;
408 }
409
410 udelay(5000);
411
412 /* Execute RX reset command. */
413 writel(gp->swrst_base | GREG_SWRST_RXRST,
414 gp->regs + GREG_SWRST);
415 for (limit = 0; limit < 5000; limit++) {
416 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
417 break;
418 udelay(10);
419 }
420 if (limit == 5000) {
421 printk(KERN_ERR "%s: RX reset command will not execute, resetting "
422 "whole chip.\n", dev->name);
423 return 1;
424 }
425
426 /* Refresh the RX ring. */
427 for (i = 0; i < RX_RING_SIZE; i++) {
428 struct gem_rxd *rxd = &gp->init_block->rxd[i];
429
430 if (gp->rx_skbs[i] == NULL) {
431 printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
432 "whole chip.\n", dev->name);
433 return 1;
434 }
435
436 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
437 }
438 gp->rx_new = gp->rx_old = 0;
439
440 /* Now we must reprogram the rest of RX unit. */
441 desc_dma = (u64) gp->gblock_dvma;
442 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
443 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
444 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
445 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
446 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
447 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
448 writel(val, gp->regs + RXDMA_CFG);
449 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
450 writel(((5 & RXDMA_BLANK_IPKTS) |
451 ((8 << 12) & RXDMA_BLANK_ITIME)),
452 gp->regs + RXDMA_BLANK);
453 else
454 writel(((5 & RXDMA_BLANK_IPKTS) |
455 ((4 << 12) & RXDMA_BLANK_ITIME)),
456 gp->regs + RXDMA_BLANK);
457 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
458 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
459 writel(val, gp->regs + RXDMA_PTHRESH);
460 val = readl(gp->regs + RXDMA_CFG);
461 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
462 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
463 val = readl(gp->regs + MAC_RXCFG);
464 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
465
466 return 0;
467 }
468
469 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
470 {
471 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
472 int ret = 0;
473
474 if (netif_msg_intr(gp))
475 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
476 gp->dev->name, rxmac_stat);
477
478 if (rxmac_stat & MAC_RXSTAT_OFLW) {
479 u32 smac = readl(gp->regs + MAC_SMACHINE);
480
481 printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
482 dev->name, smac);
483 gp->net_stats.rx_over_errors++;
484 gp->net_stats.rx_fifo_errors++;
485
486 ret = gem_rxmac_reset(gp);
487 }
488
489 if (rxmac_stat & MAC_RXSTAT_ACE)
490 gp->net_stats.rx_frame_errors += 0x10000;
491
492 if (rxmac_stat & MAC_RXSTAT_CCE)
493 gp->net_stats.rx_crc_errors += 0x10000;
494
495 if (rxmac_stat & MAC_RXSTAT_LCE)
496 gp->net_stats.rx_length_errors += 0x10000;
497
498 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
499 * events.
500 */
501 return ret;
502 }
503
504 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
505 {
506 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
507
508 if (netif_msg_intr(gp))
509 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
510 gp->dev->name, mac_cstat);
511
512 /* This interrupt is just for pause frame and pause
513 * tracking. It is useful for diagnostics and debug
514 * but probably by default we will mask these events.
515 */
516 if (mac_cstat & MAC_CSTAT_PS)
517 gp->pause_entered++;
518
519 if (mac_cstat & MAC_CSTAT_PRCV)
520 gp->pause_last_time_recvd = (mac_cstat >> 16);
521
522 return 0;
523 }
524
525 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
526 {
527 u32 mif_status = readl(gp->regs + MIF_STATUS);
528 u32 reg_val, changed_bits;
529
530 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
531 changed_bits = (mif_status & MIF_STATUS_STAT);
532
533 gem_handle_mif_event(gp, reg_val, changed_bits);
534
535 return 0;
536 }
537
538 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
539 {
540 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
541
542 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
543 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
544 printk(KERN_ERR "%s: PCI error [%04x] ",
545 dev->name, pci_estat);
546
547 if (pci_estat & GREG_PCIESTAT_BADACK)
548 printk("<No ACK64# during ABS64 cycle> ");
549 if (pci_estat & GREG_PCIESTAT_DTRTO)
550 printk("<Delayed transaction timeout> ");
551 if (pci_estat & GREG_PCIESTAT_OTHER)
552 printk("<other>");
553 printk("\n");
554 } else {
555 pci_estat |= GREG_PCIESTAT_OTHER;
556 printk(KERN_ERR "%s: PCI error\n", dev->name);
557 }
558
559 if (pci_estat & GREG_PCIESTAT_OTHER) {
560 u16 pci_cfg_stat;
561
562 /* Interrogate PCI config space for the
563 * true cause.
564 */
565 pci_read_config_word(gp->pdev, PCI_STATUS,
566 &pci_cfg_stat);
567 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
568 dev->name, pci_cfg_stat);
569 if (pci_cfg_stat & PCI_STATUS_PARITY)
570 printk(KERN_ERR "%s: PCI parity error detected.\n",
571 dev->name);
572 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
573 printk(KERN_ERR "%s: PCI target abort.\n",
574 dev->name);
575 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
576 printk(KERN_ERR "%s: PCI master acks target abort.\n",
577 dev->name);
578 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
579 printk(KERN_ERR "%s: PCI master abort.\n",
580 dev->name);
581 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
582 printk(KERN_ERR "%s: PCI system error SERR#.\n",
583 dev->name);
584 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
585 printk(KERN_ERR "%s: PCI parity error.\n",
586 dev->name);
587
588 /* Write the error bits back to clear them. */
589 pci_cfg_stat &= (PCI_STATUS_PARITY |
590 PCI_STATUS_SIG_TARGET_ABORT |
591 PCI_STATUS_REC_TARGET_ABORT |
592 PCI_STATUS_REC_MASTER_ABORT |
593 PCI_STATUS_SIG_SYSTEM_ERROR |
594 PCI_STATUS_DETECTED_PARITY);
595 pci_write_config_word(gp->pdev,
596 PCI_STATUS, pci_cfg_stat);
597 }
598
599 /* For all PCI errors, we should reset the chip. */
600 return 1;
601 }
602
603 /* All non-normal interrupt conditions get serviced here.
604 * Returns non-zero if we should just exit the interrupt
605 * handler right now (ie. if we reset the card which invalidates
606 * all of the other original irq status bits).
607 */
608 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
609 {
610 if (gem_status & GREG_STAT_RXNOBUF) {
611 /* Frame arrived, no free RX buffers available. */
612 if (netif_msg_rx_err(gp))
613 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
614 gp->dev->name);
615 gp->net_stats.rx_dropped++;
616 }
617
618 if (gem_status & GREG_STAT_RXTAGERR) {
619 /* corrupt RX tag framing */
620 if (netif_msg_rx_err(gp))
621 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
622 gp->dev->name);
623 gp->net_stats.rx_errors++;
624
625 goto do_reset;
626 }
627
628 if (gem_status & GREG_STAT_PCS) {
629 if (gem_pcs_interrupt(dev, gp, gem_status))
630 goto do_reset;
631 }
632
633 if (gem_status & GREG_STAT_TXMAC) {
634 if (gem_txmac_interrupt(dev, gp, gem_status))
635 goto do_reset;
636 }
637
638 if (gem_status & GREG_STAT_RXMAC) {
639 if (gem_rxmac_interrupt(dev, gp, gem_status))
640 goto do_reset;
641 }
642
643 if (gem_status & GREG_STAT_MAC) {
644 if (gem_mac_interrupt(dev, gp, gem_status))
645 goto do_reset;
646 }
647
648 if (gem_status & GREG_STAT_MIF) {
649 if (gem_mif_interrupt(dev, gp, gem_status))
650 goto do_reset;
651 }
652
653 if (gem_status & GREG_STAT_PCIERR) {
654 if (gem_pci_interrupt(dev, gp, gem_status))
655 goto do_reset;
656 }
657
658 return 0;
659
660 do_reset:
661 gp->reset_task_pending = 1;
662 schedule_work(&gp->reset_task);
663
664 return 1;
665 }
666
667 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
668 {
669 int entry, limit;
670
671 if (netif_msg_intr(gp))
672 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
673 gp->dev->name, gem_status);
674
675 entry = gp->tx_old;
676 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
677 while (entry != limit) {
678 struct sk_buff *skb;
679 struct gem_txd *txd;
680 dma_addr_t dma_addr;
681 u32 dma_len;
682 int frag;
683
684 if (netif_msg_tx_done(gp))
685 printk(KERN_DEBUG "%s: tx done, slot %d\n",
686 gp->dev->name, entry);
687 skb = gp->tx_skbs[entry];
688 if (skb_shinfo(skb)->nr_frags) {
689 int last = entry + skb_shinfo(skb)->nr_frags;
690 int walk = entry;
691 int incomplete = 0;
692
693 last &= (TX_RING_SIZE - 1);
694 for (;;) {
695 walk = NEXT_TX(walk);
696 if (walk == limit)
697 incomplete = 1;
698 if (walk == last)
699 break;
700 }
701 if (incomplete)
702 break;
703 }
704 gp->tx_skbs[entry] = NULL;
705 gp->net_stats.tx_bytes += skb->len;
706
707 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
708 txd = &gp->init_block->txd[entry];
709
710 dma_addr = le64_to_cpu(txd->buffer);
711 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
712
713 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
714 entry = NEXT_TX(entry);
715 }
716
717 gp->net_stats.tx_packets++;
718 dev_kfree_skb_irq(skb);
719 }
720 gp->tx_old = entry;
721
722 if (netif_queue_stopped(dev) &&
723 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
724 netif_wake_queue(dev);
725 }
726
727 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
728 {
729 int cluster_start, curr, count, kick;
730
731 cluster_start = curr = (gp->rx_new & ~(4 - 1));
732 count = 0;
733 kick = -1;
734 wmb();
735 while (curr != limit) {
736 curr = NEXT_RX(curr);
737 if (++count == 4) {
738 struct gem_rxd *rxd =
739 &gp->init_block->rxd[cluster_start];
740 for (;;) {
741 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
742 rxd++;
743 cluster_start = NEXT_RX(cluster_start);
744 if (cluster_start == curr)
745 break;
746 }
747 kick = curr;
748 count = 0;
749 }
750 }
751 if (kick >= 0) {
752 mb();
753 writel(kick, gp->regs + RXDMA_KICK);
754 }
755 }
756
757 static int gem_rx(struct gem *gp, int work_to_do)
758 {
759 int entry, drops, work_done = 0;
760 u32 done;
761 __sum16 csum;
762
763 if (netif_msg_rx_status(gp))
764 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
765 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
766
767 entry = gp->rx_new;
768 drops = 0;
769 done = readl(gp->regs + RXDMA_DONE);
770 for (;;) {
771 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
772 struct sk_buff *skb;
773 u64 status = le64_to_cpu(rxd->status_word);
774 dma_addr_t dma_addr;
775 int len;
776
777 if ((status & RXDCTRL_OWN) != 0)
778 break;
779
780 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
781 break;
782
783 /* When writing back RX descriptor, GEM writes status
784 * then buffer address, possibly in seperate transactions.
785 * If we don't wait for the chip to write both, we could
786 * post a new buffer to this descriptor then have GEM spam
787 * on the buffer address. We sync on the RX completion
788 * register to prevent this from happening.
789 */
790 if (entry == done) {
791 done = readl(gp->regs + RXDMA_DONE);
792 if (entry == done)
793 break;
794 }
795
796 /* We can now account for the work we're about to do */
797 work_done++;
798
799 skb = gp->rx_skbs[entry];
800
801 len = (status & RXDCTRL_BUFSZ) >> 16;
802 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
803 gp->net_stats.rx_errors++;
804 if (len < ETH_ZLEN)
805 gp->net_stats.rx_length_errors++;
806 if (len & RXDCTRL_BAD)
807 gp->net_stats.rx_crc_errors++;
808
809 /* We'll just return it to GEM. */
810 drop_it:
811 gp->net_stats.rx_dropped++;
812 goto next;
813 }
814
815 dma_addr = le64_to_cpu(rxd->buffer);
816 if (len > RX_COPY_THRESHOLD) {
817 struct sk_buff *new_skb;
818
819 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
820 if (new_skb == NULL) {
821 drops++;
822 goto drop_it;
823 }
824 pci_unmap_page(gp->pdev, dma_addr,
825 RX_BUF_ALLOC_SIZE(gp),
826 PCI_DMA_FROMDEVICE);
827 gp->rx_skbs[entry] = new_skb;
828 new_skb->dev = gp->dev;
829 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
830 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
831 virt_to_page(new_skb->data),
832 offset_in_page(new_skb->data),
833 RX_BUF_ALLOC_SIZE(gp),
834 PCI_DMA_FROMDEVICE));
835 skb_reserve(new_skb, RX_OFFSET);
836
837 /* Trim the original skb for the netif. */
838 skb_trim(skb, len);
839 } else {
840 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
841
842 if (copy_skb == NULL) {
843 drops++;
844 goto drop_it;
845 }
846
847 skb_reserve(copy_skb, 2);
848 skb_put(copy_skb, len);
849 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
850 skb_copy_from_linear_data(skb, copy_skb->data, len);
851 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
852
853 /* We'll reuse the original ring buffer. */
854 skb = copy_skb;
855 }
856
857 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
858 skb->csum = csum_unfold(csum);
859 skb->ip_summed = CHECKSUM_COMPLETE;
860 skb->protocol = eth_type_trans(skb, gp->dev);
861
862 netif_receive_skb(skb);
863
864 gp->net_stats.rx_packets++;
865 gp->net_stats.rx_bytes += len;
866
867 next:
868 entry = NEXT_RX(entry);
869 }
870
871 gem_post_rxds(gp, entry);
872
873 gp->rx_new = entry;
874
875 if (drops)
876 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
877 gp->dev->name);
878
879 return work_done;
880 }
881
882 static int gem_poll(struct napi_struct *napi, int budget)
883 {
884 struct gem *gp = container_of(napi, struct gem, napi);
885 struct net_device *dev = gp->dev;
886 unsigned long flags;
887 int work_done;
888
889 /*
890 * NAPI locking nightmare: See comment at head of driver
891 */
892 spin_lock_irqsave(&gp->lock, flags);
893
894 work_done = 0;
895 do {
896 /* Handle anomalies */
897 if (gp->status & GREG_STAT_ABNORMAL) {
898 if (gem_abnormal_irq(dev, gp, gp->status))
899 break;
900 }
901
902 /* Run TX completion thread */
903 spin_lock(&gp->tx_lock);
904 gem_tx(dev, gp, gp->status);
905 spin_unlock(&gp->tx_lock);
906
907 spin_unlock_irqrestore(&gp->lock, flags);
908
909 /* Run RX thread. We don't use any locking here,
910 * code willing to do bad things - like cleaning the
911 * rx ring - must call napi_disable(), which
912 * schedule_timeout()'s if polling is already disabled.
913 */
914 work_done += gem_rx(gp, budget - work_done);
915
916 if (work_done >= budget)
917 return work_done;
918
919 spin_lock_irqsave(&gp->lock, flags);
920
921 gp->status = readl(gp->regs + GREG_STAT);
922 } while (gp->status & GREG_STAT_NAPI);
923
924 __netif_rx_complete(napi);
925 gem_enable_ints(gp);
926
927 spin_unlock_irqrestore(&gp->lock, flags);
928
929 return work_done;
930 }
931
932 static irqreturn_t gem_interrupt(int irq, void *dev_id)
933 {
934 struct net_device *dev = dev_id;
935 struct gem *gp = netdev_priv(dev);
936 unsigned long flags;
937
938 /* Swallow interrupts when shutting the chip down, though
939 * that shouldn't happen, we should have done free_irq() at
940 * this point...
941 */
942 if (!gp->running)
943 return IRQ_HANDLED;
944
945 spin_lock_irqsave(&gp->lock, flags);
946
947 if (netif_rx_schedule_prep(&gp->napi)) {
948 u32 gem_status = readl(gp->regs + GREG_STAT);
949
950 if (gem_status == 0) {
951 napi_enable(&gp->napi);
952 spin_unlock_irqrestore(&gp->lock, flags);
953 return IRQ_NONE;
954 }
955 gp->status = gem_status;
956 gem_disable_ints(gp);
957 __netif_rx_schedule(&gp->napi);
958 }
959
960 spin_unlock_irqrestore(&gp->lock, flags);
961
962 /* If polling was disabled at the time we received that
963 * interrupt, we may return IRQ_HANDLED here while we
964 * should return IRQ_NONE. No big deal...
965 */
966 return IRQ_HANDLED;
967 }
968
969 #ifdef CONFIG_NET_POLL_CONTROLLER
970 static void gem_poll_controller(struct net_device *dev)
971 {
972 /* gem_interrupt is safe to reentrance so no need
973 * to disable_irq here.
974 */
975 gem_interrupt(dev->irq, dev);
976 }
977 #endif
978
979 static void gem_tx_timeout(struct net_device *dev)
980 {
981 struct gem *gp = netdev_priv(dev);
982
983 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
984 if (!gp->running) {
985 printk("%s: hrm.. hw not running !\n", dev->name);
986 return;
987 }
988 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
989 dev->name,
990 readl(gp->regs + TXDMA_CFG),
991 readl(gp->regs + MAC_TXSTAT),
992 readl(gp->regs + MAC_TXCFG));
993 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
994 dev->name,
995 readl(gp->regs + RXDMA_CFG),
996 readl(gp->regs + MAC_RXSTAT),
997 readl(gp->regs + MAC_RXCFG));
998
999 spin_lock_irq(&gp->lock);
1000 spin_lock(&gp->tx_lock);
1001
1002 gp->reset_task_pending = 1;
1003 schedule_work(&gp->reset_task);
1004
1005 spin_unlock(&gp->tx_lock);
1006 spin_unlock_irq(&gp->lock);
1007 }
1008
1009 static __inline__ int gem_intme(int entry)
1010 {
1011 /* Algorithm: IRQ every 1/2 of descriptors. */
1012 if (!(entry & ((TX_RING_SIZE>>1)-1)))
1013 return 1;
1014
1015 return 0;
1016 }
1017
1018 static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
1019 {
1020 struct gem *gp = netdev_priv(dev);
1021 int entry;
1022 u64 ctrl;
1023 unsigned long flags;
1024
1025 ctrl = 0;
1026 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1027 const u64 csum_start_off = skb_transport_offset(skb);
1028 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1029
1030 ctrl = (TXDCTRL_CENAB |
1031 (csum_start_off << 15) |
1032 (csum_stuff_off << 21));
1033 }
1034
1035 spin_lock_irqsave(&gp->tx_lock, flags);
1036
1037 /* We raced with gem_do_stop() */
1038 if (!gp->running) {
1039 spin_unlock_irqrestore(&gp->tx_lock, flags);
1040 return NETDEV_TX_BUSY;
1041 }
1042
1043 /* This is a hard error, log it. */
1044 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
1045 netif_stop_queue(dev);
1046 spin_unlock_irqrestore(&gp->tx_lock, flags);
1047 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
1048 dev->name);
1049 return NETDEV_TX_BUSY;
1050 }
1051
1052 entry = gp->tx_new;
1053 gp->tx_skbs[entry] = skb;
1054
1055 if (skb_shinfo(skb)->nr_frags == 0) {
1056 struct gem_txd *txd = &gp->init_block->txd[entry];
1057 dma_addr_t mapping;
1058 u32 len;
1059
1060 len = skb->len;
1061 mapping = pci_map_page(gp->pdev,
1062 virt_to_page(skb->data),
1063 offset_in_page(skb->data),
1064 len, PCI_DMA_TODEVICE);
1065 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1066 if (gem_intme(entry))
1067 ctrl |= TXDCTRL_INTME;
1068 txd->buffer = cpu_to_le64(mapping);
1069 wmb();
1070 txd->control_word = cpu_to_le64(ctrl);
1071 entry = NEXT_TX(entry);
1072 } else {
1073 struct gem_txd *txd;
1074 u32 first_len;
1075 u64 intme;
1076 dma_addr_t first_mapping;
1077 int frag, first_entry = entry;
1078
1079 intme = 0;
1080 if (gem_intme(entry))
1081 intme |= TXDCTRL_INTME;
1082
1083 /* We must give this initial chunk to the device last.
1084 * Otherwise we could race with the device.
1085 */
1086 first_len = skb_headlen(skb);
1087 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1088 offset_in_page(skb->data),
1089 first_len, PCI_DMA_TODEVICE);
1090 entry = NEXT_TX(entry);
1091
1092 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1093 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1094 u32 len;
1095 dma_addr_t mapping;
1096 u64 this_ctrl;
1097
1098 len = this_frag->size;
1099 mapping = pci_map_page(gp->pdev,
1100 this_frag->page,
1101 this_frag->page_offset,
1102 len, PCI_DMA_TODEVICE);
1103 this_ctrl = ctrl;
1104 if (frag == skb_shinfo(skb)->nr_frags - 1)
1105 this_ctrl |= TXDCTRL_EOF;
1106
1107 txd = &gp->init_block->txd[entry];
1108 txd->buffer = cpu_to_le64(mapping);
1109 wmb();
1110 txd->control_word = cpu_to_le64(this_ctrl | len);
1111
1112 if (gem_intme(entry))
1113 intme |= TXDCTRL_INTME;
1114
1115 entry = NEXT_TX(entry);
1116 }
1117 txd = &gp->init_block->txd[first_entry];
1118 txd->buffer = cpu_to_le64(first_mapping);
1119 wmb();
1120 txd->control_word =
1121 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1122 }
1123
1124 gp->tx_new = entry;
1125 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
1126 netif_stop_queue(dev);
1127
1128 if (netif_msg_tx_queued(gp))
1129 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1130 dev->name, entry, skb->len);
1131 mb();
1132 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1133 spin_unlock_irqrestore(&gp->tx_lock, flags);
1134
1135 dev->trans_start = jiffies;
1136
1137 return NETDEV_TX_OK;
1138 }
1139
1140 static void gem_pcs_reset(struct gem *gp)
1141 {
1142 int limit;
1143 u32 val;
1144
1145 /* Reset PCS unit. */
1146 val = readl(gp->regs + PCS_MIICTRL);
1147 val |= PCS_MIICTRL_RST;
1148 writel(val, gp->regs + PCS_MIICTRL);
1149
1150 limit = 32;
1151 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1152 udelay(100);
1153 if (limit-- <= 0)
1154 break;
1155 }
1156 if (limit < 0)
1157 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1158 gp->dev->name);
1159 }
1160
1161 static void gem_pcs_reinit_adv(struct gem *gp)
1162 {
1163 u32 val;
1164
1165 /* Make sure PCS is disabled while changing advertisement
1166 * configuration.
1167 */
1168 val = readl(gp->regs + PCS_CFG);
1169 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1170 writel(val, gp->regs + PCS_CFG);
1171
1172 /* Advertise all capabilities except assymetric
1173 * pause.
1174 */
1175 val = readl(gp->regs + PCS_MIIADV);
1176 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1177 PCS_MIIADV_SP | PCS_MIIADV_AP);
1178 writel(val, gp->regs + PCS_MIIADV);
1179
1180 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1181 * and re-enable PCS.
1182 */
1183 val = readl(gp->regs + PCS_MIICTRL);
1184 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1185 val &= ~PCS_MIICTRL_WB;
1186 writel(val, gp->regs + PCS_MIICTRL);
1187
1188 val = readl(gp->regs + PCS_CFG);
1189 val |= PCS_CFG_ENABLE;
1190 writel(val, gp->regs + PCS_CFG);
1191
1192 /* Make sure serialink loopback is off. The meaning
1193 * of this bit is logically inverted based upon whether
1194 * you are in Serialink or SERDES mode.
1195 */
1196 val = readl(gp->regs + PCS_SCTRL);
1197 if (gp->phy_type == phy_serialink)
1198 val &= ~PCS_SCTRL_LOOP;
1199 else
1200 val |= PCS_SCTRL_LOOP;
1201 writel(val, gp->regs + PCS_SCTRL);
1202 }
1203
1204 #define STOP_TRIES 32
1205
1206 /* Must be invoked under gp->lock and gp->tx_lock. */
1207 static void gem_reset(struct gem *gp)
1208 {
1209 int limit;
1210 u32 val;
1211
1212 /* Make sure we won't get any more interrupts */
1213 writel(0xffffffff, gp->regs + GREG_IMASK);
1214
1215 /* Reset the chip */
1216 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1217 gp->regs + GREG_SWRST);
1218
1219 limit = STOP_TRIES;
1220
1221 do {
1222 udelay(20);
1223 val = readl(gp->regs + GREG_SWRST);
1224 if (limit-- <= 0)
1225 break;
1226 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1227
1228 if (limit < 0)
1229 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
1230
1231 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1232 gem_pcs_reinit_adv(gp);
1233 }
1234
1235 /* Must be invoked under gp->lock and gp->tx_lock. */
1236 static void gem_start_dma(struct gem *gp)
1237 {
1238 u32 val;
1239
1240 /* We are ready to rock, turn everything on. */
1241 val = readl(gp->regs + TXDMA_CFG);
1242 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1243 val = readl(gp->regs + RXDMA_CFG);
1244 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1245 val = readl(gp->regs + MAC_TXCFG);
1246 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1247 val = readl(gp->regs + MAC_RXCFG);
1248 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1249
1250 (void) readl(gp->regs + MAC_RXCFG);
1251 udelay(100);
1252
1253 gem_enable_ints(gp);
1254
1255 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1256 }
1257
1258 /* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
1259 * actually stopped before about 4ms tho ...
1260 */
1261 static void gem_stop_dma(struct gem *gp)
1262 {
1263 u32 val;
1264
1265 /* We are done rocking, turn everything off. */
1266 val = readl(gp->regs + TXDMA_CFG);
1267 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1268 val = readl(gp->regs + RXDMA_CFG);
1269 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1270 val = readl(gp->regs + MAC_TXCFG);
1271 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1272 val = readl(gp->regs + MAC_RXCFG);
1273 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1274
1275 (void) readl(gp->regs + MAC_RXCFG);
1276
1277 /* Need to wait a bit ... done by the caller */
1278 }
1279
1280
1281 /* Must be invoked under gp->lock and gp->tx_lock. */
1282 // XXX dbl check what that function should do when called on PCS PHY
1283 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1284 {
1285 u32 advertise, features;
1286 int autoneg;
1287 int speed;
1288 int duplex;
1289
1290 if (gp->phy_type != phy_mii_mdio0 &&
1291 gp->phy_type != phy_mii_mdio1)
1292 goto non_mii;
1293
1294 /* Setup advertise */
1295 if (found_mii_phy(gp))
1296 features = gp->phy_mii.def->features;
1297 else
1298 features = 0;
1299
1300 advertise = features & ADVERTISE_MASK;
1301 if (gp->phy_mii.advertising != 0)
1302 advertise &= gp->phy_mii.advertising;
1303
1304 autoneg = gp->want_autoneg;
1305 speed = gp->phy_mii.speed;
1306 duplex = gp->phy_mii.duplex;
1307
1308 /* Setup link parameters */
1309 if (!ep)
1310 goto start_aneg;
1311 if (ep->autoneg == AUTONEG_ENABLE) {
1312 advertise = ep->advertising;
1313 autoneg = 1;
1314 } else {
1315 autoneg = 0;
1316 speed = ep->speed;
1317 duplex = ep->duplex;
1318 }
1319
1320 start_aneg:
1321 /* Sanitize settings based on PHY capabilities */
1322 if ((features & SUPPORTED_Autoneg) == 0)
1323 autoneg = 0;
1324 if (speed == SPEED_1000 &&
1325 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1326 speed = SPEED_100;
1327 if (speed == SPEED_100 &&
1328 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1329 speed = SPEED_10;
1330 if (duplex == DUPLEX_FULL &&
1331 !(features & (SUPPORTED_1000baseT_Full |
1332 SUPPORTED_100baseT_Full |
1333 SUPPORTED_10baseT_Full)))
1334 duplex = DUPLEX_HALF;
1335 if (speed == 0)
1336 speed = SPEED_10;
1337
1338 /* If we are asleep, we don't try to actually setup the PHY, we
1339 * just store the settings
1340 */
1341 if (gp->asleep) {
1342 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1343 gp->phy_mii.speed = speed;
1344 gp->phy_mii.duplex = duplex;
1345 return;
1346 }
1347
1348 /* Configure PHY & start aneg */
1349 gp->want_autoneg = autoneg;
1350 if (autoneg) {
1351 if (found_mii_phy(gp))
1352 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1353 gp->lstate = link_aneg;
1354 } else {
1355 if (found_mii_phy(gp))
1356 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1357 gp->lstate = link_force_ok;
1358 }
1359
1360 non_mii:
1361 gp->timer_ticks = 0;
1362 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1363 }
1364
1365 /* A link-up condition has occurred, initialize and enable the
1366 * rest of the chip.
1367 *
1368 * Must be invoked under gp->lock and gp->tx_lock.
1369 */
1370 static int gem_set_link_modes(struct gem *gp)
1371 {
1372 u32 val;
1373 int full_duplex, speed, pause;
1374
1375 full_duplex = 0;
1376 speed = SPEED_10;
1377 pause = 0;
1378
1379 if (found_mii_phy(gp)) {
1380 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1381 return 1;
1382 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1383 speed = gp->phy_mii.speed;
1384 pause = gp->phy_mii.pause;
1385 } else if (gp->phy_type == phy_serialink ||
1386 gp->phy_type == phy_serdes) {
1387 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1388
1389 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1390 full_duplex = 1;
1391 speed = SPEED_1000;
1392 }
1393
1394 if (netif_msg_link(gp))
1395 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
1396 gp->dev->name, speed, (full_duplex ? "full" : "half"));
1397
1398 if (!gp->running)
1399 return 0;
1400
1401 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1402 if (full_duplex) {
1403 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1404 } else {
1405 /* MAC_TXCFG_NBO must be zero. */
1406 }
1407 writel(val, gp->regs + MAC_TXCFG);
1408
1409 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1410 if (!full_duplex &&
1411 (gp->phy_type == phy_mii_mdio0 ||
1412 gp->phy_type == phy_mii_mdio1)) {
1413 val |= MAC_XIFCFG_DISE;
1414 } else if (full_duplex) {
1415 val |= MAC_XIFCFG_FLED;
1416 }
1417
1418 if (speed == SPEED_1000)
1419 val |= (MAC_XIFCFG_GMII);
1420
1421 writel(val, gp->regs + MAC_XIFCFG);
1422
1423 /* If gigabit and half-duplex, enable carrier extension
1424 * mode. Else, disable it.
1425 */
1426 if (speed == SPEED_1000 && !full_duplex) {
1427 val = readl(gp->regs + MAC_TXCFG);
1428 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1429
1430 val = readl(gp->regs + MAC_RXCFG);
1431 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1432 } else {
1433 val = readl(gp->regs + MAC_TXCFG);
1434 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1435
1436 val = readl(gp->regs + MAC_RXCFG);
1437 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1438 }
1439
1440 if (gp->phy_type == phy_serialink ||
1441 gp->phy_type == phy_serdes) {
1442 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1443
1444 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1445 pause = 1;
1446 }
1447
1448 if (netif_msg_link(gp)) {
1449 if (pause) {
1450 printk(KERN_INFO "%s: Pause is enabled "
1451 "(rxfifo: %d off: %d on: %d)\n",
1452 gp->dev->name,
1453 gp->rx_fifo_sz,
1454 gp->rx_pause_off,
1455 gp->rx_pause_on);
1456 } else {
1457 printk(KERN_INFO "%s: Pause is disabled\n",
1458 gp->dev->name);
1459 }
1460 }
1461
1462 if (!full_duplex)
1463 writel(512, gp->regs + MAC_STIME);
1464 else
1465 writel(64, gp->regs + MAC_STIME);
1466 val = readl(gp->regs + MAC_MCCFG);
1467 if (pause)
1468 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1469 else
1470 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1471 writel(val, gp->regs + MAC_MCCFG);
1472
1473 gem_start_dma(gp);
1474
1475 return 0;
1476 }
1477
1478 /* Must be invoked under gp->lock and gp->tx_lock. */
1479 static int gem_mdio_link_not_up(struct gem *gp)
1480 {
1481 switch (gp->lstate) {
1482 case link_force_ret:
1483 if (netif_msg_link(gp))
1484 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1485 " forced mode\n", gp->dev->name);
1486 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1487 gp->last_forced_speed, DUPLEX_HALF);
1488 gp->timer_ticks = 5;
1489 gp->lstate = link_force_ok;
1490 return 0;
1491 case link_aneg:
1492 /* We try forced modes after a failed aneg only on PHYs that don't
1493 * have "magic_aneg" bit set, which means they internally do the
1494 * while forced-mode thingy. On these, we just restart aneg
1495 */
1496 if (gp->phy_mii.def->magic_aneg)
1497 return 1;
1498 if (netif_msg_link(gp))
1499 printk(KERN_INFO "%s: switching to forced 100bt\n",
1500 gp->dev->name);
1501 /* Try forced modes. */
1502 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1503 DUPLEX_HALF);
1504 gp->timer_ticks = 5;
1505 gp->lstate = link_force_try;
1506 return 0;
1507 case link_force_try:
1508 /* Downgrade from 100 to 10 Mbps if necessary.
1509 * If already at 10Mbps, warn user about the
1510 * situation every 10 ticks.
1511 */
1512 if (gp->phy_mii.speed == SPEED_100) {
1513 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1514 DUPLEX_HALF);
1515 gp->timer_ticks = 5;
1516 if (netif_msg_link(gp))
1517 printk(KERN_INFO "%s: switching to forced 10bt\n",
1518 gp->dev->name);
1519 return 0;
1520 } else
1521 return 1;
1522 default:
1523 return 0;
1524 }
1525 }
1526
1527 static void gem_link_timer(unsigned long data)
1528 {
1529 struct gem *gp = (struct gem *) data;
1530 int restart_aneg = 0;
1531
1532 if (gp->asleep)
1533 return;
1534
1535 spin_lock_irq(&gp->lock);
1536 spin_lock(&gp->tx_lock);
1537 gem_get_cell(gp);
1538
1539 /* If the reset task is still pending, we just
1540 * reschedule the link timer
1541 */
1542 if (gp->reset_task_pending)
1543 goto restart;
1544
1545 if (gp->phy_type == phy_serialink ||
1546 gp->phy_type == phy_serdes) {
1547 u32 val = readl(gp->regs + PCS_MIISTAT);
1548
1549 if (!(val & PCS_MIISTAT_LS))
1550 val = readl(gp->regs + PCS_MIISTAT);
1551
1552 if ((val & PCS_MIISTAT_LS) != 0) {
1553 if (gp->lstate == link_up)
1554 goto restart;
1555
1556 gp->lstate = link_up;
1557 netif_carrier_on(gp->dev);
1558 (void)gem_set_link_modes(gp);
1559 }
1560 goto restart;
1561 }
1562 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1563 /* Ok, here we got a link. If we had it due to a forced
1564 * fallback, and we were configured for autoneg, we do
1565 * retry a short autoneg pass. If you know your hub is
1566 * broken, use ethtool ;)
1567 */
1568 if (gp->lstate == link_force_try && gp->want_autoneg) {
1569 gp->lstate = link_force_ret;
1570 gp->last_forced_speed = gp->phy_mii.speed;
1571 gp->timer_ticks = 5;
1572 if (netif_msg_link(gp))
1573 printk(KERN_INFO "%s: Got link after fallback, retrying"
1574 " autoneg once...\n", gp->dev->name);
1575 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1576 } else if (gp->lstate != link_up) {
1577 gp->lstate = link_up;
1578 netif_carrier_on(gp->dev);
1579 if (gem_set_link_modes(gp))
1580 restart_aneg = 1;
1581 }
1582 } else {
1583 /* If the link was previously up, we restart the
1584 * whole process
1585 */
1586 if (gp->lstate == link_up) {
1587 gp->lstate = link_down;
1588 if (netif_msg_link(gp))
1589 printk(KERN_INFO "%s: Link down\n",
1590 gp->dev->name);
1591 netif_carrier_off(gp->dev);
1592 gp->reset_task_pending = 1;
1593 schedule_work(&gp->reset_task);
1594 restart_aneg = 1;
1595 } else if (++gp->timer_ticks > 10) {
1596 if (found_mii_phy(gp))
1597 restart_aneg = gem_mdio_link_not_up(gp);
1598 else
1599 restart_aneg = 1;
1600 }
1601 }
1602 if (restart_aneg) {
1603 gem_begin_auto_negotiation(gp, NULL);
1604 goto out_unlock;
1605 }
1606 restart:
1607 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1608 out_unlock:
1609 gem_put_cell(gp);
1610 spin_unlock(&gp->tx_lock);
1611 spin_unlock_irq(&gp->lock);
1612 }
1613
1614 /* Must be invoked under gp->lock and gp->tx_lock. */
1615 static void gem_clean_rings(struct gem *gp)
1616 {
1617 struct gem_init_block *gb = gp->init_block;
1618 struct sk_buff *skb;
1619 int i;
1620 dma_addr_t dma_addr;
1621
1622 for (i = 0; i < RX_RING_SIZE; i++) {
1623 struct gem_rxd *rxd;
1624
1625 rxd = &gb->rxd[i];
1626 if (gp->rx_skbs[i] != NULL) {
1627 skb = gp->rx_skbs[i];
1628 dma_addr = le64_to_cpu(rxd->buffer);
1629 pci_unmap_page(gp->pdev, dma_addr,
1630 RX_BUF_ALLOC_SIZE(gp),
1631 PCI_DMA_FROMDEVICE);
1632 dev_kfree_skb_any(skb);
1633 gp->rx_skbs[i] = NULL;
1634 }
1635 rxd->status_word = 0;
1636 wmb();
1637 rxd->buffer = 0;
1638 }
1639
1640 for (i = 0; i < TX_RING_SIZE; i++) {
1641 if (gp->tx_skbs[i] != NULL) {
1642 struct gem_txd *txd;
1643 int frag;
1644
1645 skb = gp->tx_skbs[i];
1646 gp->tx_skbs[i] = NULL;
1647
1648 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1649 int ent = i & (TX_RING_SIZE - 1);
1650
1651 txd = &gb->txd[ent];
1652 dma_addr = le64_to_cpu(txd->buffer);
1653 pci_unmap_page(gp->pdev, dma_addr,
1654 le64_to_cpu(txd->control_word) &
1655 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1656
1657 if (frag != skb_shinfo(skb)->nr_frags)
1658 i++;
1659 }
1660 dev_kfree_skb_any(skb);
1661 }
1662 }
1663 }
1664
1665 /* Must be invoked under gp->lock and gp->tx_lock. */
1666 static void gem_init_rings(struct gem *gp)
1667 {
1668 struct gem_init_block *gb = gp->init_block;
1669 struct net_device *dev = gp->dev;
1670 int i;
1671 dma_addr_t dma_addr;
1672
1673 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1674
1675 gem_clean_rings(gp);
1676
1677 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1678 (unsigned)VLAN_ETH_FRAME_LEN);
1679
1680 for (i = 0; i < RX_RING_SIZE; i++) {
1681 struct sk_buff *skb;
1682 struct gem_rxd *rxd = &gb->rxd[i];
1683
1684 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1685 if (!skb) {
1686 rxd->buffer = 0;
1687 rxd->status_word = 0;
1688 continue;
1689 }
1690
1691 gp->rx_skbs[i] = skb;
1692 skb->dev = dev;
1693 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1694 dma_addr = pci_map_page(gp->pdev,
1695 virt_to_page(skb->data),
1696 offset_in_page(skb->data),
1697 RX_BUF_ALLOC_SIZE(gp),
1698 PCI_DMA_FROMDEVICE);
1699 rxd->buffer = cpu_to_le64(dma_addr);
1700 wmb();
1701 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1702 skb_reserve(skb, RX_OFFSET);
1703 }
1704
1705 for (i = 0; i < TX_RING_SIZE; i++) {
1706 struct gem_txd *txd = &gb->txd[i];
1707
1708 txd->control_word = 0;
1709 wmb();
1710 txd->buffer = 0;
1711 }
1712 wmb();
1713 }
1714
1715 /* Init PHY interface and start link poll state machine */
1716 static void gem_init_phy(struct gem *gp)
1717 {
1718 u32 mifcfg;
1719
1720 /* Revert MIF CFG setting done on stop_phy */
1721 mifcfg = readl(gp->regs + MIF_CFG);
1722 mifcfg &= ~MIF_CFG_BBMODE;
1723 writel(mifcfg, gp->regs + MIF_CFG);
1724
1725 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1726 int i;
1727
1728 /* Those delay sucks, the HW seem to love them though, I'll
1729 * serisouly consider breaking some locks here to be able
1730 * to schedule instead
1731 */
1732 for (i = 0; i < 3; i++) {
1733 #ifdef CONFIG_PPC_PMAC
1734 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1735 msleep(20);
1736 #endif
1737 /* Some PHYs used by apple have problem getting back to us,
1738 * we do an additional reset here
1739 */
1740 phy_write(gp, MII_BMCR, BMCR_RESET);
1741 msleep(20);
1742 if (phy_read(gp, MII_BMCR) != 0xffff)
1743 break;
1744 if (i == 2)
1745 printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
1746 gp->dev->name);
1747 }
1748 }
1749
1750 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1751 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1752 u32 val;
1753
1754 /* Init datapath mode register. */
1755 if (gp->phy_type == phy_mii_mdio0 ||
1756 gp->phy_type == phy_mii_mdio1) {
1757 val = PCS_DMODE_MGM;
1758 } else if (gp->phy_type == phy_serialink) {
1759 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1760 } else {
1761 val = PCS_DMODE_ESM;
1762 }
1763
1764 writel(val, gp->regs + PCS_DMODE);
1765 }
1766
1767 if (gp->phy_type == phy_mii_mdio0 ||
1768 gp->phy_type == phy_mii_mdio1) {
1769 // XXX check for errors
1770 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1771
1772 /* Init PHY */
1773 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1774 gp->phy_mii.def->ops->init(&gp->phy_mii);
1775 } else {
1776 gem_pcs_reset(gp);
1777 gem_pcs_reinit_adv(gp);
1778 }
1779
1780 /* Default aneg parameters */
1781 gp->timer_ticks = 0;
1782 gp->lstate = link_down;
1783 netif_carrier_off(gp->dev);
1784
1785 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1786 spin_lock_irq(&gp->lock);
1787 gem_begin_auto_negotiation(gp, NULL);
1788 spin_unlock_irq(&gp->lock);
1789 }
1790
1791 /* Must be invoked under gp->lock and gp->tx_lock. */
1792 static void gem_init_dma(struct gem *gp)
1793 {
1794 u64 desc_dma = (u64) gp->gblock_dvma;
1795 u32 val;
1796
1797 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1798 writel(val, gp->regs + TXDMA_CFG);
1799
1800 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1801 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1802 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1803
1804 writel(0, gp->regs + TXDMA_KICK);
1805
1806 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1807 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1808 writel(val, gp->regs + RXDMA_CFG);
1809
1810 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1811 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1812
1813 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1814
1815 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1816 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1817 writel(val, gp->regs + RXDMA_PTHRESH);
1818
1819 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1820 writel(((5 & RXDMA_BLANK_IPKTS) |
1821 ((8 << 12) & RXDMA_BLANK_ITIME)),
1822 gp->regs + RXDMA_BLANK);
1823 else
1824 writel(((5 & RXDMA_BLANK_IPKTS) |
1825 ((4 << 12) & RXDMA_BLANK_ITIME)),
1826 gp->regs + RXDMA_BLANK);
1827 }
1828
1829 /* Must be invoked under gp->lock and gp->tx_lock. */
1830 static u32 gem_setup_multicast(struct gem *gp)
1831 {
1832 u32 rxcfg = 0;
1833 int i;
1834
1835 if ((gp->dev->flags & IFF_ALLMULTI) ||
1836 (gp->dev->mc_count > 256)) {
1837 for (i=0; i<16; i++)
1838 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1839 rxcfg |= MAC_RXCFG_HFE;
1840 } else if (gp->dev->flags & IFF_PROMISC) {
1841 rxcfg |= MAC_RXCFG_PROM;
1842 } else {
1843 u16 hash_table[16];
1844 u32 crc;
1845 struct dev_mc_list *dmi = gp->dev->mc_list;
1846 int i;
1847
1848 for (i = 0; i < 16; i++)
1849 hash_table[i] = 0;
1850
1851 for (i = 0; i < gp->dev->mc_count; i++) {
1852 char *addrs = dmi->dmi_addr;
1853
1854 dmi = dmi->next;
1855
1856 if (!(*addrs & 1))
1857 continue;
1858
1859 crc = ether_crc_le(6, addrs);
1860 crc >>= 24;
1861 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1862 }
1863 for (i=0; i<16; i++)
1864 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1865 rxcfg |= MAC_RXCFG_HFE;
1866 }
1867
1868 return rxcfg;
1869 }
1870
1871 /* Must be invoked under gp->lock and gp->tx_lock. */
1872 static void gem_init_mac(struct gem *gp)
1873 {
1874 unsigned char *e = &gp->dev->dev_addr[0];
1875
1876 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1877
1878 writel(0x00, gp->regs + MAC_IPG0);
1879 writel(0x08, gp->regs + MAC_IPG1);
1880 writel(0x04, gp->regs + MAC_IPG2);
1881 writel(0x40, gp->regs + MAC_STIME);
1882 writel(0x40, gp->regs + MAC_MINFSZ);
1883
1884 /* Ethernet payload + header + FCS + optional VLAN tag. */
1885 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1886
1887 writel(0x07, gp->regs + MAC_PASIZE);
1888 writel(0x04, gp->regs + MAC_JAMSIZE);
1889 writel(0x10, gp->regs + MAC_ATTLIM);
1890 writel(0x8808, gp->regs + MAC_MCTYPE);
1891
1892 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1893
1894 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1895 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1896 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1897
1898 writel(0, gp->regs + MAC_ADDR3);
1899 writel(0, gp->regs + MAC_ADDR4);
1900 writel(0, gp->regs + MAC_ADDR5);
1901
1902 writel(0x0001, gp->regs + MAC_ADDR6);
1903 writel(0xc200, gp->regs + MAC_ADDR7);
1904 writel(0x0180, gp->regs + MAC_ADDR8);
1905
1906 writel(0, gp->regs + MAC_AFILT0);
1907 writel(0, gp->regs + MAC_AFILT1);
1908 writel(0, gp->regs + MAC_AFILT2);
1909 writel(0, gp->regs + MAC_AF21MSK);
1910 writel(0, gp->regs + MAC_AF0MSK);
1911
1912 gp->mac_rx_cfg = gem_setup_multicast(gp);
1913 #ifdef STRIP_FCS
1914 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1915 #endif
1916 writel(0, gp->regs + MAC_NCOLL);
1917 writel(0, gp->regs + MAC_FASUCC);
1918 writel(0, gp->regs + MAC_ECOLL);
1919 writel(0, gp->regs + MAC_LCOLL);
1920 writel(0, gp->regs + MAC_DTIMER);
1921 writel(0, gp->regs + MAC_PATMPS);
1922 writel(0, gp->regs + MAC_RFCTR);
1923 writel(0, gp->regs + MAC_LERR);
1924 writel(0, gp->regs + MAC_AERR);
1925 writel(0, gp->regs + MAC_FCSERR);
1926 writel(0, gp->regs + MAC_RXCVERR);
1927
1928 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1929 * them once a link is established.
1930 */
1931 writel(0, gp->regs + MAC_TXCFG);
1932 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1933 writel(0, gp->regs + MAC_MCCFG);
1934 writel(0, gp->regs + MAC_XIFCFG);
1935
1936 /* Setup MAC interrupts. We want to get all of the interesting
1937 * counter expiration events, but we do not want to hear about
1938 * normal rx/tx as the DMA engine tells us that.
1939 */
1940 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1941 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1942
1943 /* Don't enable even the PAUSE interrupts for now, we
1944 * make no use of those events other than to record them.
1945 */
1946 writel(0xffffffff, gp->regs + MAC_MCMASK);
1947
1948 /* Don't enable GEM's WOL in normal operations
1949 */
1950 if (gp->has_wol)
1951 writel(0, gp->regs + WOL_WAKECSR);
1952 }
1953
1954 /* Must be invoked under gp->lock and gp->tx_lock. */
1955 static void gem_init_pause_thresholds(struct gem *gp)
1956 {
1957 u32 cfg;
1958
1959 /* Calculate pause thresholds. Setting the OFF threshold to the
1960 * full RX fifo size effectively disables PAUSE generation which
1961 * is what we do for 10/100 only GEMs which have FIFOs too small
1962 * to make real gains from PAUSE.
1963 */
1964 if (gp->rx_fifo_sz <= (2 * 1024)) {
1965 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1966 } else {
1967 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1968 int off = (gp->rx_fifo_sz - (max_frame * 2));
1969 int on = off - max_frame;
1970
1971 gp->rx_pause_off = off;
1972 gp->rx_pause_on = on;
1973 }
1974
1975
1976 /* Configure the chip "burst" DMA mode & enable some
1977 * HW bug fixes on Apple version
1978 */
1979 cfg = 0;
1980 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1981 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1982 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1983 cfg |= GREG_CFG_IBURST;
1984 #endif
1985 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1986 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1987 writel(cfg, gp->regs + GREG_CFG);
1988
1989 /* If Infinite Burst didn't stick, then use different
1990 * thresholds (and Apple bug fixes don't exist)
1991 */
1992 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1993 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1994 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1995 writel(cfg, gp->regs + GREG_CFG);
1996 }
1997 }
1998
1999 static int gem_check_invariants(struct gem *gp)
2000 {
2001 struct pci_dev *pdev = gp->pdev;
2002 u32 mif_cfg;
2003
2004 /* On Apple's sungem, we can't rely on registers as the chip
2005 * was been powered down by the firmware. The PHY is looked
2006 * up later on.
2007 */
2008 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
2009 gp->phy_type = phy_mii_mdio0;
2010 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2011 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2012 gp->swrst_base = 0;
2013
2014 mif_cfg = readl(gp->regs + MIF_CFG);
2015 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
2016 mif_cfg |= MIF_CFG_MDI0;
2017 writel(mif_cfg, gp->regs + MIF_CFG);
2018 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
2019 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
2020
2021 /* We hard-code the PHY address so we can properly bring it out of
2022 * reset later on, we can't really probe it at this point, though
2023 * that isn't an issue.
2024 */
2025 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
2026 gp->mii_phy_addr = 1;
2027 else
2028 gp->mii_phy_addr = 0;
2029
2030 return 0;
2031 }
2032
2033 mif_cfg = readl(gp->regs + MIF_CFG);
2034
2035 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2036 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
2037 /* One of the MII PHYs _must_ be present
2038 * as this chip has no gigabit PHY.
2039 */
2040 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
2041 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
2042 mif_cfg);
2043 return -1;
2044 }
2045 }
2046
2047 /* Determine initial PHY interface type guess. MDIO1 is the
2048 * external PHY and thus takes precedence over MDIO0.
2049 */
2050
2051 if (mif_cfg & MIF_CFG_MDI1) {
2052 gp->phy_type = phy_mii_mdio1;
2053 mif_cfg |= MIF_CFG_PSELECT;
2054 writel(mif_cfg, gp->regs + MIF_CFG);
2055 } else if (mif_cfg & MIF_CFG_MDI0) {
2056 gp->phy_type = phy_mii_mdio0;
2057 mif_cfg &= ~MIF_CFG_PSELECT;
2058 writel(mif_cfg, gp->regs + MIF_CFG);
2059 } else {
2060 gp->phy_type = phy_serialink;
2061 }
2062 if (gp->phy_type == phy_mii_mdio1 ||
2063 gp->phy_type == phy_mii_mdio0) {
2064 int i;
2065
2066 for (i = 0; i < 32; i++) {
2067 gp->mii_phy_addr = i;
2068 if (phy_read(gp, MII_BMCR) != 0xffff)
2069 break;
2070 }
2071 if (i == 32) {
2072 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2073 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
2074 return -1;
2075 }
2076 gp->phy_type = phy_serdes;
2077 }
2078 }
2079
2080 /* Fetch the FIFO configurations now too. */
2081 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2082 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2083
2084 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2085 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2086 if (gp->tx_fifo_sz != (9 * 1024) ||
2087 gp->rx_fifo_sz != (20 * 1024)) {
2088 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2089 gp->tx_fifo_sz, gp->rx_fifo_sz);
2090 return -1;
2091 }
2092 gp->swrst_base = 0;
2093 } else {
2094 if (gp->tx_fifo_sz != (2 * 1024) ||
2095 gp->rx_fifo_sz != (2 * 1024)) {
2096 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2097 gp->tx_fifo_sz, gp->rx_fifo_sz);
2098 return -1;
2099 }
2100 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2101 }
2102 }
2103
2104 return 0;
2105 }
2106
2107 /* Must be invoked under gp->lock and gp->tx_lock. */
2108 static void gem_reinit_chip(struct gem *gp)
2109 {
2110 /* Reset the chip */
2111 gem_reset(gp);
2112
2113 /* Make sure ints are disabled */
2114 gem_disable_ints(gp);
2115
2116 /* Allocate & setup ring buffers */
2117 gem_init_rings(gp);
2118
2119 /* Configure pause thresholds */
2120 gem_init_pause_thresholds(gp);
2121
2122 /* Init DMA & MAC engines */
2123 gem_init_dma(gp);
2124 gem_init_mac(gp);
2125 }
2126
2127
2128 /* Must be invoked with no lock held. */
2129 static void gem_stop_phy(struct gem *gp, int wol)
2130 {
2131 u32 mifcfg;
2132 unsigned long flags;
2133
2134 /* Let the chip settle down a bit, it seems that helps
2135 * for sleep mode on some models
2136 */
2137 msleep(10);
2138
2139 /* Make sure we aren't polling PHY status change. We
2140 * don't currently use that feature though
2141 */
2142 mifcfg = readl(gp->regs + MIF_CFG);
2143 mifcfg &= ~MIF_CFG_POLL;
2144 writel(mifcfg, gp->regs + MIF_CFG);
2145
2146 if (wol && gp->has_wol) {
2147 unsigned char *e = &gp->dev->dev_addr[0];
2148 u32 csr;
2149
2150 /* Setup wake-on-lan for MAGIC packet */
2151 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2152 gp->regs + MAC_RXCFG);
2153 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2154 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2155 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2156
2157 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2158 csr = WOL_WAKECSR_ENABLE;
2159 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2160 csr |= WOL_WAKECSR_MII;
2161 writel(csr, gp->regs + WOL_WAKECSR);
2162 } else {
2163 writel(0, gp->regs + MAC_RXCFG);
2164 (void)readl(gp->regs + MAC_RXCFG);
2165 /* Machine sleep will die in strange ways if we
2166 * dont wait a bit here, looks like the chip takes
2167 * some time to really shut down
2168 */
2169 msleep(10);
2170 }
2171
2172 writel(0, gp->regs + MAC_TXCFG);
2173 writel(0, gp->regs + MAC_XIFCFG);
2174 writel(0, gp->regs + TXDMA_CFG);
2175 writel(0, gp->regs + RXDMA_CFG);
2176
2177 if (!wol) {
2178 spin_lock_irqsave(&gp->lock, flags);
2179 spin_lock(&gp->tx_lock);
2180 gem_reset(gp);
2181 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2182 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2183 spin_unlock(&gp->tx_lock);
2184 spin_unlock_irqrestore(&gp->lock, flags);
2185
2186 /* No need to take the lock here */
2187
2188 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2189 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2190
2191 /* According to Apple, we must set the MDIO pins to this begnign
2192 * state or we may 1) eat more current, 2) damage some PHYs
2193 */
2194 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2195 writel(0, gp->regs + MIF_BBCLK);
2196 writel(0, gp->regs + MIF_BBDATA);
2197 writel(0, gp->regs + MIF_BBOENAB);
2198 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2199 (void) readl(gp->regs + MAC_XIFCFG);
2200 }
2201 }
2202
2203
2204 static int gem_do_start(struct net_device *dev)
2205 {
2206 struct gem *gp = netdev_priv(dev);
2207 unsigned long flags;
2208
2209 spin_lock_irqsave(&gp->lock, flags);
2210 spin_lock(&gp->tx_lock);
2211
2212 /* Enable the cell */
2213 gem_get_cell(gp);
2214
2215 /* Init & setup chip hardware */
2216 gem_reinit_chip(gp);
2217
2218 gp->running = 1;
2219
2220 napi_enable(&gp->napi);
2221
2222 if (gp->lstate == link_up) {
2223 netif_carrier_on(gp->dev);
2224 gem_set_link_modes(gp);
2225 }
2226
2227 netif_wake_queue(gp->dev);
2228
2229 spin_unlock(&gp->tx_lock);
2230 spin_unlock_irqrestore(&gp->lock, flags);
2231
2232 if (request_irq(gp->pdev->irq, gem_interrupt,
2233 IRQF_SHARED, dev->name, (void *)dev)) {
2234 printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
2235
2236 spin_lock_irqsave(&gp->lock, flags);
2237 spin_lock(&gp->tx_lock);
2238
2239 napi_disable(&gp->napi);
2240
2241 gp->running = 0;
2242 gem_reset(gp);
2243 gem_clean_rings(gp);
2244 gem_put_cell(gp);
2245
2246 spin_unlock(&gp->tx_lock);
2247 spin_unlock_irqrestore(&gp->lock, flags);
2248
2249 return -EAGAIN;
2250 }
2251
2252 return 0;
2253 }
2254
2255 static void gem_do_stop(struct net_device *dev, int wol)
2256 {
2257 struct gem *gp = netdev_priv(dev);
2258 unsigned long flags;
2259
2260 spin_lock_irqsave(&gp->lock, flags);
2261 spin_lock(&gp->tx_lock);
2262
2263 gp->running = 0;
2264
2265 /* Stop netif queue */
2266 netif_stop_queue(dev);
2267
2268 /* Make sure ints are disabled */
2269 gem_disable_ints(gp);
2270
2271 /* We can drop the lock now */
2272 spin_unlock(&gp->tx_lock);
2273 spin_unlock_irqrestore(&gp->lock, flags);
2274
2275 /* If we are going to sleep with WOL */
2276 gem_stop_dma(gp);
2277 msleep(10);
2278 if (!wol)
2279 gem_reset(gp);
2280 msleep(10);
2281
2282 /* Get rid of rings */
2283 gem_clean_rings(gp);
2284
2285 /* No irq needed anymore */
2286 free_irq(gp->pdev->irq, (void *) dev);
2287
2288 /* Cell not needed neither if no WOL */
2289 if (!wol) {
2290 spin_lock_irqsave(&gp->lock, flags);
2291 gem_put_cell(gp);
2292 spin_unlock_irqrestore(&gp->lock, flags);
2293 }
2294 }
2295
2296 static void gem_reset_task(struct work_struct *work)
2297 {
2298 struct gem *gp = container_of(work, struct gem, reset_task);
2299
2300 mutex_lock(&gp->pm_mutex);
2301
2302 if (gp->opened)
2303 napi_disable(&gp->napi);
2304
2305 spin_lock_irq(&gp->lock);
2306 spin_lock(&gp->tx_lock);
2307
2308 if (gp->running) {
2309 netif_stop_queue(gp->dev);
2310
2311 /* Reset the chip & rings */
2312 gem_reinit_chip(gp);
2313 if (gp->lstate == link_up)
2314 gem_set_link_modes(gp);
2315 netif_wake_queue(gp->dev);
2316 }
2317
2318 gp->reset_task_pending = 0;
2319
2320 spin_unlock(&gp->tx_lock);
2321 spin_unlock_irq(&gp->lock);
2322
2323 if (gp->opened)
2324 napi_enable(&gp->napi);
2325
2326 mutex_unlock(&gp->pm_mutex);
2327 }
2328
2329
2330 static int gem_open(struct net_device *dev)
2331 {
2332 struct gem *gp = netdev_priv(dev);
2333 int rc = 0;
2334
2335 mutex_lock(&gp->pm_mutex);
2336
2337 /* We need the cell enabled */
2338 if (!gp->asleep)
2339 rc = gem_do_start(dev);
2340 gp->opened = (rc == 0);
2341
2342 mutex_unlock(&gp->pm_mutex);
2343
2344 return rc;
2345 }
2346
2347 static int gem_close(struct net_device *dev)
2348 {
2349 struct gem *gp = netdev_priv(dev);
2350
2351 mutex_lock(&gp->pm_mutex);
2352
2353 napi_disable(&gp->napi);
2354
2355 gp->opened = 0;
2356 if (!gp->asleep)
2357 gem_do_stop(dev, 0);
2358
2359 mutex_unlock(&gp->pm_mutex);
2360
2361 return 0;
2362 }
2363
2364 #ifdef CONFIG_PM
2365 static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2366 {
2367 struct net_device *dev = pci_get_drvdata(pdev);
2368 struct gem *gp = netdev_priv(dev);
2369 unsigned long flags;
2370
2371 mutex_lock(&gp->pm_mutex);
2372
2373 printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
2374 dev->name,
2375 (gp->wake_on_lan && gp->opened) ? "enabled" : "disabled");
2376
2377 /* Keep the cell enabled during the entire operation */
2378 spin_lock_irqsave(&gp->lock, flags);
2379 spin_lock(&gp->tx_lock);
2380 gem_get_cell(gp);
2381 spin_unlock(&gp->tx_lock);
2382 spin_unlock_irqrestore(&gp->lock, flags);
2383
2384 /* If the driver is opened, we stop the MAC */
2385 if (gp->opened) {
2386 napi_disable(&gp->napi);
2387
2388 /* Stop traffic, mark us closed */
2389 netif_device_detach(dev);
2390
2391 /* Switch off MAC, remember WOL setting */
2392 gp->asleep_wol = gp->wake_on_lan;
2393 gem_do_stop(dev, gp->asleep_wol);
2394 } else
2395 gp->asleep_wol = 0;
2396
2397 /* Mark us asleep */
2398 gp->asleep = 1;
2399 wmb();
2400
2401 /* Stop the link timer */
2402 del_timer_sync(&gp->link_timer);
2403
2404 /* Now we release the mutex to not block the reset task who
2405 * can take it too. We are marked asleep, so there will be no
2406 * conflict here
2407 */
2408 mutex_unlock(&gp->pm_mutex);
2409
2410 /* Wait for a pending reset task to complete */
2411 while (gp->reset_task_pending)
2412 yield();
2413 flush_scheduled_work();
2414
2415 /* Shut the PHY down eventually and setup WOL */
2416 gem_stop_phy(gp, gp->asleep_wol);
2417
2418 /* Make sure bus master is disabled */
2419 pci_disable_device(gp->pdev);
2420
2421 /* Release the cell, no need to take a lock at this point since
2422 * nothing else can happen now
2423 */
2424 gem_put_cell(gp);
2425
2426 return 0;
2427 }
2428
2429 static int gem_resume(struct pci_dev *pdev)
2430 {
2431 struct net_device *dev = pci_get_drvdata(pdev);
2432 struct gem *gp = netdev_priv(dev);
2433 unsigned long flags;
2434
2435 printk(KERN_INFO "%s: resuming\n", dev->name);
2436
2437 mutex_lock(&gp->pm_mutex);
2438
2439 /* Keep the cell enabled during the entire operation, no need to
2440 * take a lock here tho since nothing else can happen while we are
2441 * marked asleep
2442 */
2443 gem_get_cell(gp);
2444
2445 /* Make sure PCI access and bus master are enabled */
2446 if (pci_enable_device(gp->pdev)) {
2447 printk(KERN_ERR "%s: Can't re-enable chip !\n",
2448 dev->name);
2449 /* Put cell and forget it for now, it will be considered as
2450 * still asleep, a new sleep cycle may bring it back
2451 */
2452 gem_put_cell(gp);
2453 mutex_unlock(&gp->pm_mutex);
2454 return 0;
2455 }
2456 pci_set_master(gp->pdev);
2457
2458 /* Reset everything */
2459 gem_reset(gp);
2460
2461 /* Mark us woken up */
2462 gp->asleep = 0;
2463 wmb();
2464
2465 /* Bring the PHY back. Again, lock is useless at this point as
2466 * nothing can be happening until we restart the whole thing
2467 */
2468 gem_init_phy(gp);
2469
2470 /* If we were opened, bring everything back */
2471 if (gp->opened) {
2472 /* Restart MAC */
2473 gem_do_start(dev);
2474
2475 /* Re-attach net device */
2476 netif_device_attach(dev);
2477 }
2478
2479 spin_lock_irqsave(&gp->lock, flags);
2480 spin_lock(&gp->tx_lock);
2481
2482 /* If we had WOL enabled, the cell clock was never turned off during
2483 * sleep, so we end up beeing unbalanced. Fix that here
2484 */
2485 if (gp->asleep_wol)
2486 gem_put_cell(gp);
2487
2488 /* This function doesn't need to hold the cell, it will be held if the
2489 * driver is open by gem_do_start().
2490 */
2491 gem_put_cell(gp);
2492
2493 spin_unlock(&gp->tx_lock);
2494 spin_unlock_irqrestore(&gp->lock, flags);
2495
2496 mutex_unlock(&gp->pm_mutex);
2497
2498 return 0;
2499 }
2500 #endif /* CONFIG_PM */
2501
2502 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2503 {
2504 struct gem *gp = netdev_priv(dev);
2505 struct net_device_stats *stats = &gp->net_stats;
2506
2507 spin_lock_irq(&gp->lock);
2508 spin_lock(&gp->tx_lock);
2509
2510 /* I have seen this being called while the PM was in progress,
2511 * so we shield against this
2512 */
2513 if (gp->running) {
2514 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2515 writel(0, gp->regs + MAC_FCSERR);
2516
2517 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2518 writel(0, gp->regs + MAC_AERR);
2519
2520 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2521 writel(0, gp->regs + MAC_LERR);
2522
2523 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2524 stats->collisions +=
2525 (readl(gp->regs + MAC_ECOLL) +
2526 readl(gp->regs + MAC_LCOLL));
2527 writel(0, gp->regs + MAC_ECOLL);
2528 writel(0, gp->regs + MAC_LCOLL);
2529 }
2530
2531 spin_unlock(&gp->tx_lock);
2532 spin_unlock_irq(&gp->lock);
2533
2534 return &gp->net_stats;
2535 }
2536
2537 static int gem_set_mac_address(struct net_device *dev, void *addr)
2538 {
2539 struct sockaddr *macaddr = (struct sockaddr *) addr;
2540 struct gem *gp = netdev_priv(dev);
2541 unsigned char *e = &dev->dev_addr[0];
2542
2543 if (!is_valid_ether_addr(macaddr->sa_data))
2544 return -EADDRNOTAVAIL;
2545
2546 if (!netif_running(dev) || !netif_device_present(dev)) {
2547 /* We'll just catch it later when the
2548 * device is up'd or resumed.
2549 */
2550 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2551 return 0;
2552 }
2553
2554 mutex_lock(&gp->pm_mutex);
2555 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2556 if (gp->running) {
2557 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2558 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2559 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2560 }
2561 mutex_unlock(&gp->pm_mutex);
2562
2563 return 0;
2564 }
2565
2566 static void gem_set_multicast(struct net_device *dev)
2567 {
2568 struct gem *gp = netdev_priv(dev);
2569 u32 rxcfg, rxcfg_new;
2570 int limit = 10000;
2571
2572
2573 spin_lock_irq(&gp->lock);
2574 spin_lock(&gp->tx_lock);
2575
2576 if (!gp->running)
2577 goto bail;
2578
2579 netif_stop_queue(dev);
2580
2581 rxcfg = readl(gp->regs + MAC_RXCFG);
2582 rxcfg_new = gem_setup_multicast(gp);
2583 #ifdef STRIP_FCS
2584 rxcfg_new |= MAC_RXCFG_SFCS;
2585 #endif
2586 gp->mac_rx_cfg = rxcfg_new;
2587
2588 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2589 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2590 if (!limit--)
2591 break;
2592 udelay(10);
2593 }
2594
2595 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2596 rxcfg |= rxcfg_new;
2597
2598 writel(rxcfg, gp->regs + MAC_RXCFG);
2599
2600 netif_wake_queue(dev);
2601
2602 bail:
2603 spin_unlock(&gp->tx_lock);
2604 spin_unlock_irq(&gp->lock);
2605 }
2606
2607 /* Jumbo-grams don't seem to work :-( */
2608 #define GEM_MIN_MTU 68
2609 #if 1
2610 #define GEM_MAX_MTU 1500
2611 #else
2612 #define GEM_MAX_MTU 9000
2613 #endif
2614
2615 static int gem_change_mtu(struct net_device *dev, int new_mtu)
2616 {
2617 struct gem *gp = netdev_priv(dev);
2618
2619 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2620 return -EINVAL;
2621
2622 if (!netif_running(dev) || !netif_device_present(dev)) {
2623 /* We'll just catch it later when the
2624 * device is up'd or resumed.
2625 */
2626 dev->mtu = new_mtu;
2627 return 0;
2628 }
2629
2630 mutex_lock(&gp->pm_mutex);
2631 spin_lock_irq(&gp->lock);
2632 spin_lock(&gp->tx_lock);
2633 dev->mtu = new_mtu;
2634 if (gp->running) {
2635 gem_reinit_chip(gp);
2636 if (gp->lstate == link_up)
2637 gem_set_link_modes(gp);
2638 }
2639 spin_unlock(&gp->tx_lock);
2640 spin_unlock_irq(&gp->lock);
2641 mutex_unlock(&gp->pm_mutex);
2642
2643 return 0;
2644 }
2645
2646 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2647 {
2648 struct gem *gp = netdev_priv(dev);
2649
2650 strcpy(info->driver, DRV_NAME);
2651 strcpy(info->version, DRV_VERSION);
2652 strcpy(info->bus_info, pci_name(gp->pdev));
2653 }
2654
2655 static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2656 {
2657 struct gem *gp = netdev_priv(dev);
2658
2659 if (gp->phy_type == phy_mii_mdio0 ||
2660 gp->phy_type == phy_mii_mdio1) {
2661 if (gp->phy_mii.def)
2662 cmd->supported = gp->phy_mii.def->features;
2663 else
2664 cmd->supported = (SUPPORTED_10baseT_Half |
2665 SUPPORTED_10baseT_Full);
2666
2667 /* XXX hardcoded stuff for now */
2668 cmd->port = PORT_MII;
2669 cmd->transceiver = XCVR_EXTERNAL;
2670 cmd->phy_address = 0; /* XXX fixed PHYAD */
2671
2672 /* Return current PHY settings */
2673 spin_lock_irq(&gp->lock);
2674 cmd->autoneg = gp->want_autoneg;
2675 cmd->speed = gp->phy_mii.speed;
2676 cmd->duplex = gp->phy_mii.duplex;
2677 cmd->advertising = gp->phy_mii.advertising;
2678
2679 /* If we started with a forced mode, we don't have a default
2680 * advertise set, we need to return something sensible so
2681 * userland can re-enable autoneg properly.
2682 */
2683 if (cmd->advertising == 0)
2684 cmd->advertising = cmd->supported;
2685 spin_unlock_irq(&gp->lock);
2686 } else { // XXX PCS ?
2687 cmd->supported =
2688 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2689 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2690 SUPPORTED_Autoneg);
2691 cmd->advertising = cmd->supported;
2692 cmd->speed = 0;
2693 cmd->duplex = cmd->port = cmd->phy_address =
2694 cmd->transceiver = cmd->autoneg = 0;
2695
2696 /* serdes means usually a Fibre connector, with most fixed */
2697 if (gp->phy_type == phy_serdes) {
2698 cmd->port = PORT_FIBRE;
2699 cmd->supported = (SUPPORTED_1000baseT_Half |
2700 SUPPORTED_1000baseT_Full |
2701 SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2702 SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2703 cmd->advertising = cmd->supported;
2704 cmd->transceiver = XCVR_INTERNAL;
2705 if (gp->lstate == link_up)
2706 cmd->speed = SPEED_1000;
2707 cmd->duplex = DUPLEX_FULL;
2708 cmd->autoneg = 1;
2709 }
2710 }
2711 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2712
2713 return 0;
2714 }
2715
2716 static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2717 {
2718 struct gem *gp = netdev_priv(dev);
2719
2720 /* Verify the settings we care about. */
2721 if (cmd->autoneg != AUTONEG_ENABLE &&
2722 cmd->autoneg != AUTONEG_DISABLE)
2723 return -EINVAL;
2724
2725 if (cmd->autoneg == AUTONEG_ENABLE &&
2726 cmd->advertising == 0)
2727 return -EINVAL;
2728
2729 if (cmd->autoneg == AUTONEG_DISABLE &&
2730 ((cmd->speed != SPEED_1000 &&
2731 cmd->speed != SPEED_100 &&
2732 cmd->speed != SPEED_10) ||
2733 (cmd->duplex != DUPLEX_HALF &&
2734 cmd->duplex != DUPLEX_FULL)))
2735 return -EINVAL;
2736
2737 /* Apply settings and restart link process. */
2738 spin_lock_irq(&gp->lock);
2739 gem_get_cell(gp);
2740 gem_begin_auto_negotiation(gp, cmd);
2741 gem_put_cell(gp);
2742 spin_unlock_irq(&gp->lock);
2743
2744 return 0;
2745 }
2746
2747 static int gem_nway_reset(struct net_device *dev)
2748 {
2749 struct gem *gp = netdev_priv(dev);
2750
2751 if (!gp->want_autoneg)
2752 return -EINVAL;
2753
2754 /* Restart link process. */
2755 spin_lock_irq(&gp->lock);
2756 gem_get_cell(gp);
2757 gem_begin_auto_negotiation(gp, NULL);
2758 gem_put_cell(gp);
2759 spin_unlock_irq(&gp->lock);
2760
2761 return 0;
2762 }
2763
2764 static u32 gem_get_msglevel(struct net_device *dev)
2765 {
2766 struct gem *gp = netdev_priv(dev);
2767 return gp->msg_enable;
2768 }
2769
2770 static void gem_set_msglevel(struct net_device *dev, u32 value)
2771 {
2772 struct gem *gp = netdev_priv(dev);
2773 gp->msg_enable = value;
2774 }
2775
2776
2777 /* Add more when I understand how to program the chip */
2778 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2779
2780 #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2781
2782 static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2783 {
2784 struct gem *gp = netdev_priv(dev);
2785
2786 /* Add more when I understand how to program the chip */
2787 if (gp->has_wol) {
2788 wol->supported = WOL_SUPPORTED_MASK;
2789 wol->wolopts = gp->wake_on_lan;
2790 } else {
2791 wol->supported = 0;
2792 wol->wolopts = 0;
2793 }
2794 }
2795
2796 static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2797 {
2798 struct gem *gp = netdev_priv(dev);
2799
2800 if (!gp->has_wol)
2801 return -EOPNOTSUPP;
2802 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2803 return 0;
2804 }
2805
2806 static const struct ethtool_ops gem_ethtool_ops = {
2807 .get_drvinfo = gem_get_drvinfo,
2808 .get_link = ethtool_op_get_link,
2809 .get_settings = gem_get_settings,
2810 .set_settings = gem_set_settings,
2811 .nway_reset = gem_nway_reset,
2812 .get_msglevel = gem_get_msglevel,
2813 .set_msglevel = gem_set_msglevel,
2814 .get_wol = gem_get_wol,
2815 .set_wol = gem_set_wol,
2816 };
2817
2818 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2819 {
2820 struct gem *gp = netdev_priv(dev);
2821 struct mii_ioctl_data *data = if_mii(ifr);
2822 int rc = -EOPNOTSUPP;
2823 unsigned long flags;
2824
2825 /* Hold the PM mutex while doing ioctl's or we may collide
2826 * with power management.
2827 */
2828 mutex_lock(&gp->pm_mutex);
2829
2830 spin_lock_irqsave(&gp->lock, flags);
2831 gem_get_cell(gp);
2832 spin_unlock_irqrestore(&gp->lock, flags);
2833
2834 switch (cmd) {
2835 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2836 data->phy_id = gp->mii_phy_addr;
2837 /* Fallthrough... */
2838
2839 case SIOCGMIIREG: /* Read MII PHY register. */
2840 if (!gp->running)
2841 rc = -EAGAIN;
2842 else {
2843 data->val_out = __phy_read(gp, data->phy_id & 0x1f,
2844 data->reg_num & 0x1f);
2845 rc = 0;
2846 }
2847 break;
2848
2849 case SIOCSMIIREG: /* Write MII PHY register. */
2850 if (!capable(CAP_NET_ADMIN))
2851 rc = -EPERM;
2852 else if (!gp->running)
2853 rc = -EAGAIN;
2854 else {
2855 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2856 data->val_in);
2857 rc = 0;
2858 }
2859 break;
2860 };
2861
2862 spin_lock_irqsave(&gp->lock, flags);
2863 gem_put_cell(gp);
2864 spin_unlock_irqrestore(&gp->lock, flags);
2865
2866 mutex_unlock(&gp->pm_mutex);
2867
2868 return rc;
2869 }
2870
2871 #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2872 /* Fetch MAC address from vital product data of PCI ROM. */
2873 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2874 {
2875 int this_offset;
2876
2877 for (this_offset = 0x20; this_offset < len; this_offset++) {
2878 void __iomem *p = rom_base + this_offset;
2879 int i;
2880
2881 if (readb(p + 0) != 0x90 ||
2882 readb(p + 1) != 0x00 ||
2883 readb(p + 2) != 0x09 ||
2884 readb(p + 3) != 0x4e ||
2885 readb(p + 4) != 0x41 ||
2886 readb(p + 5) != 0x06)
2887 continue;
2888
2889 this_offset += 6;
2890 p += 6;
2891
2892 for (i = 0; i < 6; i++)
2893 dev_addr[i] = readb(p + i);
2894 return 1;
2895 }
2896 return 0;
2897 }
2898
2899 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2900 {
2901 size_t size;
2902 void __iomem *p = pci_map_rom(pdev, &size);
2903
2904 if (p) {
2905 int found;
2906
2907 found = readb(p) == 0x55 &&
2908 readb(p + 1) == 0xaa &&
2909 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2910 pci_unmap_rom(pdev, p);
2911 if (found)
2912 return;
2913 }
2914
2915 /* Sun MAC prefix then 3 random bytes. */
2916 dev_addr[0] = 0x08;
2917 dev_addr[1] = 0x00;
2918 dev_addr[2] = 0x20;
2919 get_random_bytes(dev_addr + 3, 3);
2920 return;
2921 }
2922 #endif /* not Sparc and not PPC */
2923
2924 static int __devinit gem_get_device_address(struct gem *gp)
2925 {
2926 #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2927 struct net_device *dev = gp->dev;
2928 const unsigned char *addr;
2929
2930 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2931 if (addr == NULL) {
2932 #ifdef CONFIG_SPARC
2933 addr = idprom->id_ethaddr;
2934 #else
2935 printk("\n");
2936 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
2937 return -1;
2938 #endif
2939 }
2940 memcpy(dev->dev_addr, addr, 6);
2941 #else
2942 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2943 #endif
2944 return 0;
2945 }
2946
2947 static void gem_remove_one(struct pci_dev *pdev)
2948 {
2949 struct net_device *dev = pci_get_drvdata(pdev);
2950
2951 if (dev) {
2952 struct gem *gp = netdev_priv(dev);
2953
2954 unregister_netdev(dev);
2955
2956 /* Stop the link timer */
2957 del_timer_sync(&gp->link_timer);
2958
2959 /* We shouldn't need any locking here */
2960 gem_get_cell(gp);
2961
2962 /* Wait for a pending reset task to complete */
2963 while (gp->reset_task_pending)
2964 yield();
2965 flush_scheduled_work();
2966
2967 /* Shut the PHY down */
2968 gem_stop_phy(gp, 0);
2969
2970 gem_put_cell(gp);
2971
2972 /* Make sure bus master is disabled */
2973 pci_disable_device(gp->pdev);
2974
2975 /* Free resources */
2976 pci_free_consistent(pdev,
2977 sizeof(struct gem_init_block),
2978 gp->init_block,
2979 gp->gblock_dvma);
2980 iounmap(gp->regs);
2981 pci_release_regions(pdev);
2982 free_netdev(dev);
2983
2984 pci_set_drvdata(pdev, NULL);
2985 }
2986 }
2987
2988 static const struct net_device_ops gem_netdev_ops = {
2989 .ndo_open = gem_open,
2990 .ndo_stop = gem_close,
2991 .ndo_start_xmit = gem_start_xmit,
2992 .ndo_get_stats = gem_get_stats,
2993 .ndo_set_multicast_list = gem_set_multicast,
2994 .ndo_do_ioctl = gem_ioctl,
2995 .ndo_tx_timeout = gem_tx_timeout,
2996 .ndo_change_mtu = gem_change_mtu,
2997 .ndo_validate_addr = eth_validate_addr,
2998 .ndo_set_mac_address = gem_set_mac_address,
2999 #ifdef CONFIG_NET_POLL_CONTROLLER
3000 .ndo_poll_controller = gem_poll_controller,
3001 #endif
3002 };
3003
3004 static int __devinit gem_init_one(struct pci_dev *pdev,
3005 const struct pci_device_id *ent)
3006 {
3007 static int gem_version_printed = 0;
3008 unsigned long gemreg_base, gemreg_len;
3009 struct net_device *dev;
3010 struct gem *gp;
3011 int err, pci_using_dac;
3012
3013 if (gem_version_printed++ == 0)
3014 printk(KERN_INFO "%s", version);
3015
3016 /* Apple gmac note: during probe, the chip is powered up by
3017 * the arch code to allow the code below to work (and to let
3018 * the chip be probed on the config space. It won't stay powered
3019 * up until the interface is brought up however, so we can't rely
3020 * on register configuration done at this point.
3021 */
3022 err = pci_enable_device(pdev);
3023 if (err) {
3024 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
3025 "aborting.\n");
3026 return err;
3027 }
3028 pci_set_master(pdev);
3029
3030 /* Configure DMA attributes. */
3031
3032 /* All of the GEM documentation states that 64-bit DMA addressing
3033 * is fully supported and should work just fine. However the
3034 * front end for RIO based GEMs is different and only supports
3035 * 32-bit addressing.
3036 *
3037 * For now we assume the various PPC GEMs are 32-bit only as well.
3038 */
3039 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
3040 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
3041 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3042 pci_using_dac = 1;
3043 } else {
3044 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3045 if (err) {
3046 printk(KERN_ERR PFX "No usable DMA configuration, "
3047 "aborting.\n");
3048 goto err_disable_device;
3049 }
3050 pci_using_dac = 0;
3051 }
3052
3053 gemreg_base = pci_resource_start(pdev, 0);
3054 gemreg_len = pci_resource_len(pdev, 0);
3055
3056 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3057 printk(KERN_ERR PFX "Cannot find proper PCI device "
3058 "base address, aborting.\n");
3059 err = -ENODEV;
3060 goto err_disable_device;
3061 }
3062
3063 dev = alloc_etherdev(sizeof(*gp));
3064 if (!dev) {
3065 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
3066 err = -ENOMEM;
3067 goto err_disable_device;
3068 }
3069 SET_NETDEV_DEV(dev, &pdev->dev);
3070
3071 gp = netdev_priv(dev);
3072
3073 err = pci_request_regions(pdev, DRV_NAME);
3074 if (err) {
3075 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
3076 "aborting.\n");
3077 goto err_out_free_netdev;
3078 }
3079
3080 gp->pdev = pdev;
3081 dev->base_addr = (long) pdev;
3082 gp->dev = dev;
3083
3084 gp->msg_enable = DEFAULT_MSG;
3085
3086 spin_lock_init(&gp->lock);
3087 spin_lock_init(&gp->tx_lock);
3088 mutex_init(&gp->pm_mutex);
3089
3090 init_timer(&gp->link_timer);
3091 gp->link_timer.function = gem_link_timer;
3092 gp->link_timer.data = (unsigned long) gp;
3093
3094 INIT_WORK(&gp->reset_task, gem_reset_task);
3095
3096 gp->lstate = link_down;
3097 gp->timer_ticks = 0;
3098 netif_carrier_off(dev);
3099
3100 gp->regs = ioremap(gemreg_base, gemreg_len);
3101 if (!gp->regs) {
3102 printk(KERN_ERR PFX "Cannot map device registers, "
3103 "aborting.\n");
3104 err = -EIO;
3105 goto err_out_free_res;
3106 }
3107
3108 /* On Apple, we want a reference to the Open Firmware device-tree
3109 * node. We use it for clock control.
3110 */
3111 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
3112 gp->of_node = pci_device_to_OF_node(pdev);
3113 #endif
3114
3115 /* Only Apple version supports WOL afaik */
3116 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
3117 gp->has_wol = 1;
3118
3119 /* Make sure cell is enabled */
3120 gem_get_cell(gp);
3121
3122 /* Make sure everything is stopped and in init state */
3123 gem_reset(gp);
3124
3125 /* Fill up the mii_phy structure (even if we won't use it) */
3126 gp->phy_mii.dev = dev;
3127 gp->phy_mii.mdio_read = _phy_read;
3128 gp->phy_mii.mdio_write = _phy_write;
3129 #ifdef CONFIG_PPC_PMAC
3130 gp->phy_mii.platform_data = gp->of_node;
3131 #endif
3132 /* By default, we start with autoneg */
3133 gp->want_autoneg = 1;
3134
3135 /* Check fifo sizes, PHY type, etc... */
3136 if (gem_check_invariants(gp)) {
3137 err = -ENODEV;
3138 goto err_out_iounmap;
3139 }
3140
3141 /* It is guaranteed that the returned buffer will be at least
3142 * PAGE_SIZE aligned.
3143 */
3144 gp->init_block = (struct gem_init_block *)
3145 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
3146 &gp->gblock_dvma);
3147 if (!gp->init_block) {
3148 printk(KERN_ERR PFX "Cannot allocate init block, "
3149 "aborting.\n");
3150 err = -ENOMEM;
3151 goto err_out_iounmap;
3152 }
3153
3154 if (gem_get_device_address(gp))
3155 goto err_out_free_consistent;
3156
3157 dev->netdev_ops = &gem_netdev_ops;
3158 netif_napi_add(dev, &gp->napi, gem_poll, 64);
3159 dev->ethtool_ops = &gem_ethtool_ops;
3160 dev->watchdog_timeo = 5 * HZ;
3161 dev->irq = pdev->irq;
3162 dev->dma = 0;
3163
3164 /* Set that now, in case PM kicks in now */
3165 pci_set_drvdata(pdev, dev);
3166
3167 /* Detect & init PHY, start autoneg, we release the cell now
3168 * too, it will be managed by whoever needs it
3169 */
3170 gem_init_phy(gp);
3171
3172 spin_lock_irq(&gp->lock);
3173 gem_put_cell(gp);
3174 spin_unlock_irq(&gp->lock);
3175
3176 /* Register with kernel */
3177 if (register_netdev(dev)) {
3178 printk(KERN_ERR PFX "Cannot register net device, "
3179 "aborting.\n");
3180 err = -ENOMEM;
3181 goto err_out_free_consistent;
3182 }
3183
3184 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3185 dev->name, dev->dev_addr);
3186
3187 if (gp->phy_type == phy_mii_mdio0 ||
3188 gp->phy_type == phy_mii_mdio1)
3189 printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
3190 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
3191
3192 /* GEM can do it all... */
3193 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_LLTX;
3194 if (pci_using_dac)
3195 dev->features |= NETIF_F_HIGHDMA;
3196
3197 return 0;
3198
3199 err_out_free_consistent:
3200 gem_remove_one(pdev);
3201 err_out_iounmap:
3202 gem_put_cell(gp);
3203 iounmap(gp->regs);
3204
3205 err_out_free_res:
3206 pci_release_regions(pdev);
3207
3208 err_out_free_netdev:
3209 free_netdev(dev);
3210 err_disable_device:
3211 pci_disable_device(pdev);
3212 return err;
3213
3214 }
3215
3216
3217 static struct pci_driver gem_driver = {
3218 .name = GEM_MODULE_NAME,
3219 .id_table = gem_pci_tbl,
3220 .probe = gem_init_one,
3221 .remove = gem_remove_one,
3222 #ifdef CONFIG_PM
3223 .suspend = gem_suspend,
3224 .resume = gem_resume,
3225 #endif /* CONFIG_PM */
3226 };
3227
3228 static int __init gem_init(void)
3229 {
3230 return pci_register_driver(&gem_driver);
3231 }
3232
3233 static void __exit gem_cleanup(void)
3234 {
3235 pci_unregister_driver(&gem_driver);
3236 }
3237
3238 module_init(gem_init);
3239 module_exit(gem_cleanup);
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