kernel/2.6.29.6-aldebaran-rt/drivers/net/igb/igb.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28
  29 /* Linux PRO/1000 Ethernet Driver main header file */
  30
  31 #ifndef _IGB_H_
  32 #define _IGB_H_
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36
  37 struct igb_adapter;
  38
  39 #ifdef CONFIG_IGB_LRO
  40 #include <linux/inet_lro.h>
  41 #define MAX_LRO_AGGR                      32
  42 #define MAX_LRO_DESCRIPTORS                8
  43 #endif
  44
  45 /* Interrupt defines */
  46 #define IGB_MIN_DYN_ITR 3000
  47 #define IGB_MAX_DYN_ITR 96000
  48
  49 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
  50 #define IGB_START_ITR 648
  51
  52 #define IGB_DYN_ITR_PACKET_THRESHOLD 2
  53 #define IGB_DYN_ITR_LENGTH_LOW 200
  54 #define IGB_DYN_ITR_LENGTH_HIGH 1000
  55
  56 /* TX/RX descriptor defines */
  57 #define IGB_DEFAULT_TXD                  256
  58 #define IGB_MIN_TXD                       80
  59 #define IGB_MAX_TXD                     4096
  60
  61 #define IGB_DEFAULT_RXD                  256
  62 #define IGB_MIN_RXD                       80
  63 #define IGB_MAX_RXD                     4096
  64
  65 #define IGB_DEFAULT_ITR                    3 /* dynamic */
  66 #define IGB_MAX_ITR_USECS              10000
  67 #define IGB_MIN_ITR_USECS                 10
  68
  69 /* Transmit and receive queues */
  70 #define IGB_MAX_RX_QUEUES                  4
  71 #define IGB_MAX_TX_QUEUES                  4
  72
  73 /* RX descriptor control thresholds.
  74  * PTHRESH - MAC will consider prefetch if it has fewer than this number of
  75  *           descriptors available in its onboard memory.
  76  *           Setting this to 0 disables RX descriptor prefetch.
  77  * HTHRESH - MAC will only prefetch if there are at least this many descriptors
  78  *           available in host memory.
  79  *           If PTHRESH is 0, this should also be 0.
  80  * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
  81  *           descriptors until either it has this many to write back, or the
  82  *           ITR timer expires.
  83  */
  84 #define IGB_RX_PTHRESH                    16
  85 #define IGB_RX_HTHRESH                     8
  86 #define IGB_RX_WTHRESH                     1
  87
  88 /* this is the size past which hardware will drop packets when setting LPE=0 */
  89 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
  90
  91 /* Supported Rx Buffer Sizes */
  92 #define IGB_RXBUFFER_128   128    /* Used for packet split */
  93 #define IGB_RXBUFFER_256   256    /* Used for packet split */
  94 #define IGB_RXBUFFER_512   512
  95 #define IGB_RXBUFFER_1024  1024
  96 #define IGB_RXBUFFER_2048  2048
  97 #define IGB_RXBUFFER_4096  4096
  98 #define IGB_RXBUFFER_8192  8192
  99 #define IGB_RXBUFFER_16384 16384
 100
 101 /* Packet Buffer allocations */
 102
 103
 104 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
 105 #define IGB_TX_QUEUE_WAKE       16
 106 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 107 #define IGB_RX_BUFFER_WRITE     16      /* Must be power of 2 */
 108
 109 #define AUTO_ALL_MODES            0
 110 #define IGB_EEPROM_APME         0x0400
 111
 112 #ifndef IGB_MASTER_SLAVE
 113 /* Switch to override PHY master/slave setting */
 114 #define IGB_MASTER_SLAVE        e1000_ms_hw_default
 115 #endif
 116
 117 #define IGB_MNG_VLAN_NONE -1
 118
 119 /* wrapper around a pointer to a socket buffer,
 120  * so a DMA handle can be stored along with the buffer */
 121 struct igb_buffer {
 122         struct sk_buff *skb;
 123         dma_addr_t dma;
 124         union {
 125                 /* TX */
 126                 struct {
 127                         unsigned long time_stamp;
 128                         u16 length;
 129                         u16 next_to_watch;
 130                 };
 131                 /* RX */
 132                 struct {
 133                         struct page *page;
 134                         u64 page_dma;
 135                         unsigned int page_offset;
 136                 };
 137         };
 138 };
 139
 140 struct igb_queue_stats {
 141         u64 packets;
 142         u64 bytes;
 143 };
 144
 145 struct igb_ring {
 146         struct igb_adapter *adapter; /* backlink */
 147         void *desc;                  /* descriptor ring memory */
 148         dma_addr_t dma;              /* phys address of the ring */
 149         unsigned int size;           /* length of desc. ring in bytes */
 150         unsigned int count;          /* number of desc. in the ring */
 151         u16 next_to_use;
 152         u16 next_to_clean;
 153         u16 head;
 154         u16 tail;
 155         struct igb_buffer *buffer_info; /* array of buffer info structs */
 156
 157         u32 eims_value;
 158         u32 itr_val;
 159         u16 itr_register;
 160         u16 cpu;
 161
 162         u16 queue_index;
 163         u16 reg_idx;
 164         unsigned int total_bytes;
 165         unsigned int total_packets;
 166
 167         union {
 168                 /* TX */
 169                 struct {
 170                         struct igb_queue_stats tx_stats;
 171                         bool detect_tx_hung;
 172                 };
 173                 /* RX */
 174                 struct {
 175                         struct igb_queue_stats rx_stats;
 176                         struct napi_struct napi;
 177                         int set_itr;
 178                         struct igb_ring *buddy;
 179 #ifdef CONFIG_IGB_LRO
 180                         struct net_lro_mgr lro_mgr;
 181                         bool lro_used;
 182 #endif
 183                 };
 184         };
 185
 186         char name[IFNAMSIZ + 5];
 187 };
 188
 189 #define IGB_DESC_UNUSED(R) \
 190         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 191         (R)->next_to_clean - (R)->next_to_use - 1)
 192
 193 #define E1000_RX_DESC_ADV(R, i)     \
 194         (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
 195 #define E1000_TX_DESC_ADV(R, i)     \
 196         (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
 197 #define E1000_TX_CTXTDESC_ADV(R, i)         \
 198         (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
 199 #define E1000_GET_DESC(R, i, type)      (&(((struct type *)((R).desc))[i]))
 200 #define E1000_TX_DESC(R, i)             E1000_GET_DESC(R, i, e1000_tx_desc)
 201 #define E1000_RX_DESC(R, i)             E1000_GET_DESC(R, i, e1000_rx_desc)
 202
 203 /* board specific private data structure */
 204
 205 struct igb_adapter {
 206         struct timer_list watchdog_timer;
 207         struct timer_list phy_info_timer;
 208         struct vlan_group *vlgrp;
 209         u16 mng_vlan_id;
 210         u32 bd_number;
 211         u32 rx_buffer_len;
 212         u32 wol;
 213         u32 en_mng_pt;
 214         u16 link_speed;
 215         u16 link_duplex;
 216         unsigned int total_tx_bytes;
 217         unsigned int total_tx_packets;
 218         unsigned int total_rx_bytes;
 219         unsigned int total_rx_packets;
 220         /* Interrupt Throttle Rate */
 221         u32 itr;
 222         u32 itr_setting;
 223         u16 tx_itr;
 224         u16 rx_itr;
 225
 226         struct work_struct reset_task;
 227         struct work_struct watchdog_task;
 228         bool fc_autoneg;
 229         u8  tx_timeout_factor;
 230         struct timer_list blink_timer;
 231         unsigned long led_status;
 232
 233         /* TX */
 234         struct igb_ring *tx_ring;      /* One per active queue */
 235         unsigned int restart_queue;
 236         unsigned long tx_queue_len;
 237         u32 txd_cmd;
 238         u32 gotc;
 239         u64 gotc_old;
 240         u64 tpt_old;
 241         u64 colc_old;
 242         u32 tx_timeout_count;
 243
 244         /* RX */
 245         struct igb_ring *rx_ring;      /* One per active queue */
 246         int num_tx_queues;
 247         int num_rx_queues;
 248
 249         u64 hw_csum_err;
 250         u64 hw_csum_good;
 251         u64 rx_hdr_split;
 252         u32 alloc_rx_buff_failed;
 253         bool rx_csum;
 254         u32 gorc;
 255         u64 gorc_old;
 256         u16 rx_ps_hdr_size;
 257         u32 max_frame_size;
 258         u32 min_frame_size;
 259
 260         /* OS defined structs */
 261         struct net_device *netdev;
 262         struct napi_struct napi;
 263         struct pci_dev *pdev;
 264         struct net_device_stats net_stats;
 265
 266         /* structs defined in e1000_hw.h */
 267         struct e1000_hw hw;
 268         struct e1000_hw_stats stats;
 269         struct e1000_phy_info phy_info;
 270         struct e1000_phy_stats phy_stats;
 271
 272         u32 test_icr;
 273         struct igb_ring test_tx_ring;
 274         struct igb_ring test_rx_ring;
 275
 276         int msg_enable;
 277         struct msix_entry *msix_entries;
 278         u32 eims_enable_mask;
 279         u32 eims_other;
 280
 281         /* to not mess up cache alignment, always add to the bottom */
 282         unsigned long state;
 283         unsigned int flags;
 284         u32 eeprom_wol;
 285
 286         /* for ioport free */
 287         int bars;
 288         int need_ioport;
 289
 290         struct igb_ring *multi_tx_table[IGB_MAX_TX_QUEUES];
 291 #ifdef CONFIG_IGB_LRO
 292         unsigned int lro_max_aggr;
 293         unsigned int lro_aggregated;
 294         unsigned int lro_flushed;
 295         unsigned int lro_no_desc;
 296 #endif
 297         unsigned int tx_ring_count;
 298         unsigned int rx_ring_count;
 299 };
 300
 301 #define IGB_FLAG_HAS_MSI           (1 << 0)
 302 #define IGB_FLAG_MSI_ENABLE        (1 << 1)
 303 #define IGB_FLAG_DCA_ENABLED       (1 << 2)
 304 #define IGB_FLAG_IN_NETPOLL        (1 << 3)
 305 #define IGB_FLAG_QUAD_PORT_A       (1 << 4)
 306 #define IGB_FLAG_NEED_CTX_IDX      (1 << 5)
 307
 308 enum e1000_state_t {
 309         __IGB_TESTING,
 310         __IGB_RESETTING,
 311         __IGB_DOWN
 312 };
 313
 314 enum igb_boards {
 315         board_82575,
 316 };
 317
 318 extern char igb_driver_name[];
 319 extern char igb_driver_version[];
 320
 321 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
 322 extern int igb_up(struct igb_adapter *);
 323 extern void igb_down(struct igb_adapter *);
 324 extern void igb_reinit_locked(struct igb_adapter *);
 325 extern void igb_reset(struct igb_adapter *);
 326 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
 327 extern int igb_setup_tx_resources(struct igb_adapter *, struct igb_ring *);
 328 extern int igb_setup_rx_resources(struct igb_adapter *, struct igb_ring *);
 329 extern void igb_free_tx_resources(struct igb_ring *);
 330 extern void igb_free_rx_resources(struct igb_ring *);
 331 extern void igb_update_stats(struct igb_adapter *);
 332 extern void igb_set_ethtool_ops(struct net_device *);
 333
 334 static inline s32 igb_reset_phy(struct e1000_hw *hw)
 335 {
 336         if (hw->phy.ops.reset_phy)
 337                 return hw->phy.ops.reset_phy(hw);
 338
 339         return 0;
 340 }
 341
 342 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
 343 {
 344         if (hw->phy.ops.read_phy_reg)
 345                 return hw->phy.ops.read_phy_reg(hw, offset, data);
 346
 347         return 0;
 348 }
 349
 350 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
 351 {
 352         if (hw->phy.ops.write_phy_reg)
 353                 return hw->phy.ops.write_phy_reg(hw, offset, data);
 354
 355         return 0;
 356 }
 357
 358 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
 359 {
 360         if (hw->phy.ops.get_phy_info)
 361                 return hw->phy.ops.get_phy_info(hw);
 362
 363         return 0;
 364 }
 365
 366 #endif /* _IGB_H_ */