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added 2.6.29.6 aldebaran kernel
[nao-ulib.git] / kernel / 2.6.29.6-aldebaran-rt / drivers / net / e1000 / e1000_hw.h
blob99fce2c5dd26b21b0b4e6ff7d6a96d10e8e29758
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* e1000_hw.h
30 * Structures, enums, and macros for the MAC
31 */
32
33 #ifndef _E1000_HW_H_
34 #define _E1000_HW_H_
35
36 #include "e1000_osdep.h"
37
38
39 /* Forward declarations of structures used by the shared code */
40 struct e1000_hw;
41 struct e1000_hw_stats;
42
43 /* Enumerated types specific to the e1000 hardware */
44 /* Media Access Controlers */
45 typedef enum {
46 e1000_undefined = 0,
47 e1000_82542_rev2_0,
48 e1000_82542_rev2_1,
49 e1000_82543,
50 e1000_82544,
51 e1000_82540,
52 e1000_82545,
53 e1000_82545_rev_3,
54 e1000_82546,
55 e1000_82546_rev_3,
56 e1000_82541,
57 e1000_82541_rev_2,
58 e1000_82547,
59 e1000_82547_rev_2,
60 e1000_82571,
61 e1000_82572,
62 e1000_82573,
63 e1000_80003es2lan,
64 e1000_ich8lan,
65 e1000_num_macs
66 } e1000_mac_type;
67
68 typedef enum {
69 e1000_eeprom_uninitialized = 0,
70 e1000_eeprom_spi,
71 e1000_eeprom_microwire,
72 e1000_eeprom_flash,
73 e1000_eeprom_ich8,
74 e1000_eeprom_none, /* No NVM support */
75 e1000_num_eeprom_types
76 } e1000_eeprom_type;
77
78 /* Media Types */
79 typedef enum {
80 e1000_media_type_copper = 0,
81 e1000_media_type_fiber = 1,
82 e1000_media_type_internal_serdes = 2,
83 e1000_num_media_types
84 } e1000_media_type;
85
86 typedef enum {
87 e1000_10_half = 0,
88 e1000_10_full = 1,
89 e1000_100_half = 2,
90 e1000_100_full = 3
91 } e1000_speed_duplex_type;
92
93 /* Flow Control Settings */
94 typedef enum {
95 E1000_FC_NONE = 0,
96 E1000_FC_RX_PAUSE = 1,
97 E1000_FC_TX_PAUSE = 2,
98 E1000_FC_FULL = 3,
99 E1000_FC_DEFAULT = 0xFF
100 } e1000_fc_type;
101
102 struct e1000_shadow_ram {
103 u16 eeprom_word;
104 bool modified;
105 };
106
107 /* PCI bus types */
108 typedef enum {
109 e1000_bus_type_unknown = 0,
110 e1000_bus_type_pci,
111 e1000_bus_type_pcix,
112 e1000_bus_type_pci_express,
113 e1000_bus_type_reserved
114 } e1000_bus_type;
115
116 /* PCI bus speeds */
117 typedef enum {
118 e1000_bus_speed_unknown = 0,
119 e1000_bus_speed_33,
120 e1000_bus_speed_66,
121 e1000_bus_speed_100,
122 e1000_bus_speed_120,
123 e1000_bus_speed_133,
124 e1000_bus_speed_2500,
125 e1000_bus_speed_reserved
126 } e1000_bus_speed;
127
128 /* PCI bus widths */
129 typedef enum {
130 e1000_bus_width_unknown = 0,
131 /* These PCIe values should literally match the possible return values
132 * from config space */
133 e1000_bus_width_pciex_1 = 1,
134 e1000_bus_width_pciex_2 = 2,
135 e1000_bus_width_pciex_4 = 4,
136 e1000_bus_width_32,
137 e1000_bus_width_64,
138 e1000_bus_width_reserved
139 } e1000_bus_width;
140
141 /* PHY status info structure and supporting enums */
142 typedef enum {
143 e1000_cable_length_50 = 0,
144 e1000_cable_length_50_80,
145 e1000_cable_length_80_110,
146 e1000_cable_length_110_140,
147 e1000_cable_length_140,
148 e1000_cable_length_undefined = 0xFF
149 } e1000_cable_length;
150
151 typedef enum {
152 e1000_gg_cable_length_60 = 0,
153 e1000_gg_cable_length_60_115 = 1,
154 e1000_gg_cable_length_115_150 = 2,
155 e1000_gg_cable_length_150 = 4
156 } e1000_gg_cable_length;
157
158 typedef enum {
159 e1000_igp_cable_length_10 = 10,
160 e1000_igp_cable_length_20 = 20,
161 e1000_igp_cable_length_30 = 30,
162 e1000_igp_cable_length_40 = 40,
163 e1000_igp_cable_length_50 = 50,
164 e1000_igp_cable_length_60 = 60,
165 e1000_igp_cable_length_70 = 70,
166 e1000_igp_cable_length_80 = 80,
167 e1000_igp_cable_length_90 = 90,
168 e1000_igp_cable_length_100 = 100,
169 e1000_igp_cable_length_110 = 110,
170 e1000_igp_cable_length_115 = 115,
171 e1000_igp_cable_length_120 = 120,
172 e1000_igp_cable_length_130 = 130,
173 e1000_igp_cable_length_140 = 140,
174 e1000_igp_cable_length_150 = 150,
175 e1000_igp_cable_length_160 = 160,
176 e1000_igp_cable_length_170 = 170,
177 e1000_igp_cable_length_180 = 180
178 } e1000_igp_cable_length;
179
180 typedef enum {
181 e1000_10bt_ext_dist_enable_normal = 0,
182 e1000_10bt_ext_dist_enable_lower,
183 e1000_10bt_ext_dist_enable_undefined = 0xFF
184 } e1000_10bt_ext_dist_enable;
185
186 typedef enum {
187 e1000_rev_polarity_normal = 0,
188 e1000_rev_polarity_reversed,
189 e1000_rev_polarity_undefined = 0xFF
190 } e1000_rev_polarity;
191
192 typedef enum {
193 e1000_downshift_normal = 0,
194 e1000_downshift_activated,
195 e1000_downshift_undefined = 0xFF
196 } e1000_downshift;
197
198 typedef enum {
199 e1000_smart_speed_default = 0,
200 e1000_smart_speed_on,
201 e1000_smart_speed_off
202 } e1000_smart_speed;
203
204 typedef enum {
205 e1000_polarity_reversal_enabled = 0,
206 e1000_polarity_reversal_disabled,
207 e1000_polarity_reversal_undefined = 0xFF
208 } e1000_polarity_reversal;
209
210 typedef enum {
211 e1000_auto_x_mode_manual_mdi = 0,
212 e1000_auto_x_mode_manual_mdix,
213 e1000_auto_x_mode_auto1,
214 e1000_auto_x_mode_auto2,
215 e1000_auto_x_mode_undefined = 0xFF
216 } e1000_auto_x_mode;
217
218 typedef enum {
219 e1000_1000t_rx_status_not_ok = 0,
220 e1000_1000t_rx_status_ok,
221 e1000_1000t_rx_status_undefined = 0xFF
222 } e1000_1000t_rx_status;
223
224 typedef enum {
225 e1000_phy_m88 = 0,
226 e1000_phy_igp,
227 e1000_phy_igp_2,
228 e1000_phy_gg82563,
229 e1000_phy_igp_3,
230 e1000_phy_ife,
231 e1000_phy_undefined = 0xFF
232 } e1000_phy_type;
233
234 typedef enum {
235 e1000_ms_hw_default = 0,
236 e1000_ms_force_master,
237 e1000_ms_force_slave,
238 e1000_ms_auto
239 } e1000_ms_type;
240
241 typedef enum {
242 e1000_ffe_config_enabled = 0,
243 e1000_ffe_config_active,
244 e1000_ffe_config_blocked
245 } e1000_ffe_config;
246
247 typedef enum {
248 e1000_dsp_config_disabled = 0,
249 e1000_dsp_config_enabled,
250 e1000_dsp_config_activated,
251 e1000_dsp_config_undefined = 0xFF
252 } e1000_dsp_config;
253
254 struct e1000_phy_info {
255 e1000_cable_length cable_length;
256 e1000_10bt_ext_dist_enable extended_10bt_distance;
257 e1000_rev_polarity cable_polarity;
258 e1000_downshift downshift;
259 e1000_polarity_reversal polarity_correction;
260 e1000_auto_x_mode mdix_mode;
261 e1000_1000t_rx_status local_rx;
262 e1000_1000t_rx_status remote_rx;
263 };
264
265 struct e1000_phy_stats {
266 u32 idle_errors;
267 u32 receive_errors;
268 };
269
270 struct e1000_eeprom_info {
271 e1000_eeprom_type type;
272 u16 word_size;
273 u16 opcode_bits;
274 u16 address_bits;
275 u16 delay_usec;
276 u16 page_size;
277 bool use_eerd;
278 bool use_eewr;
279 };
280
281 /* Flex ASF Information */
282 #define E1000_HOST_IF_MAX_SIZE 2048
283
284 typedef enum {
285 e1000_byte_align = 0,
286 e1000_word_align = 1,
287 e1000_dword_align = 2
288 } e1000_align_type;
289
290
291
292 /* Error Codes */
293 #define E1000_SUCCESS 0
294 #define E1000_ERR_EEPROM 1
295 #define E1000_ERR_PHY 2
296 #define E1000_ERR_CONFIG 3
297 #define E1000_ERR_PARAM 4
298 #define E1000_ERR_MAC_TYPE 5
299 #define E1000_ERR_PHY_TYPE 6
300 #define E1000_ERR_RESET 9
301 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
302 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
303 #define E1000_BLK_PHY_RESET 12
304 #define E1000_ERR_SWFW_SYNC 13
305
306 #define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \
307 (((_value) & 0xff00) >> 8))
308
309 /* Function prototypes */
310 /* Initialization */
311 s32 e1000_reset_hw(struct e1000_hw *hw);
312 s32 e1000_init_hw(struct e1000_hw *hw);
313 s32 e1000_set_mac_type(struct e1000_hw *hw);
314 void e1000_set_media_type(struct e1000_hw *hw);
315
316 /* Link Configuration */
317 s32 e1000_setup_link(struct e1000_hw *hw);
318 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
319 void e1000_config_collision_dist(struct e1000_hw *hw);
320 s32 e1000_check_for_link(struct e1000_hw *hw);
321 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex);
322 s32 e1000_force_mac_fc(struct e1000_hw *hw);
323
324 /* PHY */
325 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data);
326 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
327 s32 e1000_phy_hw_reset(struct e1000_hw *hw);
328 s32 e1000_phy_reset(struct e1000_hw *hw);
329 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
330 s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
331
332 void e1000_phy_powerdown_workaround(struct e1000_hw *hw);
333
334 /* EEPROM Functions */
335 s32 e1000_init_eeprom_params(struct e1000_hw *hw);
336
337 /* MNG HOST IF functions */
338 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);
339
340 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
341 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
342
343 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
344 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
345 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
346 #define E1000_MNG_IAMT_MODE 0x3
347 #define E1000_MNG_ICH_IAMT_MODE 0x2
348 #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
349
350 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
351 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
352 #define E1000_VFTA_ENTRY_SHIFT 0x5
353 #define E1000_VFTA_ENTRY_MASK 0x7F
354 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
355
356 struct e1000_host_mng_command_header {
357 u8 command_id;
358 u8 checksum;
359 u16 reserved1;
360 u16 reserved2;
361 u16 command_length;
362 };
363
364 struct e1000_host_mng_command_info {
365 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
366 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/
367 };
368 #ifdef __BIG_ENDIAN
369 struct e1000_host_mng_dhcp_cookie{
370 u32 signature;
371 u16 vlan_id;
372 u8 reserved0;
373 u8 status;
374 u32 reserved1;
375 u8 checksum;
376 u8 reserved3;
377 u16 reserved2;
378 };
379 #else
380 struct e1000_host_mng_dhcp_cookie{
381 u32 signature;
382 u8 status;
383 u8 reserved0;
384 u16 vlan_id;
385 u32 reserved1;
386 u16 reserved2;
387 u8 reserved3;
388 u8 checksum;
389 };
390 #endif
391
392 s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer,
393 u16 length);
394 bool e1000_check_mng_mode(struct e1000_hw *hw);
395 bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
396 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data);
397 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
398 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
399 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data);
400 s32 e1000_read_mac_addr(struct e1000_hw * hw);
401
402 /* Filters (multicast, vlan, receive) */
403 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
404 void e1000_mta_set(struct e1000_hw *hw, u32 hash_value);
405 void e1000_rar_set(struct e1000_hw *hw, u8 * mc_addr, u32 rar_index);
406 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
407
408 /* LED functions */
409 s32 e1000_setup_led(struct e1000_hw *hw);
410 s32 e1000_cleanup_led(struct e1000_hw *hw);
411 s32 e1000_led_on(struct e1000_hw *hw);
412 s32 e1000_led_off(struct e1000_hw *hw);
413 s32 e1000_blink_led_start(struct e1000_hw *hw);
414
415 /* Adaptive IFS Functions */
416
417 /* Everything else */
418 void e1000_reset_adaptive(struct e1000_hw *hw);
419 void e1000_update_adaptive(struct e1000_hw *hw);
420 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, u32 frame_len, u8 * mac_addr);
421 void e1000_get_bus_info(struct e1000_hw *hw);
422 void e1000_pci_set_mwi(struct e1000_hw *hw);
423 void e1000_pci_clear_mwi(struct e1000_hw *hw);
424 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
425 void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc);
426 int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
427 /* Port I/O is only supported on 82544 and newer */
428 void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
429 s32 e1000_disable_pciex_master(struct e1000_hw *hw);
430 s32 e1000_check_phy_reset_block(struct e1000_hw *hw);
431
432
433 #define E1000_READ_REG_IO(a, reg) \
434 e1000_read_reg_io((a), E1000_##reg)
435 #define E1000_WRITE_REG_IO(a, reg, val) \
436 e1000_write_reg_io((a), E1000_##reg, val)
437
438 /* PCI Device IDs */
439 #define E1000_DEV_ID_82542 0x1000
440 #define E1000_DEV_ID_82543GC_FIBER 0x1001
441 #define E1000_DEV_ID_82543GC_COPPER 0x1004
442 #define E1000_DEV_ID_82544EI_COPPER 0x1008
443 #define E1000_DEV_ID_82544EI_FIBER 0x1009
444 #define E1000_DEV_ID_82544GC_COPPER 0x100C
445 #define E1000_DEV_ID_82544GC_LOM 0x100D
446 #define E1000_DEV_ID_82540EM 0x100E
447 #define E1000_DEV_ID_82540EM_LOM 0x1015
448 #define E1000_DEV_ID_82540EP_LOM 0x1016
449 #define E1000_DEV_ID_82540EP 0x1017
450 #define E1000_DEV_ID_82540EP_LP 0x101E
451 #define E1000_DEV_ID_82545EM_COPPER 0x100F
452 #define E1000_DEV_ID_82545EM_FIBER 0x1011
453 #define E1000_DEV_ID_82545GM_COPPER 0x1026
454 #define E1000_DEV_ID_82545GM_FIBER 0x1027
455 #define E1000_DEV_ID_82545GM_SERDES 0x1028
456 #define E1000_DEV_ID_82546EB_COPPER 0x1010
457 #define E1000_DEV_ID_82546EB_FIBER 0x1012
458 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
459 #define E1000_DEV_ID_82541EI 0x1013
460 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
461 #define E1000_DEV_ID_82541ER_LOM 0x1014
462 #define E1000_DEV_ID_82541ER 0x1078
463 #define E1000_DEV_ID_82547GI 0x1075
464 #define E1000_DEV_ID_82541GI 0x1076
465 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
466 #define E1000_DEV_ID_82541GI_LF 0x107C
467 #define E1000_DEV_ID_82546GB_COPPER 0x1079
468 #define E1000_DEV_ID_82546GB_FIBER 0x107A
469 #define E1000_DEV_ID_82546GB_SERDES 0x107B
470 #define E1000_DEV_ID_82546GB_PCIE 0x108A
471 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
472 #define E1000_DEV_ID_82547EI 0x1019
473 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
474 #define E1000_DEV_ID_82571EB_COPPER 0x105E
475 #define E1000_DEV_ID_82571EB_FIBER 0x105F
476 #define E1000_DEV_ID_82571EB_SERDES 0x1060
477 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
478 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
479 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
480 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
481 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
482 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
483 #define E1000_DEV_ID_82572EI_COPPER 0x107D
484 #define E1000_DEV_ID_82572EI_FIBER 0x107E
485 #define E1000_DEV_ID_82572EI_SERDES 0x107F
486 #define E1000_DEV_ID_82572EI 0x10B9
487 #define E1000_DEV_ID_82573E 0x108B
488 #define E1000_DEV_ID_82573E_IAMT 0x108C
489 #define E1000_DEV_ID_82573L 0x109A
490 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
491 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
492 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
493 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
494 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
495
496 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
497 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
498 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
499 #define E1000_DEV_ID_ICH8_IFE 0x104C
500 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
501 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
502 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
503
504
505 #define NODE_ADDRESS_SIZE 6
506 #define ETH_LENGTH_OF_ADDRESS 6
507
508 /* MAC decode size is 128K - This is the size of BAR0 */
509 #define MAC_DECODE_SIZE (128 * 1024)
510
511 #define E1000_82542_2_0_REV_ID 2
512 #define E1000_82542_2_1_REV_ID 3
513 #define E1000_REVISION_0 0
514 #define E1000_REVISION_1 1
515 #define E1000_REVISION_2 2
516 #define E1000_REVISION_3 3
517
518 #define SPEED_10 10
519 #define SPEED_100 100
520 #define SPEED_1000 1000
521 #define HALF_DUPLEX 1
522 #define FULL_DUPLEX 2
523
524 /* The sizes (in bytes) of a ethernet packet */
525 #define ENET_HEADER_SIZE 14
526 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
527 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
528 #define ETHERNET_FCS_SIZE 4
529 #define MAXIMUM_ETHERNET_PACKET_SIZE \
530 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
531 #define MINIMUM_ETHERNET_PACKET_SIZE \
532 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
533 #define CRC_LENGTH ETHERNET_FCS_SIZE
534 #define MAX_JUMBO_FRAME_SIZE 0x3F00
535
536
537 /* 802.1q VLAN Packet Sizes */
538 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
539
540 /* Ethertype field values */
541 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
542 #define ETHERNET_IP_TYPE 0x0800 /* IP packets */
543 #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
544
545 /* Packet Header defines */
546 #define IP_PROTOCOL_TCP 6
547 #define IP_PROTOCOL_UDP 0x11
548
549 /* This defines the bits that are set in the Interrupt Mask
550 * Set/Read Register. Each bit is documented below:
551 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
552 * o RXSEQ = Receive Sequence Error
553 */
554 #define POLL_IMS_ENABLE_MASK ( \
555 E1000_IMS_RXDMT0 | \
556 E1000_IMS_RXSEQ)
557
558 /* This defines the bits that are set in the Interrupt Mask
559 * Set/Read Register. Each bit is documented below:
560 * o RXT0 = Receiver Timer Interrupt (ring 0)
561 * o TXDW = Transmit Descriptor Written Back
562 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
563 * o RXSEQ = Receive Sequence Error
564 * o LSC = Link Status Change
565 */
566 #define IMS_ENABLE_MASK ( \
567 E1000_IMS_RXT0 | \
568 E1000_IMS_TXDW | \
569 E1000_IMS_RXDMT0 | \
570 E1000_IMS_RXSEQ | \
571 E1000_IMS_LSC)
572
573 /* Additional interrupts need to be handled for e1000_ich8lan:
574 DSW = The FW changed the status of the DISSW bit in FWSM
575 PHYINT = The LAN connected device generates an interrupt
576 EPRST = Manageability reset event */
577 #define IMS_ICH8LAN_ENABLE_MASK (\
578 E1000_IMS_DSW | \
579 E1000_IMS_PHYINT | \
580 E1000_IMS_EPRST)
581
582 /* Number of high/low register pairs in the RAR. The RAR (Receive Address
583 * Registers) holds the directed and multicast addresses that we monitor. We
584 * reserve one of these spots for our directed address, allowing us room for
585 * E1000_RAR_ENTRIES - 1 multicast addresses.
586 */
587 #define E1000_RAR_ENTRIES 15
588
589 #define E1000_RAR_ENTRIES_ICH8LAN 6
590
591 #define MIN_NUMBER_OF_DESCRIPTORS 8
592 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
593
594 /* Receive Descriptor */
595 struct e1000_rx_desc {
596 __le64 buffer_addr; /* Address of the descriptor's data buffer */
597 __le16 length; /* Length of data DMAed into data buffer */
598 __le16 csum; /* Packet checksum */
599 u8 status; /* Descriptor status */
600 u8 errors; /* Descriptor Errors */
601 __le16 special;
602 };
603
604 /* Receive Descriptor - Extended */
605 union e1000_rx_desc_extended {
606 struct {
607 __le64 buffer_addr;
608 __le64 reserved;
609 } read;
610 struct {
611 struct {
612 __le32 mrq; /* Multiple Rx Queues */
613 union {
614 __le32 rss; /* RSS Hash */
615 struct {
616 __le16 ip_id; /* IP id */
617 __le16 csum; /* Packet Checksum */
618 } csum_ip;
619 } hi_dword;
620 } lower;
621 struct {
622 __le32 status_error; /* ext status/error */
623 __le16 length;
624 __le16 vlan; /* VLAN tag */
625 } upper;
626 } wb; /* writeback */
627 };
628
629 #define MAX_PS_BUFFERS 4
630 /* Receive Descriptor - Packet Split */
631 union e1000_rx_desc_packet_split {
632 struct {
633 /* one buffer for protocol header(s), three data buffers */
634 __le64 buffer_addr[MAX_PS_BUFFERS];
635 } read;
636 struct {
637 struct {
638 __le32 mrq; /* Multiple Rx Queues */
639 union {
640 __le32 rss; /* RSS Hash */
641 struct {
642 __le16 ip_id; /* IP id */
643 __le16 csum; /* Packet Checksum */
644 } csum_ip;
645 } hi_dword;
646 } lower;
647 struct {
648 __le32 status_error; /* ext status/error */
649 __le16 length0; /* length of buffer 0 */
650 __le16 vlan; /* VLAN tag */
651 } middle;
652 struct {
653 __le16 header_status;
654 __le16 length[3]; /* length of buffers 1-3 */
655 } upper;
656 __le64 reserved;
657 } wb; /* writeback */
658 };
659
660 /* Receive Decriptor bit definitions */
661 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
662 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
663 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
664 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
665 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
666 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
667 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
668 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
669 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
670 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
671 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
672 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
673 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
674 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
675 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
676 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
677 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
678 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
679 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
680 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
681 #define E1000_RXD_SPC_PRI_SHIFT 13
682 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
683 #define E1000_RXD_SPC_CFI_SHIFT 12
684
685 #define E1000_RXDEXT_STATERR_CE 0x01000000
686 #define E1000_RXDEXT_STATERR_SE 0x02000000
687 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
688 #define E1000_RXDEXT_STATERR_CXE 0x10000000
689 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
690 #define E1000_RXDEXT_STATERR_IPE 0x40000000
691 #define E1000_RXDEXT_STATERR_RXE 0x80000000
692
693 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
694 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
695
696 /* mask to determine if packets should be dropped due to frame errors */
697 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
698 E1000_RXD_ERR_CE | \
699 E1000_RXD_ERR_SE | \
700 E1000_RXD_ERR_SEQ | \
701 E1000_RXD_ERR_CXE | \
702 E1000_RXD_ERR_RXE)
703
704
705 /* Same mask, but for extended and packet split descriptors */
706 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
707 E1000_RXDEXT_STATERR_CE | \
708 E1000_RXDEXT_STATERR_SE | \
709 E1000_RXDEXT_STATERR_SEQ | \
710 E1000_RXDEXT_STATERR_CXE | \
711 E1000_RXDEXT_STATERR_RXE)
712
713
714 /* Transmit Descriptor */
715 struct e1000_tx_desc {
716 __le64 buffer_addr; /* Address of the descriptor's data buffer */
717 union {
718 __le32 data;
719 struct {
720 __le16 length; /* Data buffer length */
721 u8 cso; /* Checksum offset */
722 u8 cmd; /* Descriptor control */
723 } flags;
724 } lower;
725 union {
726 __le32 data;
727 struct {
728 u8 status; /* Descriptor status */
729 u8 css; /* Checksum start */
730 __le16 special;
731 } fields;
732 } upper;
733 };
734
735 /* Transmit Descriptor bit definitions */
736 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
737 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
738 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
739 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
740 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
741 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
742 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
743 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
744 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
745 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
746 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
747 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
748 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
749 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
750 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
751 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
752 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
753 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
754 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
755 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
756
757 /* Offload Context Descriptor */
758 struct e1000_context_desc {
759 union {
760 __le32 ip_config;
761 struct {
762 u8 ipcss; /* IP checksum start */
763 u8 ipcso; /* IP checksum offset */
764 __le16 ipcse; /* IP checksum end */
765 } ip_fields;
766 } lower_setup;
767 union {
768 __le32 tcp_config;
769 struct {
770 u8 tucss; /* TCP checksum start */
771 u8 tucso; /* TCP checksum offset */
772 __le16 tucse; /* TCP checksum end */
773 } tcp_fields;
774 } upper_setup;
775 __le32 cmd_and_length; /* */
776 union {
777 __le32 data;
778 struct {
779 u8 status; /* Descriptor status */
780 u8 hdr_len; /* Header length */
781 __le16 mss; /* Maximum segment size */
782 } fields;
783 } tcp_seg_setup;
784 };
785
786 /* Offload data descriptor */
787 struct e1000_data_desc {
788 __le64 buffer_addr; /* Address of the descriptor's buffer address */
789 union {
790 __le32 data;
791 struct {
792 __le16 length; /* Data buffer length */
793 u8 typ_len_ext; /* */
794 u8 cmd; /* */
795 } flags;
796 } lower;
797 union {
798 __le32 data;
799 struct {
800 u8 status; /* Descriptor status */
801 u8 popts; /* Packet Options */
802 __le16 special; /* */
803 } fields;
804 } upper;
805 };
806
807 /* Filters */
808 #define E1000_NUM_UNICAST 16 /* Unicast filter entries */
809 #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
810 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
811
812 #define E1000_NUM_UNICAST_ICH8LAN 7
813 #define E1000_MC_TBL_SIZE_ICH8LAN 32
814
815
816 /* Receive Address Register */
817 struct e1000_rar {
818 volatile __le32 low; /* receive address low */
819 volatile __le32 high; /* receive address high */
820 };
821
822 /* Number of entries in the Multicast Table Array (MTA). */
823 #define E1000_NUM_MTA_REGISTERS 128
824 #define E1000_NUM_MTA_REGISTERS_ICH8LAN 32
825
826 /* IPv4 Address Table Entry */
827 struct e1000_ipv4_at_entry {
828 volatile u32 ipv4_addr; /* IP Address (RW) */
829 volatile u32 reserved;
830 };
831
832 /* Four wakeup IP addresses are supported */
833 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
834 #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
835 #define E1000_IP4AT_SIZE_ICH8LAN 3
836 #define E1000_IP6AT_SIZE 1
837
838 /* IPv6 Address Table Entry */
839 struct e1000_ipv6_at_entry {
840 volatile u8 ipv6_addr[16];
841 };
842
843 /* Flexible Filter Length Table Entry */
844 struct e1000_fflt_entry {
845 volatile u32 length; /* Flexible Filter Length (RW) */
846 volatile u32 reserved;
847 };
848
849 /* Flexible Filter Mask Table Entry */
850 struct e1000_ffmt_entry {
851 volatile u32 mask; /* Flexible Filter Mask (RW) */
852 volatile u32 reserved;
853 };
854
855 /* Flexible Filter Value Table Entry */
856 struct e1000_ffvt_entry {
857 volatile u32 value; /* Flexible Filter Value (RW) */
858 volatile u32 reserved;
859 };
860
861 /* Four Flexible Filters are supported */
862 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
863
864 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
865 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
866
867 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
868 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
869 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
870
871 #define E1000_DISABLE_SERDES_LOOPBACK 0x0400
872
873 /* Register Set. (82543, 82544)
874 *
875 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
876 * These registers are physically located on the NIC, but are mapped into the
877 * host memory address space.
878 *
879 * RW - register is both readable and writable
880 * RO - register is read only
881 * WO - register is write only
882 * R/clr - register is read only and is cleared when read
883 * A - register array
884 */
885 #define E1000_CTRL 0x00000 /* Device Control - RW */
886 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
887 #define E1000_STATUS 0x00008 /* Device Status - RO */
888 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
889 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
890 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
891 #define E1000_FLA 0x0001C /* Flash Access - RW */
892 #define E1000_MDIC 0x00020 /* MDI Control - RW */
893 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
894 #define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
895 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
896 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
897 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
898 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
899 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
900 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
901 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
902 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
903 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
904 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
905 #define E1000_RCTL 0x00100 /* RX Control - RW */
906 #define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
907 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
908 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
909 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
910 #define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
911 #define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
912 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
913 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
914 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
915 #define E1000_TCTL 0x00400 /* TX Control - RW */
916 #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
917 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
918 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */
919 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
920 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
921 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
922 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
923 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
924 #define FEXTNVM_SW_CONFIG 0x0001
925 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
926 #define E1000_PBS 0x01008 /* Packet Buffer Size */
927 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
928 #define E1000_FLASH_UPDATES 1000
929 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
930 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */
931 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
932 #define E1000_FLSWCTL 0x01030 /* FLASH control register */
933 #define E1000_FLSWDATA 0x01034 /* FLASH data register */
934 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
935 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */
936 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
937 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
938 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
939 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
940 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
941 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
942 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
943 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
944 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
945 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
946 #define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
947 #define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
948 #define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
949 #define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
950 #define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
951 #define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
952 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
953 #define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
954 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
955 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
956 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
957 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
958 #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
959 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
960 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
961 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
962 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
963 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
964 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
965 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
966 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
967 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
968 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
969 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
970 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
971 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
972 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
973 #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
974 #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
975 #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
976 #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
977 #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
978 #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
979 #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
980 #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
981 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
982 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
983 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
984 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
985 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
986 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
987 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
988 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
989 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
990 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
991 #define E1000_DC 0x04030 /* Defer Count - R/clr */
992 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
993 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
994 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
995 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
996 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
997 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
998 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
999 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
1000 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
1001 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
1002 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
1003 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
1004 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
1005 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
1006 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
1007 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
1008 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
1009 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
1010 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
1011 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
1012 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
1013 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
1014 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
1015 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
1016 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
1017 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
1018 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
1019 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
1020 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
1021 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
1022 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
1023 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
1024 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
1025 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
1026 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
1027 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
1028 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
1029 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
1030 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
1031 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
1032 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
1033 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
1034 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
1035 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
1036 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
1037 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
1038 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
1039 #define E1000_IAC 0x04100 /* Interrupt Assertion Count */
1040 #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
1041 #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
1042 #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
1043 #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
1044 #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
1045 #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
1046 #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
1047 #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
1048 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
1049 #define E1000_RFCTL 0x05008 /* Receive Filter Control*/
1050 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
1051 #define E1000_RA 0x05400 /* Receive Address - RW Array */
1052 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
1053 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
1054 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
1055 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
1056 #define E1000_MANC 0x05820 /* Management Control - RW */
1057 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
1058 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
1059 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
1060 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
1061 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
1062 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
1063 #define E1000_HOST_IF 0x08800 /* Host Interface */
1064 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
1065 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
1066
1067 #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
1068 #define E1000_MDPHYA 0x0003C /* PHY address - RW */
1069 #define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */
1070 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
1071
1072 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
1073 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1074 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1075 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1076 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1077 #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1078 #define E1000_SWSM 0x05B50 /* SW Semaphore */
1079 #define E1000_FWSM 0x05B54 /* FW Semaphore */
1080 #define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1081 #define E1000_HICR 0x08F00 /* Host Inteface Control */
1082
1083 /* RSS registers */
1084 #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1085 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1086 #define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1087 #define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1088 #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
1089 #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
1090 /* Register Set (82542)
1091 *
1092 * Some of the 82542 registers are located at different offsets than they are
1093 * in more current versions of the 8254x. Despite the difference in location,
1094 * the registers function in the same manner.
1095 */
1096 #define E1000_82542_CTRL E1000_CTRL
1097 #define E1000_82542_CTRL_DUP E1000_CTRL_DUP
1098 #define E1000_82542_STATUS E1000_STATUS
1099 #define E1000_82542_EECD E1000_EECD
1100 #define E1000_82542_EERD E1000_EERD
1101 #define E1000_82542_CTRL_EXT E1000_CTRL_EXT
1102 #define E1000_82542_FLA E1000_FLA
1103 #define E1000_82542_MDIC E1000_MDIC
1104 #define E1000_82542_SCTL E1000_SCTL
1105 #define E1000_82542_FEXTNVM E1000_FEXTNVM
1106 #define E1000_82542_FCAL E1000_FCAL
1107 #define E1000_82542_FCAH E1000_FCAH
1108 #define E1000_82542_FCT E1000_FCT
1109 #define E1000_82542_VET E1000_VET
1110 #define E1000_82542_RA 0x00040
1111 #define E1000_82542_ICR E1000_ICR
1112 #define E1000_82542_ITR E1000_ITR
1113 #define E1000_82542_ICS E1000_ICS
1114 #define E1000_82542_IMS E1000_IMS
1115 #define E1000_82542_IMC E1000_IMC
1116 #define E1000_82542_RCTL E1000_RCTL
1117 #define E1000_82542_RDTR 0x00108
1118 #define E1000_82542_RDBAL 0x00110
1119 #define E1000_82542_RDBAH 0x00114
1120 #define E1000_82542_RDLEN 0x00118
1121 #define E1000_82542_RDH 0x00120
1122 #define E1000_82542_RDT 0x00128
1123 #define E1000_82542_RDTR0 E1000_82542_RDTR
1124 #define E1000_82542_RDBAL0 E1000_82542_RDBAL
1125 #define E1000_82542_RDBAH0 E1000_82542_RDBAH
1126 #define E1000_82542_RDLEN0 E1000_82542_RDLEN
1127 #define E1000_82542_RDH0 E1000_82542_RDH
1128 #define E1000_82542_RDT0 E1000_82542_RDT
1129 #define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
1130 * RX Control - RW */
1131 #define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1132 #define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1133 #define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1134 #define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1135 #define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1136 #define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1137 #define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1138 #define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1139 #define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1140 #define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1141 #define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
1142 #define E1000_82542_RDTR1 0x00130
1143 #define E1000_82542_RDBAL1 0x00138
1144 #define E1000_82542_RDBAH1 0x0013C
1145 #define E1000_82542_RDLEN1 0x00140
1146 #define E1000_82542_RDH1 0x00148
1147 #define E1000_82542_RDT1 0x00150
1148 #define E1000_82542_FCRTH 0x00160
1149 #define E1000_82542_FCRTL 0x00168
1150 #define E1000_82542_FCTTV E1000_FCTTV
1151 #define E1000_82542_TXCW E1000_TXCW
1152 #define E1000_82542_RXCW E1000_RXCW
1153 #define E1000_82542_MTA 0x00200
1154 #define E1000_82542_TCTL E1000_TCTL
1155 #define E1000_82542_TCTL_EXT E1000_TCTL_EXT
1156 #define E1000_82542_TIPG E1000_TIPG
1157 #define E1000_82542_TDBAL 0x00420
1158 #define E1000_82542_TDBAH 0x00424
1159 #define E1000_82542_TDLEN 0x00428
1160 #define E1000_82542_TDH 0x00430
1161 #define E1000_82542_TDT 0x00438
1162 #define E1000_82542_TIDV 0x00440
1163 #define E1000_82542_TBT E1000_TBT
1164 #define E1000_82542_AIT E1000_AIT
1165 #define E1000_82542_VFTA 0x00600
1166 #define E1000_82542_LEDCTL E1000_LEDCTL
1167 #define E1000_82542_PBA E1000_PBA
1168 #define E1000_82542_PBS E1000_PBS
1169 #define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1170 #define E1000_82542_EEARBC E1000_EEARBC
1171 #define E1000_82542_FLASHT E1000_FLASHT
1172 #define E1000_82542_EEWR E1000_EEWR
1173 #define E1000_82542_FLSWCTL E1000_FLSWCTL
1174 #define E1000_82542_FLSWDATA E1000_FLSWDATA
1175 #define E1000_82542_FLSWCNT E1000_FLSWCNT
1176 #define E1000_82542_FLOP E1000_FLOP
1177 #define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1178 #define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1179 #define E1000_82542_PHY_CTRL E1000_PHY_CTRL
1180 #define E1000_82542_ERT E1000_ERT
1181 #define E1000_82542_RXDCTL E1000_RXDCTL
1182 #define E1000_82542_RXDCTL1 E1000_RXDCTL1
1183 #define E1000_82542_RADV E1000_RADV
1184 #define E1000_82542_RSRPD E1000_RSRPD
1185 #define E1000_82542_TXDMAC E1000_TXDMAC
1186 #define E1000_82542_KABGTXD E1000_KABGTXD
1187 #define E1000_82542_TDFHS E1000_TDFHS
1188 #define E1000_82542_TDFTS E1000_TDFTS
1189 #define E1000_82542_TDFPC E1000_TDFPC
1190 #define E1000_82542_TXDCTL E1000_TXDCTL
1191 #define E1000_82542_TADV E1000_TADV
1192 #define E1000_82542_TSPMT E1000_TSPMT
1193 #define E1000_82542_CRCERRS E1000_CRCERRS
1194 #define E1000_82542_ALGNERRC E1000_ALGNERRC
1195 #define E1000_82542_SYMERRS E1000_SYMERRS
1196 #define E1000_82542_RXERRC E1000_RXERRC
1197 #define E1000_82542_MPC E1000_MPC
1198 #define E1000_82542_SCC E1000_SCC
1199 #define E1000_82542_ECOL E1000_ECOL
1200 #define E1000_82542_MCC E1000_MCC
1201 #define E1000_82542_LATECOL E1000_LATECOL
1202 #define E1000_82542_COLC E1000_COLC
1203 #define E1000_82542_DC E1000_DC
1204 #define E1000_82542_TNCRS E1000_TNCRS
1205 #define E1000_82542_SEC E1000_SEC
1206 #define E1000_82542_CEXTERR E1000_CEXTERR
1207 #define E1000_82542_RLEC E1000_RLEC
1208 #define E1000_82542_XONRXC E1000_XONRXC
1209 #define E1000_82542_XONTXC E1000_XONTXC
1210 #define E1000_82542_XOFFRXC E1000_XOFFRXC
1211 #define E1000_82542_XOFFTXC E1000_XOFFTXC
1212 #define E1000_82542_FCRUC E1000_FCRUC
1213 #define E1000_82542_PRC64 E1000_PRC64
1214 #define E1000_82542_PRC127 E1000_PRC127
1215 #define E1000_82542_PRC255 E1000_PRC255
1216 #define E1000_82542_PRC511 E1000_PRC511
1217 #define E1000_82542_PRC1023 E1000_PRC1023
1218 #define E1000_82542_PRC1522 E1000_PRC1522
1219 #define E1000_82542_GPRC E1000_GPRC
1220 #define E1000_82542_BPRC E1000_BPRC
1221 #define E1000_82542_MPRC E1000_MPRC
1222 #define E1000_82542_GPTC E1000_GPTC
1223 #define E1000_82542_GORCL E1000_GORCL
1224 #define E1000_82542_GORCH E1000_GORCH
1225 #define E1000_82542_GOTCL E1000_GOTCL
1226 #define E1000_82542_GOTCH E1000_GOTCH
1227 #define E1000_82542_RNBC E1000_RNBC
1228 #define E1000_82542_RUC E1000_RUC
1229 #define E1000_82542_RFC E1000_RFC
1230 #define E1000_82542_ROC E1000_ROC
1231 #define E1000_82542_RJC E1000_RJC
1232 #define E1000_82542_MGTPRC E1000_MGTPRC
1233 #define E1000_82542_MGTPDC E1000_MGTPDC
1234 #define E1000_82542_MGTPTC E1000_MGTPTC
1235 #define E1000_82542_TORL E1000_TORL
1236 #define E1000_82542_TORH E1000_TORH
1237 #define E1000_82542_TOTL E1000_TOTL
1238 #define E1000_82542_TOTH E1000_TOTH
1239 #define E1000_82542_TPR E1000_TPR
1240 #define E1000_82542_TPT E1000_TPT
1241 #define E1000_82542_PTC64 E1000_PTC64
1242 #define E1000_82542_PTC127 E1000_PTC127
1243 #define E1000_82542_PTC255 E1000_PTC255
1244 #define E1000_82542_PTC511 E1000_PTC511
1245 #define E1000_82542_PTC1023 E1000_PTC1023
1246 #define E1000_82542_PTC1522 E1000_PTC1522
1247 #define E1000_82542_MPTC E1000_MPTC
1248 #define E1000_82542_BPTC E1000_BPTC
1249 #define E1000_82542_TSCTC E1000_TSCTC
1250 #define E1000_82542_TSCTFC E1000_TSCTFC
1251 #define E1000_82542_RXCSUM E1000_RXCSUM
1252 #define E1000_82542_WUC E1000_WUC
1253 #define E1000_82542_WUFC E1000_WUFC
1254 #define E1000_82542_WUS E1000_WUS
1255 #define E1000_82542_MANC E1000_MANC
1256 #define E1000_82542_IPAV E1000_IPAV
1257 #define E1000_82542_IP4AT E1000_IP4AT
1258 #define E1000_82542_IP6AT E1000_IP6AT
1259 #define E1000_82542_WUPL E1000_WUPL
1260 #define E1000_82542_WUPM E1000_WUPM
1261 #define E1000_82542_FFLT E1000_FFLT
1262 #define E1000_82542_TDFH 0x08010
1263 #define E1000_82542_TDFT 0x08018
1264 #define E1000_82542_FFMT E1000_FFMT
1265 #define E1000_82542_FFVT E1000_FFVT
1266 #define E1000_82542_HOST_IF E1000_HOST_IF
1267 #define E1000_82542_IAM E1000_IAM
1268 #define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1269 #define E1000_82542_PSRCTL E1000_PSRCTL
1270 #define E1000_82542_RAID E1000_RAID
1271 #define E1000_82542_TARC0 E1000_TARC0
1272 #define E1000_82542_TDBAL1 E1000_TDBAL1
1273 #define E1000_82542_TDBAH1 E1000_TDBAH1
1274 #define E1000_82542_TDLEN1 E1000_TDLEN1
1275 #define E1000_82542_TDH1 E1000_TDH1
1276 #define E1000_82542_TDT1 E1000_TDT1
1277 #define E1000_82542_TXDCTL1 E1000_TXDCTL1
1278 #define E1000_82542_TARC1 E1000_TARC1
1279 #define E1000_82542_RFCTL E1000_RFCTL
1280 #define E1000_82542_GCR E1000_GCR
1281 #define E1000_82542_GSCL_1 E1000_GSCL_1
1282 #define E1000_82542_GSCL_2 E1000_GSCL_2
1283 #define E1000_82542_GSCL_3 E1000_GSCL_3
1284 #define E1000_82542_GSCL_4 E1000_GSCL_4
1285 #define E1000_82542_FACTPS E1000_FACTPS
1286 #define E1000_82542_SWSM E1000_SWSM
1287 #define E1000_82542_FWSM E1000_FWSM
1288 #define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1289 #define E1000_82542_IAC E1000_IAC
1290 #define E1000_82542_ICRXPTC E1000_ICRXPTC
1291 #define E1000_82542_ICRXATC E1000_ICRXATC
1292 #define E1000_82542_ICTXPTC E1000_ICTXPTC
1293 #define E1000_82542_ICTXATC E1000_ICTXATC
1294 #define E1000_82542_ICTXQEC E1000_ICTXQEC
1295 #define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1296 #define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1297 #define E1000_82542_ICRXOC E1000_ICRXOC
1298 #define E1000_82542_HICR E1000_HICR
1299
1300 #define E1000_82542_CPUVEC E1000_CPUVEC
1301 #define E1000_82542_MRQC E1000_MRQC
1302 #define E1000_82542_RETA E1000_RETA
1303 #define E1000_82542_RSSRK E1000_RSSRK
1304 #define E1000_82542_RSSIM E1000_RSSIM
1305 #define E1000_82542_RSSIR E1000_RSSIR
1306 #define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
1307 #define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC
1308 #define E1000_82542_MANC2H E1000_MANC2H
1309
1310 /* Statistics counters collected by the MAC */
1311 struct e1000_hw_stats {
1312 u64 crcerrs;
1313 u64 algnerrc;
1314 u64 symerrs;
1315 u64 rxerrc;
1316 u64 txerrc;
1317 u64 mpc;
1318 u64 scc;
1319 u64 ecol;
1320 u64 mcc;
1321 u64 latecol;
1322 u64 colc;
1323 u64 dc;
1324 u64 tncrs;
1325 u64 sec;
1326 u64 cexterr;
1327 u64 rlec;
1328 u64 xonrxc;
1329 u64 xontxc;
1330 u64 xoffrxc;
1331 u64 xofftxc;
1332 u64 fcruc;
1333 u64 prc64;
1334 u64 prc127;
1335 u64 prc255;
1336 u64 prc511;
1337 u64 prc1023;
1338 u64 prc1522;
1339 u64 gprc;
1340 u64 bprc;
1341 u64 mprc;
1342 u64 gptc;
1343 u64 gorcl;
1344 u64 gorch;
1345 u64 gotcl;
1346 u64 gotch;
1347 u64 rnbc;
1348 u64 ruc;
1349 u64 rfc;
1350 u64 roc;
1351 u64 rlerrc;
1352 u64 rjc;
1353 u64 mgprc;
1354 u64 mgpdc;
1355 u64 mgptc;
1356 u64 torl;
1357 u64 torh;
1358 u64 totl;
1359 u64 toth;
1360 u64 tpr;
1361 u64 tpt;
1362 u64 ptc64;
1363 u64 ptc127;
1364 u64 ptc255;
1365 u64 ptc511;
1366 u64 ptc1023;
1367 u64 ptc1522;
1368 u64 mptc;
1369 u64 bptc;
1370 u64 tsctc;
1371 u64 tsctfc;
1372 u64 iac;
1373 u64 icrxptc;
1374 u64 icrxatc;
1375 u64 ictxptc;
1376 u64 ictxatc;
1377 u64 ictxqec;
1378 u64 ictxqmtc;
1379 u64 icrxdmtc;
1380 u64 icrxoc;
1381 };
1382
1383 /* Structure containing variables used by the shared code (e1000_hw.c) */
1384 struct e1000_hw {
1385 u8 __iomem *hw_addr;
1386 u8 __iomem *flash_address;
1387 e1000_mac_type mac_type;
1388 e1000_phy_type phy_type;
1389 u32 phy_init_script;
1390 e1000_media_type media_type;
1391 void *back;
1392 struct e1000_shadow_ram *eeprom_shadow_ram;
1393 u32 flash_bank_size;
1394 u32 flash_base_addr;
1395 e1000_fc_type fc;
1396 e1000_bus_speed bus_speed;
1397 e1000_bus_width bus_width;
1398 e1000_bus_type bus_type;
1399 struct e1000_eeprom_info eeprom;
1400 e1000_ms_type master_slave;
1401 e1000_ms_type original_master_slave;
1402 e1000_ffe_config ffe_config_state;
1403 u32 asf_firmware_present;
1404 u32 eeprom_semaphore_present;
1405 u32 swfw_sync_present;
1406 u32 swfwhw_semaphore_present;
1407 unsigned long io_base;
1408 u32 phy_id;
1409 u32 phy_revision;
1410 u32 phy_addr;
1411 u32 original_fc;
1412 u32 txcw;
1413 u32 autoneg_failed;
1414 u32 max_frame_size;
1415 u32 min_frame_size;
1416 u32 mc_filter_type;
1417 u32 num_mc_addrs;
1418 u32 collision_delta;
1419 u32 tx_packet_delta;
1420 u32 ledctl_default;
1421 u32 ledctl_mode1;
1422 u32 ledctl_mode2;
1423 bool tx_pkt_filtering;
1424 struct e1000_host_mng_dhcp_cookie mng_cookie;
1425 u16 phy_spd_default;
1426 u16 autoneg_advertised;
1427 u16 pci_cmd_word;
1428 u16 fc_high_water;
1429 u16 fc_low_water;
1430 u16 fc_pause_time;
1431 u16 current_ifs_val;
1432 u16 ifs_min_val;
1433 u16 ifs_max_val;
1434 u16 ifs_step_size;
1435 u16 ifs_ratio;
1436 u16 device_id;
1437 u16 vendor_id;
1438 u16 subsystem_id;
1439 u16 subsystem_vendor_id;
1440 u8 revision_id;
1441 u8 autoneg;
1442 u8 mdix;
1443 u8 forced_speed_duplex;
1444 u8 wait_autoneg_complete;
1445 u8 dma_fairness;
1446 u8 mac_addr[NODE_ADDRESS_SIZE];
1447 u8 perm_mac_addr[NODE_ADDRESS_SIZE];
1448 bool disable_polarity_correction;
1449 bool speed_downgraded;
1450 e1000_smart_speed smart_speed;
1451 e1000_dsp_config dsp_config_state;
1452 bool get_link_status;
1453 bool serdes_link_down;
1454 bool tbi_compatibility_en;
1455 bool tbi_compatibility_on;
1456 bool laa_is_present;
1457 bool phy_reset_disable;
1458 bool initialize_hw_bits_disable;
1459 bool fc_send_xon;
1460 bool fc_strict_ieee;
1461 bool report_tx_early;
1462 bool adaptive_ifs;
1463 bool ifs_params_forced;
1464 bool in_ifs_mode;
1465 bool mng_reg_access_disabled;
1466 bool leave_av_bit_off;
1467 bool kmrn_lock_loss_workaround_disabled;
1468 bool bad_tx_carr_stats_fd;
1469 bool has_manc2h;
1470 bool rx_needs_kicking;
1471 bool has_smbus;
1472 };
1473
1474
1475 #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1476 #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1477 #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1478 #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1479 #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1480 #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1481 #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1482 #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1483 /* Register Bit Masks */
1484 /* Device Control */
1485 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1486 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1487 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1488 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1489 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1490 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1491 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1492 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1493 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1494 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1495 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1496 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1497 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1498 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1499 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1500 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1501 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1502 #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
1503 #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1504 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
1505 #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
1506 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1507 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1508 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1509 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1510 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1511 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1512 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1513 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1514 #define E1000_CTRL_RST 0x04000000 /* Global reset */
1515 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1516 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1517 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1518 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1519 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1520 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1521
1522 /* Device Status */
1523 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1524 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1525 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1526 #define E1000_STATUS_FUNC_SHIFT 2
1527 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1528 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1529 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1530 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1531 #define E1000_STATUS_SPEED_MASK 0x000000C0
1532 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1533 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1534 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1535 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
1536 by EEPROM/Flash */
1537 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1538 #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1539 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1540 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1541 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1542 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1543 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1544 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1545 #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
1546 #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
1547 #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
1548 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
1549 #define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
1550 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
1551 #define E1000_STATUS_FUSE_8 0x04000000
1552 #define E1000_STATUS_FUSE_9 0x08000000
1553 #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
1554 #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
1555
1556 /* Constants used to intrepret the masked PCI-X bus speed. */
1557 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1558 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1559 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1560
1561 /* EEPROM/Flash Control */
1562 #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1563 #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1564 #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1565 #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1566 #define E1000_EECD_FWE_MASK 0x00000030
1567 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1568 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1569 #define E1000_EECD_FWE_SHIFT 4
1570 #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1571 #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1572 #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1573 #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1574 #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1575 * (0-small, 1-large) */
1576 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1577 #ifndef E1000_EEPROM_GRANT_ATTEMPTS
1578 #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1579 #endif
1580 #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1581 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1582 #define E1000_EECD_SIZE_EX_SHIFT 11
1583 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1584 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1585 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1586 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1587 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1588 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1589 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1590 #define E1000_EECD_SECVAL_SHIFT 22
1591 #define E1000_STM_OPCODE 0xDB00
1592 #define E1000_HICR_FW_RESET 0xC0
1593
1594 #define E1000_SHADOW_RAM_WORDS 2048
1595 #define E1000_ICH_NVM_SIG_WORD 0x13
1596 #define E1000_ICH_NVM_SIG_MASK 0xC0
1597
1598 /* EEPROM Read */
1599 #define E1000_EERD_START 0x00000001 /* Start Read */
1600 #define E1000_EERD_DONE 0x00000010 /* Read Done */
1601 #define E1000_EERD_ADDR_SHIFT 8
1602 #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1603 #define E1000_EERD_DATA_SHIFT 16
1604 #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1605
1606 /* SPI EEPROM Status Register */
1607 #define EEPROM_STATUS_RDY_SPI 0x01
1608 #define EEPROM_STATUS_WEN_SPI 0x02
1609 #define EEPROM_STATUS_BP0_SPI 0x04
1610 #define EEPROM_STATUS_BP1_SPI 0x08
1611 #define EEPROM_STATUS_WPEN_SPI 0x80
1612
1613 /* Extended Device Control */
1614 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1615 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1616 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1617 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1618 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1619 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1620 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1621 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1622 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1623 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1624 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1625 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1626 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1627 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1628 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1629 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1630 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1631 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1632 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1633 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1634 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1635 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1636 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
1637 #define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000
1638 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
1639 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1640 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1641 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1642 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1643 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1644 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1645 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1646 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1647 #define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
1648 #define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
1649 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
1650
1651 /* MDI Control */
1652 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1653 #define E1000_MDIC_REG_MASK 0x001F0000
1654 #define E1000_MDIC_REG_SHIFT 16
1655 #define E1000_MDIC_PHY_MASK 0x03E00000
1656 #define E1000_MDIC_PHY_SHIFT 21
1657 #define E1000_MDIC_OP_WRITE 0x04000000
1658 #define E1000_MDIC_OP_READ 0x08000000
1659 #define E1000_MDIC_READY 0x10000000
1660 #define E1000_MDIC_INT_EN 0x20000000
1661 #define E1000_MDIC_ERROR 0x40000000
1662
1663 #define E1000_KUMCTRLSTA_MASK 0x0000FFFF
1664 #define E1000_KUMCTRLSTA_OFFSET 0x001F0000
1665 #define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
1666 #define E1000_KUMCTRLSTA_REN 0x00200000
1667
1668 #define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
1669 #define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
1670 #define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
1671 #define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
1672 #define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
1673 #define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
1674 #define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
1675 #define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
1676 #define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
1677
1678 /* FIFO Control */
1679 #define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
1680 #define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1681
1682 /* In-Band Control */
1683 #define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
1684 #define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1685
1686 /* Half-Duplex Control */
1687 #define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1688 #define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1689
1690 #define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
1691
1692 #define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
1693 #define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
1694
1695 #define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
1696 #define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
1697 #define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
1698
1699 #define E1000_KABGTXD_BGSQLBIAS 0x00050000
1700
1701 #define E1000_PHY_CTRL_SPD_EN 0x00000001
1702 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1703 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1704 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1705 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1706 #define E1000_PHY_CTRL_B2B_EN 0x00000080
1707
1708 /* LED Control */
1709 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1710 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
1711 #define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
1712 #define E1000_LEDCTL_LED0_IVRT 0x00000040
1713 #define E1000_LEDCTL_LED0_BLINK 0x00000080
1714 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1715 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
1716 #define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
1717 #define E1000_LEDCTL_LED1_IVRT 0x00004000
1718 #define E1000_LEDCTL_LED1_BLINK 0x00008000
1719 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1720 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
1721 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
1722 #define E1000_LEDCTL_LED2_IVRT 0x00400000
1723 #define E1000_LEDCTL_LED2_BLINK 0x00800000
1724 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1725 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
1726 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
1727 #define E1000_LEDCTL_LED3_IVRT 0x40000000
1728 #define E1000_LEDCTL_LED3_BLINK 0x80000000
1729
1730 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1731 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1732 #define E1000_LEDCTL_MODE_LINK_UP 0x2
1733 #define E1000_LEDCTL_MODE_ACTIVITY 0x3
1734 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1735 #define E1000_LEDCTL_MODE_LINK_10 0x5
1736 #define E1000_LEDCTL_MODE_LINK_100 0x6
1737 #define E1000_LEDCTL_MODE_LINK_1000 0x7
1738 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1739 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1740 #define E1000_LEDCTL_MODE_COLLISION 0xA
1741 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1742 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1743 #define E1000_LEDCTL_MODE_PAUSED 0xD
1744 #define E1000_LEDCTL_MODE_LED_ON 0xE
1745 #define E1000_LEDCTL_MODE_LED_OFF 0xF
1746
1747 /* Receive Address */
1748 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1749
1750 /* Interrupt Cause Read */
1751 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1752 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1753 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1754 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1755 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1756 #define E1000_ICR_RXO 0x00000040 /* rx overrun */
1757 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1758 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1759 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1760 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1761 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1762 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1763 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1764 #define E1000_ICR_TXD_LOW 0x00008000
1765 #define E1000_ICR_SRPD 0x00010000
1766 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1767 #define E1000_ICR_MNG 0x00040000 /* Manageability event */
1768 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1769 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1770 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
1771 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
1772 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
1773 #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
1774 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1775 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1776 #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
1777 #define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
1778 #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
1779 #define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */
1780
1781 /* Interrupt Cause Set */
1782 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1783 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1784 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1785 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1786 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1787 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1788 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1789 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1790 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1791 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1792 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1793 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1794 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1795 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1796 #define E1000_ICS_SRPD E1000_ICR_SRPD
1797 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1798 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1799 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1800 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1801 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1802 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1803 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1804 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1805 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1806 #define E1000_ICS_DSW E1000_ICR_DSW
1807 #define E1000_ICS_PHYINT E1000_ICR_PHYINT
1808 #define E1000_ICS_EPRST E1000_ICR_EPRST
1809
1810 /* Interrupt Mask Set */
1811 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1812 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1813 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1814 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1815 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1816 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1817 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1818 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1819 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1820 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1821 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1822 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1823 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1824 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1825 #define E1000_IMS_SRPD E1000_ICR_SRPD
1826 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1827 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1828 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1829 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1830 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1831 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1832 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1833 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1834 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1835 #define E1000_IMS_DSW E1000_ICR_DSW
1836 #define E1000_IMS_PHYINT E1000_ICR_PHYINT
1837 #define E1000_IMS_EPRST E1000_ICR_EPRST
1838
1839 /* Interrupt Mask Clear */
1840 #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1841 #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1842 #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1843 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1844 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1845 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1846 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1847 #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1848 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1849 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1850 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1851 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1852 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1853 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1854 #define E1000_IMC_SRPD E1000_ICR_SRPD
1855 #define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1856 #define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1857 #define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
1858 #define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1859 #define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1860 #define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1861 #define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1862 #define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1863 #define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1864 #define E1000_IMC_DSW E1000_ICR_DSW
1865 #define E1000_IMC_PHYINT E1000_ICR_PHYINT
1866 #define E1000_IMC_EPRST E1000_ICR_EPRST
1867
1868 /* Receive Control */
1869 #define E1000_RCTL_RST 0x00000001 /* Software reset */
1870 #define E1000_RCTL_EN 0x00000002 /* enable */
1871 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1872 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1873 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1874 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1875 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1876 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1877 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1878 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1879 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1880 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1881 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1882 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1883 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1884 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1885 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1886 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1887 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1888 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1889 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1890 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1891 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1892 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1893 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1894 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1895 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1896 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1897 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1898 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1899 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1900 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1901 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1902 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1903 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1904 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1905 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1906 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1907 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1908 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1909
1910 /* Use byte values for the following shift parameters
1911 * Usage:
1912 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1913 * E1000_PSRCTL_BSIZE0_MASK) |
1914 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1915 * E1000_PSRCTL_BSIZE1_MASK) |
1916 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1917 * E1000_PSRCTL_BSIZE2_MASK) |
1918 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1919 * E1000_PSRCTL_BSIZE3_MASK))
1920 * where value0 = [128..16256], default=256
1921 * value1 = [1024..64512], default=4096
1922 * value2 = [0..64512], default=4096
1923 * value3 = [0..64512], default=0
1924 */
1925
1926 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1927 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1928 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1929 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1930
1931 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1932 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1933 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1934 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1935
1936 /* SW_W_SYNC definitions */
1937 #define E1000_SWFW_EEP_SM 0x0001
1938 #define E1000_SWFW_PHY0_SM 0x0002
1939 #define E1000_SWFW_PHY1_SM 0x0004
1940 #define E1000_SWFW_MAC_CSR_SM 0x0008
1941
1942 /* Receive Descriptor */
1943 #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1944 #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1945 #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1946 #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1947 #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1948
1949 /* Flow Control */
1950 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1951 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1952 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1953 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1954
1955 /* Header split receive */
1956 #define E1000_RFCTL_ISCSI_DIS 0x00000001
1957 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
1958 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1
1959 #define E1000_RFCTL_NFSW_DIS 0x00000040
1960 #define E1000_RFCTL_NFSR_DIS 0x00000080
1961 #define E1000_RFCTL_NFS_VER_MASK 0x00000300
1962 #define E1000_RFCTL_NFS_VER_SHIFT 8
1963 #define E1000_RFCTL_IPV6_DIS 0x00000400
1964 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
1965 #define E1000_RFCTL_ACK_DIS 0x00001000
1966 #define E1000_RFCTL_ACKD_DIS 0x00002000
1967 #define E1000_RFCTL_IPFRSP_DIS 0x00004000
1968 #define E1000_RFCTL_EXTEN 0x00008000
1969 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1970 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1971
1972 /* Receive Descriptor Control */
1973 #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1974 #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1975 #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1976 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1977
1978 /* Transmit Descriptor Control */
1979 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
1980 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
1981 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
1982 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1983 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1984 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1985 #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1986 still to be processed. */
1987 /* Transmit Configuration Word */
1988 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1989 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1990 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1991 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1992 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1993 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1994 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1995 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1996 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1997 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1998
1999 /* Receive Configuration Word */
2000 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
2001 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
2002 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
2003 #define E1000_RXCW_CC 0x10000000 /* Receive config change */
2004 #define E1000_RXCW_C 0x20000000 /* Receive config */
2005 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
2006 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
2007
2008 /* Transmit Control */
2009 #define E1000_TCTL_RST 0x00000001 /* software reset */
2010 #define E1000_TCTL_EN 0x00000002 /* enable tx */
2011 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */
2012 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
2013 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
2014 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
2015 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
2016 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
2017 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
2018 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
2019 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
2020 /* Extended Transmit Control */
2021 #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
2022 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
2023
2024 #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
2025
2026 /* Receive Checksum Control */
2027 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
2028 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
2029 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
2030 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
2031 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
2032 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
2033
2034 /* Multiple Receive Queue Control */
2035 #define E1000_MRQC_ENABLE_MASK 0x00000003
2036 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
2037 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004
2038 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
2039 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
2040 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
2041 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
2042 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
2043 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
2044 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
2045
2046 /* Definitions for power management and wakeup registers */
2047 /* Wake Up Control */
2048 #define E1000_WUC_APME 0x00000001 /* APM Enable */
2049 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
2050 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
2051 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
2052 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */
2053
2054 /* Wake Up Filter Control */
2055 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
2056 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
2057 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
2058 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
2059 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
2060 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
2061 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
2062 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
2063 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
2064 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
2065 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
2066 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
2067 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
2068 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
2069 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
2070 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
2071
2072 /* Wake Up Status */
2073 #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
2074 #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
2075 #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
2076 #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
2077 #define E1000_WUS_BC 0x00000010 /* Broadcast Received */
2078 #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
2079 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
2080 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
2081 #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
2082 #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
2083 #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
2084 #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
2085 #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
2086
2087 /* Management Control */
2088 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
2089 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
2090 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
2091 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
2092 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
2093 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
2094 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
2095 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
2096 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
2097 #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
2098 * Filtering */
2099 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
2100 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
2101 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
2102 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
2103 #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
2104 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
2105 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
2106 * filtering */
2107 #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
2108 * memory */
2109 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
2110 * filtering */
2111 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
2112 #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
2113 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
2114 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
2115 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
2116 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
2117 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
2118 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
2119
2120 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
2121 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
2122
2123 /* SW Semaphore Register */
2124 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2125 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2126 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2127 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
2128
2129 /* FW Semaphore Register */
2130 #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
2131 #define E1000_FWSM_MODE_SHIFT 1
2132 #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2133
2134 #define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2135 #define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2136 #define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2137 #define E1000_FWSM_SKUEL_SHIFT 29
2138 #define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2139 #define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2140 #define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2141 #define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2142
2143 /* FFLT Debug Register */
2144 #define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2145
2146 typedef enum {
2147 e1000_mng_mode_none = 0,
2148 e1000_mng_mode_asf,
2149 e1000_mng_mode_pt,
2150 e1000_mng_mode_ipmi,
2151 e1000_mng_mode_host_interface_only
2152 } e1000_mng_mode;
2153
2154 /* Host Inteface Control Register */
2155 #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
2156 #define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
2157 * to put command in RAM */
2158 #define E1000_HICR_SV 0x00000004 /* Status Validity */
2159 #define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
2160
2161 /* Host Interface Command Interface - Address range 0x8800-0x8EFF */
2162 #define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
2163 #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
2164 #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
2165 #define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
2166
2167 struct e1000_host_command_header {
2168 u8 command_id;
2169 u8 command_length;
2170 u8 command_options; /* I/F bits for command, status for return */
2171 u8 checksum;
2172 };
2173 struct e1000_host_command_info {
2174 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
2175 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
2176 };
2177
2178 /* Host SMB register #0 */
2179 #define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
2180 #define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
2181 #define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
2182 #define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
2183
2184 /* Host SMB register #1 */
2185 #define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
2186 #define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
2187 #define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
2188 #define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
2189
2190 /* FW Status Register */
2191 #define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
2192
2193 /* Wake Up Packet Length */
2194 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
2195
2196 #define E1000_MDALIGN 4096
2197
2198 /* PCI-Ex registers*/
2199
2200 /* PCI-Ex Control Register */
2201 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
2202 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
2203 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
2204 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
2205 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
2206 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
2207
2208 #define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
2209 E1000_GCR_RXDSCW_NO_SNOOP | \
2210 E1000_GCR_RXDSCR_NO_SNOOP | \
2211 E1000_GCR_TXD_NO_SNOOP | \
2212 E1000_GCR_TXDSCW_NO_SNOOP | \
2213 E1000_GCR_TXDSCR_NO_SNOOP)
2214
2215 #define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2216
2217 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2218 /* Function Active and Power State to MNG */
2219 #define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
2220 #define E1000_FACTPS_LAN0_VALID 0x00000004
2221 #define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
2222 #define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
2223 #define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
2224 #define E1000_FACTPS_LAN1_VALID 0x00000100
2225 #define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
2226 #define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
2227 #define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
2228 #define E1000_FACTPS_IDE_ENABLE 0x00004000
2229 #define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
2230 #define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
2231 #define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
2232 #define E1000_FACTPS_SP_ENABLE 0x00100000
2233 #define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
2234 #define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
2235 #define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
2236 #define E1000_FACTPS_IPMI_ENABLE 0x04000000
2237 #define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
2238 #define E1000_FACTPS_MNGCG 0x20000000
2239 #define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
2240 #define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
2241
2242 /* PCI-Ex Config Space */
2243 #define PCI_EX_LINK_STATUS 0x12
2244 #define PCI_EX_LINK_WIDTH_MASK 0x3F0
2245 #define PCI_EX_LINK_WIDTH_SHIFT 4
2246
2247 /* EEPROM Commands - Microwire */
2248 #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
2249 #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
2250 #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
2251 #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
2252 #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
2253
2254 /* EEPROM Commands - SPI */
2255 #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2256 #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2257 #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2258 #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
2259 #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
2260 #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
2261 #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
2262 #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
2263 #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2264 #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2265 #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
2266
2267 /* EEPROM Size definitions */
2268 #define EEPROM_WORD_SIZE_SHIFT 6
2269 #define EEPROM_SIZE_SHIFT 10
2270 #define EEPROM_SIZE_MASK 0x1C00
2271
2272 /* EEPROM Word Offsets */
2273 #define EEPROM_COMPAT 0x0003
2274 #define EEPROM_ID_LED_SETTINGS 0x0004
2275 #define EEPROM_VERSION 0x0005
2276 #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
2277 #define EEPROM_PHY_CLASS_WORD 0x0007
2278 #define EEPROM_INIT_CONTROL1_REG 0x000A
2279 #define EEPROM_INIT_CONTROL2_REG 0x000F
2280 #define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
2281 #define EEPROM_INIT_CONTROL3_PORT_B 0x0014
2282 #define EEPROM_INIT_3GIO_3 0x001A
2283 #define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
2284 #define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2285 #define EEPROM_CFG 0x0012
2286 #define EEPROM_FLASH_VERSION 0x0032
2287 #define EEPROM_CHECKSUM_REG 0x003F
2288
2289 #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
2290 #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
2291
2292 /* Word definitions for ID LED Settings */
2293 #define ID_LED_RESERVED_0000 0x0000
2294 #define ID_LED_RESERVED_FFFF 0xFFFF
2295 #define ID_LED_RESERVED_82573 0xF746
2296 #define ID_LED_DEFAULT_82573 0x1811
2297 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2298 (ID_LED_OFF1_OFF2 << 8) | \
2299 (ID_LED_DEF1_DEF2 << 4) | \
2300 (ID_LED_DEF1_DEF2))
2301 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
2302 (ID_LED_DEF1_OFF2 << 8) | \
2303 (ID_LED_DEF1_ON2 << 4) | \
2304 (ID_LED_DEF1_DEF2))
2305 #define ID_LED_DEF1_DEF2 0x1
2306 #define ID_LED_DEF1_ON2 0x2
2307 #define ID_LED_DEF1_OFF2 0x3
2308 #define ID_LED_ON1_DEF2 0x4
2309 #define ID_LED_ON1_ON2 0x5
2310 #define ID_LED_ON1_OFF2 0x6
2311 #define ID_LED_OFF1_DEF2 0x7
2312 #define ID_LED_OFF1_ON2 0x8
2313 #define ID_LED_OFF1_OFF2 0x9
2314
2315 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2316 #define IGP_ACTIVITY_LED_ENABLE 0x0300
2317 #define IGP_LED3_MODE 0x07000000
2318
2319
2320 /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2321 #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2322
2323 /* Mask bit for PHY class in Word 7 of the EEPROM */
2324 #define EEPROM_PHY_CLASS_A 0x8000
2325
2326 /* Mask bits for fields in Word 0x0a of the EEPROM */
2327 #define EEPROM_WORD0A_ILOS 0x0010
2328 #define EEPROM_WORD0A_SWDPIO 0x01E0
2329 #define EEPROM_WORD0A_LRST 0x0200
2330 #define EEPROM_WORD0A_FD 0x0400
2331 #define EEPROM_WORD0A_66MHZ 0x0800
2332
2333 /* Mask bits for fields in Word 0x0f of the EEPROM */
2334 #define EEPROM_WORD0F_PAUSE_MASK 0x3000
2335 #define EEPROM_WORD0F_PAUSE 0x1000
2336 #define EEPROM_WORD0F_ASM_DIR 0x2000
2337 #define EEPROM_WORD0F_ANE 0x0800
2338 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2339 #define EEPROM_WORD0F_LPLU 0x0001
2340
2341 /* Mask bits for fields in Word 0x10/0x20 of the EEPROM */
2342 #define EEPROM_WORD1020_GIGA_DISABLE 0x0010
2343 #define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008
2344
2345 /* Mask bits for fields in Word 0x1a of the EEPROM */
2346 #define EEPROM_WORD1A_ASPM_MASK 0x000C
2347
2348 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
2349 #define EEPROM_SUM 0xBABA
2350
2351 /* EEPROM Map defines (WORD OFFSETS)*/
2352 #define EEPROM_NODE_ADDRESS_BYTE_0 0
2353 #define EEPROM_PBA_BYTE_1 8
2354
2355 #define EEPROM_RESERVED_WORD 0xFFFF
2356
2357 /* EEPROM Map Sizes (Byte Counts) */
2358 #define PBA_SIZE 4
2359
2360 /* Collision related configuration parameters */
2361 #define E1000_COLLISION_THRESHOLD 15
2362 #define E1000_CT_SHIFT 4
2363 /* Collision distance is a 0-based value that applies to
2364 * half-duplex-capable hardware only. */
2365 #define E1000_COLLISION_DISTANCE 63
2366 #define E1000_COLLISION_DISTANCE_82542 64
2367 #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2368 #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2369 #define E1000_COLD_SHIFT 12
2370
2371 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2372 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
2373 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
2374
2375 /* Default values for the transmit IPG register */
2376 #define DEFAULT_82542_TIPG_IPGT 10
2377 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
2378 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
2379
2380 #define E1000_TIPG_IPGT_MASK 0x000003FF
2381 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
2382 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
2383
2384 #define DEFAULT_82542_TIPG_IPGR1 2
2385 #define DEFAULT_82543_TIPG_IPGR1 8
2386 #define E1000_TIPG_IPGR1_SHIFT 10
2387
2388 #define DEFAULT_82542_TIPG_IPGR2 10
2389 #define DEFAULT_82543_TIPG_IPGR2 6
2390 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
2391 #define E1000_TIPG_IPGR2_SHIFT 20
2392
2393 #define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
2394 #define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
2395 #define E1000_TXDMAC_DPP 0x00000001
2396
2397 /* Adaptive IFS defines */
2398 #define TX_THRESHOLD_START 8
2399 #define TX_THRESHOLD_INCREMENT 10
2400 #define TX_THRESHOLD_DECREMENT 1
2401 #define TX_THRESHOLD_STOP 190
2402 #define TX_THRESHOLD_DISABLE 0
2403 #define TX_THRESHOLD_TIMER_MS 10000
2404 #define MIN_NUM_XMITS 1000
2405 #define IFS_MAX 80
2406 #define IFS_STEP 10
2407 #define IFS_MIN 40
2408 #define IFS_RATIO 4
2409
2410 /* Extended Configuration Control and Size */
2411 #define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2412 #define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2413 #define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2414 #define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2415 #define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2416 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2417 #define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2418 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000
2419
2420 #define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2421 #define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2422 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2423 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
2424 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2425
2426 /* PBA constants */
2427 #define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2428 #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2429 #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2430 #define E1000_PBA_20K 0x0014
2431 #define E1000_PBA_22K 0x0016
2432 #define E1000_PBA_24K 0x0018
2433 #define E1000_PBA_30K 0x001E
2434 #define E1000_PBA_32K 0x0020
2435 #define E1000_PBA_34K 0x0022
2436 #define E1000_PBA_38K 0x0026
2437 #define E1000_PBA_40K 0x0028
2438 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2439
2440 #define E1000_PBS_16K E1000_PBA_16K
2441
2442 /* Flow Control Constants */
2443 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2444 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
2445 #define FLOW_CONTROL_TYPE 0x8808
2446
2447 /* The historical defaults for the flow control values are given below. */
2448 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2449 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2450 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
2451
2452 /* PCIX Config space */
2453 #define PCIX_COMMAND_REGISTER 0xE6
2454 #define PCIX_STATUS_REGISTER_LO 0xE8
2455 #define PCIX_STATUS_REGISTER_HI 0xEA
2456
2457 #define PCIX_COMMAND_MMRBC_MASK 0x000C
2458 #define PCIX_COMMAND_MMRBC_SHIFT 0x2
2459 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060
2460 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
2461 #define PCIX_STATUS_HI_MMRBC_4K 0x3
2462 #define PCIX_STATUS_HI_MMRBC_2K 0x2
2463
2464
2465 /* Number of bits required to shift right the "pause" bits from the
2466 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2467 */
2468 #define PAUSE_SHIFT 5
2469
2470 /* Number of bits required to shift left the "SWDPIO" bits from the
2471 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
2472 */
2473 #define SWDPIO_SHIFT 17
2474
2475 /* Number of bits required to shift left the "SWDPIO_EXT" bits from the
2476 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
2477 */
2478 #define SWDPIO__EXT_SHIFT 4
2479
2480 /* Number of bits required to shift left the "ILOS" bit from the EEPROM
2481 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
2482 */
2483 #define ILOS_SHIFT 3
2484
2485
2486 #define RECEIVE_BUFFER_ALIGN_SIZE (256)
2487
2488 /* Number of milliseconds we wait for auto-negotiation to complete */
2489 #define LINK_UP_TIMEOUT 500
2490
2491 /* Number of 100 microseconds we wait for PCI Express master disable */
2492 #define MASTER_DISABLE_TIMEOUT 800
2493 /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2494 #define AUTO_READ_DONE_TIMEOUT 10
2495 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
2496 #define PHY_CFG_TIMEOUT 100
2497
2498 #define E1000_TX_BUFFER_SIZE ((u32)1514)
2499
2500 /* The carrier extension symbol, as received by the NIC. */
2501 #define CARRIER_EXTENSION 0x0F
2502
2503 /* TBI_ACCEPT macro definition:
2504 *
2505 * This macro requires:
2506 * adapter = a pointer to struct e1000_hw
2507 * status = the 8 bit status field of the RX descriptor with EOP set
2508 * error = the 8 bit error field of the RX descriptor with EOP set
2509 * length = the sum of all the length fields of the RX descriptors that
2510 * make up the current frame
2511 * last_byte = the last byte of the frame DMAed by the hardware
2512 * max_frame_length = the maximum frame length we want to accept.
2513 * min_frame_length = the minimum frame length we want to accept.
2514 *
2515 * This macro is a conditional that should be used in the interrupt
2516 * handler's Rx processing routine when RxErrors have been detected.
2517 *
2518 * Typical use:
2519 * ...
2520 * if (TBI_ACCEPT) {
2521 * accept_frame = true;
2522 * e1000_tbi_adjust_stats(adapter, MacAddress);
2523 * frame_length--;
2524 * } else {
2525 * accept_frame = false;
2526 * }
2527 * ...
2528 */
2529
2530 #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
2531 ((adapter)->tbi_compatibility_on && \
2532 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
2533 ((last_byte) == CARRIER_EXTENSION) && \
2534 (((status) & E1000_RXD_STAT_VP) ? \
2535 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2536 ((length) <= ((adapter)->max_frame_size + 1))) : \
2537 (((length) > (adapter)->min_frame_size) && \
2538 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2539
2540
2541 /* Structures, enums, and macros for the PHY */
2542
2543 /* Bit definitions for the Management Data IO (MDIO) and Management Data
2544 * Clock (MDC) pins in the Device Control Register.
2545 */
2546 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
2547 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
2548 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
2549 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
2550 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
2551 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
2552 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
2553 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
2554
2555 /* PHY 1000 MII Register/Bit Definitions */
2556 /* PHY Registers defined by IEEE */
2557 #define PHY_CTRL 0x00 /* Control Register */
2558 #define PHY_STATUS 0x01 /* Status Regiser */
2559 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2560 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2561 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2562 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2563 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2564 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2565 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2566 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2567 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2568 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2569
2570 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2571 #define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
2572
2573 /* M88E1000 Specific Registers */
2574 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2575 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2576 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2577 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2578 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2579 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2580
2581 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2582 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2583 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2584 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2585 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
2586
2587 #define IGP01E1000_IEEE_REGS_PAGE 0x0000
2588 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2589 #define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2590
2591 /* IGP01E1000 Specific Registers */
2592 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2593 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2594 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2595 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2596 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2597 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2598 #define IGP02E1000_PHY_POWER_MGMT 0x19
2599 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
2600
2601 /* IGP01E1000 AGC Registers - stores the cable length values*/
2602 #define IGP01E1000_PHY_AGC_A 0x1172
2603 #define IGP01E1000_PHY_AGC_B 0x1272
2604 #define IGP01E1000_PHY_AGC_C 0x1472
2605 #define IGP01E1000_PHY_AGC_D 0x1872
2606
2607 /* IGP02E1000 AGC Registers for cable length values */
2608 #define IGP02E1000_PHY_AGC_A 0x11B1
2609 #define IGP02E1000_PHY_AGC_B 0x12B1
2610 #define IGP02E1000_PHY_AGC_C 0x14B1
2611 #define IGP02E1000_PHY_AGC_D 0x18B1
2612
2613 /* IGP01E1000 DSP Reset Register */
2614 #define IGP01E1000_PHY_DSP_RESET 0x1F33
2615 #define IGP01E1000_PHY_DSP_SET 0x1F71
2616 #define IGP01E1000_PHY_DSP_FFE 0x1F35
2617
2618 #define IGP01E1000_PHY_CHANNEL_NUM 4
2619 #define IGP02E1000_PHY_CHANNEL_NUM 4
2620
2621 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171
2622 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271
2623 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471
2624 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871
2625
2626 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
2627 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
2628
2629 #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
2630 #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
2631 #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
2632 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
2633
2634 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
2635 /* IGP01E1000 PCS Initialization register - stores the polarity status when
2636 * speed = 1000 Mbps. */
2637 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
2638 #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
2639
2640 #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2641
2642 /* Bits...
2643 * 15-5: page
2644 * 4-0: register offset
2645 */
2646 #define GG82563_PAGE_SHIFT 5
2647 #define GG82563_REG(page, reg) \
2648 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2649 #define GG82563_MIN_ALT_REG 30
2650
2651 /* GG82563 Specific Registers */
2652 #define GG82563_PHY_SPEC_CTRL \
2653 GG82563_REG(0, 16) /* PHY Specific Control */
2654 #define GG82563_PHY_SPEC_STATUS \
2655 GG82563_REG(0, 17) /* PHY Specific Status */
2656 #define GG82563_PHY_INT_ENABLE \
2657 GG82563_REG(0, 18) /* Interrupt Enable */
2658 #define GG82563_PHY_SPEC_STATUS_2 \
2659 GG82563_REG(0, 19) /* PHY Specific Status 2 */
2660 #define GG82563_PHY_RX_ERR_CNTR \
2661 GG82563_REG(0, 21) /* Receive Error Counter */
2662 #define GG82563_PHY_PAGE_SELECT \
2663 GG82563_REG(0, 22) /* Page Select */
2664 #define GG82563_PHY_SPEC_CTRL_2 \
2665 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2666 #define GG82563_PHY_PAGE_SELECT_ALT \
2667 GG82563_REG(0, 29) /* Alternate Page Select */
2668 #define GG82563_PHY_TEST_CLK_CTRL \
2669 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
2670
2671 #define GG82563_PHY_MAC_SPEC_CTRL \
2672 GG82563_REG(2, 21) /* MAC Specific Control Register */
2673 #define GG82563_PHY_MAC_SPEC_CTRL_2 \
2674 GG82563_REG(2, 26) /* MAC Specific Control 2 */
2675
2676 #define GG82563_PHY_DSP_DISTANCE \
2677 GG82563_REG(5, 26) /* DSP Distance */
2678
2679 /* Page 193 - Port Control Registers */
2680 #define GG82563_PHY_KMRN_MODE_CTRL \
2681 GG82563_REG(193, 16) /* Kumeran Mode Control */
2682 #define GG82563_PHY_PORT_RESET \
2683 GG82563_REG(193, 17) /* Port Reset */
2684 #define GG82563_PHY_REVISION_ID \
2685 GG82563_REG(193, 18) /* Revision ID */
2686 #define GG82563_PHY_DEVICE_ID \
2687 GG82563_REG(193, 19) /* Device ID */
2688 #define GG82563_PHY_PWR_MGMT_CTRL \
2689 GG82563_REG(193, 20) /* Power Management Control */
2690 #define GG82563_PHY_RATE_ADAPT_CTRL \
2691 GG82563_REG(193, 25) /* Rate Adaptation Control */
2692
2693 /* Page 194 - KMRN Registers */
2694 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
2695 GG82563_REG(194, 16) /* FIFO's Control/Status */
2696 #define GG82563_PHY_KMRN_CTRL \
2697 GG82563_REG(194, 17) /* Control */
2698 #define GG82563_PHY_INBAND_CTRL \
2699 GG82563_REG(194, 18) /* Inband Control */
2700 #define GG82563_PHY_KMRN_DIAGNOSTIC \
2701 GG82563_REG(194, 19) /* Diagnostic */
2702 #define GG82563_PHY_ACK_TIMEOUTS \
2703 GG82563_REG(194, 20) /* Acknowledge Timeouts */
2704 #define GG82563_PHY_ADV_ABILITY \
2705 GG82563_REG(194, 21) /* Advertised Ability */
2706 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
2707 GG82563_REG(194, 23) /* Link Partner Advertised Ability */
2708 #define GG82563_PHY_ADV_NEXT_PAGE \
2709 GG82563_REG(194, 24) /* Advertised Next Page */
2710 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
2711 GG82563_REG(194, 25) /* Link Partner Advertised Next page */
2712 #define GG82563_PHY_KMRN_MISC \
2713 GG82563_REG(194, 26) /* Misc. */
2714
2715 /* PHY Control Register */
2716 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2717 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2718 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2719 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2720 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2721 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
2722 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2723 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2724 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2725 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2726
2727 /* PHY Status Register */
2728 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2729 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2730 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2731 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2732 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2733 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2734 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2735 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2736 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2737 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2738 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2739 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2740 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2741 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2742 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2743
2744 /* Autoneg Advertisement Register */
2745 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2746 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2747 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2748 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2749 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2750 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2751 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2752 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2753 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2754 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2755
2756 /* Link Partner Ability Register (Base Page) */
2757 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2758 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2759 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2760 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2761 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2762 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2763 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2764 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2765 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2766 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2767 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2768
2769 /* Autoneg Expansion Register */
2770 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2771 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2772 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2773 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2774 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
2775
2776 /* Next Page TX Register */
2777 #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2778 #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2779 * of different NP
2780 */
2781 #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2782 * 0 = cannot comply with msg
2783 */
2784 #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2785 #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2786 * 0 = sending last NP
2787 */
2788
2789 /* Link Partner Next Page Register */
2790 #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2791 #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2792 * of different NP
2793 */
2794 #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2795 * 0 = cannot comply with msg
2796 */
2797 #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2798 #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2799 #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2800 * 0 = sending last NP
2801 */
2802
2803 /* 1000BASE-T Control Register */
2804 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2805 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2806 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2807 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2808 /* 0=DTE device */
2809 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2810 /* 0=Configure PHY as Slave */
2811 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2812 /* 0=Automatic Master/Slave config */
2813 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2814 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2815 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2816 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2817 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2818
2819 /* 1000BASE-T Status Register */
2820 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2821 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2822 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2823 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2824 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2825 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2826 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2827 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2828 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2829 #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2830 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
2831 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
2832 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2833
2834 /* Extended Status Register */
2835 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2836 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2837 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2838 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2839
2840 #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2841 #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2842
2843 #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2844 /* (0=enable, 1=disable) */
2845
2846 /* M88E1000 PHY Specific Control Register */
2847 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2848 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2849 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2850 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2851 * 0=CLK125 toggling
2852 */
2853 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2854 /* Manual MDI configuration */
2855 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2856 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2857 * 100BASE-TX/10BASE-T:
2858 * MDI Mode
2859 */
2860 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2861 * all speeds.
2862 */
2863 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2864 /* 1=Enable Extended 10BASE-T distance
2865 * (Lower 10BASE-T RX Threshold)
2866 * 0=Normal 10BASE-T RX Threshold */
2867 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2868 /* 1=5-Bit interface in 100BASE-TX
2869 * 0=MII interface in 100BASE-TX */
2870 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2871 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2872 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2873
2874 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2875 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2876 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2877
2878 /* M88E1000 PHY Specific Status Register */
2879 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2880 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2881 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2882 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2883 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2884 * 3=110-140M;4=>140M */
2885 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2886 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2887 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2888 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2889 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2890 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2891 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2892 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2893
2894 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2895 #define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
2896 #define M88E1000_PSSR_MDIX_SHIFT 6
2897 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2898
2899 /* M88E1000 Extended PHY Specific Control Register */
2900 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2901 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2902 * Will assert lost lock and bring
2903 * link down if idle not seen
2904 * within 1ms in 1000BASE-T
2905 */
2906 /* Number of times we will attempt to autonegotiate before downshifting if we
2907 * are the master */
2908 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2909 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2910 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2911 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2912 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2913 /* Number of times we will attempt to autonegotiate before downshifting if we
2914 * are the slave */
2915 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2916 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2917 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2918 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2919 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2920 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2921 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2922 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2923
2924 /* M88EC018 Rev 2 specific DownShift settings */
2925 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
2926 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
2927 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
2928 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
2929 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
2930 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
2931 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
2932 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
2933 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
2934
2935 /* IGP01E1000 Specific Port Config Register - R/W */
2936 #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2937 #define IGP01E1000_PSCFR_PRE_EN 0x0020
2938 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2939 #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2940 #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2941 #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2942
2943 /* IGP01E1000 Specific Port Status Register - R/O */
2944 #define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2945 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2946 #define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2947 #define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2948 #define IGP01E1000_PSSR_LINK_UP 0x0400
2949 #define IGP01E1000_PSSR_MDIX 0x0800
2950 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2951 #define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2952 #define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2953 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2954 #define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2955 #define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2956
2957 /* IGP01E1000 Specific Port Control Register - R/W */
2958 #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2959 #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2960 #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2961 #define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2962 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2963 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2964
2965 /* IGP01E1000 Specific Port Link Health Register */
2966 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2967 #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2968 #define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2969 #define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2970 #define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2971 #define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2972 #define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2973 #define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2974 #define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2975 #define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
2976 #define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
2977 #define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
2978 #define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
2979 #define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
2980
2981 /* IGP01E1000 Channel Quality Register */
2982 #define IGP01E1000_MSE_CHANNEL_D 0x000F
2983 #define IGP01E1000_MSE_CHANNEL_C 0x00F0
2984 #define IGP01E1000_MSE_CHANNEL_B 0x0F00
2985 #define IGP01E1000_MSE_CHANNEL_A 0xF000
2986
2987 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2988 #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2989 #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2990
2991 /* IGP01E1000 DSP reset macros */
2992 #define DSP_RESET_ENABLE 0x0
2993 #define DSP_RESET_DISABLE 0x2
2994 #define E1000_MAX_DSP_RESETS 10
2995
2996 /* IGP01E1000 & IGP02E1000 AGC Registers */
2997
2998 #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2999 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
3000
3001 /* IGP02E1000 AGC Register Length 9-bit mask */
3002 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
3003
3004 /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
3005 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
3006 #define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113
3007
3008 /* The precision error of the cable length is +/- 10 meters */
3009 #define IGP01E1000_AGC_RANGE 10
3010 #define IGP02E1000_AGC_RANGE 15
3011
3012 /* IGP01E1000 PCS Initialization register */
3013 /* bits 3:6 in the PCS registers stores the channels polarity */
3014 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
3015
3016 /* IGP01E1000 GMII FIFO Register */
3017 #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
3018 * on Link-Up */
3019 #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
3020
3021 /* IGP01E1000 Analog Register */
3022 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
3023 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
3024 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
3025 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
3026
3027 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
3028 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
3029 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
3030 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
3031 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
3032
3033 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
3034 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
3035 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
3036 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
3037
3038 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
3039 #define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
3040 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */
3041 #define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
3042 #define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */
3043 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
3044 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */
3045 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */
3046 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */
3047 #define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */
3048 #define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
3049 #define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
3050 #define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */
3051 #define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
3052 #define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
3053 #define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
3054 #define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
3055 #define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
3056
3057 /* PHY Specific Status Register (Page 0, Register 17) */
3058 #define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
3059 #define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
3060 #define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
3061 #define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
3062 #define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
3063 #define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
3064 #define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
3065 #define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
3066 #define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
3067 #define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
3068 #define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
3069 #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
3070 #define GG82563_PSSR_SPEED_MASK 0xC000
3071 #define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
3072 #define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
3073 #define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
3074
3075 /* PHY Specific Status Register 2 (Page 0, Register 19) */
3076 #define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
3077 #define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
3078 #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
3079 #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
3080 #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
3081 #define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */
3082 #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
3083 #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
3084 #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
3085 #define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
3086 #define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
3087 #define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
3088 #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
3089
3090 /* PHY Specific Control Register 2 (Page 0, Register 26) */
3091 #define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */
3092 #define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
3093 #define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */
3094 #define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */
3095 #define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */
3096 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */
3097 #define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */
3098 #define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
3099 #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
3100 #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
3101
3102 /* MAC Specific Control Register (Page 2, Register 21) */
3103 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
3104 #define GG82563_MSCR_TX_CLK_MASK 0x0007
3105 #define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
3106 #define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
3107 #define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
3108 #define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
3109
3110 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
3111
3112 /* DSP Distance Register (Page 5, Register 26) */
3113 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
3114 1 = 50-80M;
3115 2 = 80-110M;
3116 3 = 110-140M;
3117 4 = >140M */
3118
3119 /* Kumeran Mode Control Register (Page 193, Register 16) */
3120 #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */
3121 #define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
3122 #define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
3123 #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
3124 #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */
3125 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
3126
3127 /* Power Management Control Register (Page 193, Register 20) */
3128 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES Electrical Idle */
3129 #define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
3130 #define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
3131 #define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */
3132 #define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */
3133 #define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */
3134 #define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */
3135 #define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
3136 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
3137 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
3138 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
3139 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
3140 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
3141
3142 /* In-Band Control Register (Page 194, Register 18) */
3143 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
3144
3145
3146 /* Bit definitions for valid PHY IDs. */
3147 /* I = Integrated
3148 * E = External
3149 */
3150 #define M88_VENDOR 0x0141
3151 #define M88E1000_E_PHY_ID 0x01410C50
3152 #define M88E1000_I_PHY_ID 0x01410C30
3153 #define M88E1011_I_PHY_ID 0x01410C20
3154 #define IGP01E1000_I_PHY_ID 0x02A80380
3155 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
3156 #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
3157 #define M88E1011_I_REV_4 0x04
3158 #define M88E1111_I_PHY_ID 0x01410CC0
3159 #define L1LXT971A_PHY_ID 0x001378E0
3160 #define GG82563_E_PHY_ID 0x01410CA0
3161
3162
3163 /* Bits...
3164 * 15-5: page
3165 * 4-0: register offset
3166 */
3167 #define PHY_PAGE_SHIFT 5
3168 #define PHY_REG(page, reg) \
3169 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
3170
3171 #define IGP3_PHY_PORT_CTRL \
3172 PHY_REG(769, 17) /* Port General Configuration */
3173 #define IGP3_PHY_RATE_ADAPT_CTRL \
3174 PHY_REG(769, 25) /* Rate Adapter Control Register */
3175
3176 #define IGP3_KMRN_FIFO_CTRL_STATS \
3177 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
3178 #define IGP3_KMRN_POWER_MNG_CTRL \
3179 PHY_REG(770, 17) /* KMRN Power Management Control Register */
3180 #define IGP3_KMRN_INBAND_CTRL \
3181 PHY_REG(770, 18) /* KMRN Inband Control Register */
3182 #define IGP3_KMRN_DIAG \
3183 PHY_REG(770, 19) /* KMRN Diagnostic register */
3184 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
3185 #define IGP3_KMRN_ACK_TIMEOUT \
3186 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
3187
3188 #define IGP3_VR_CTRL \
3189 PHY_REG(776, 18) /* Voltage regulator control register */
3190 #define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
3191 #define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */
3192
3193 #define IGP3_CAPABILITY \
3194 PHY_REG(776, 19) /* IGP3 Capability Register */
3195
3196 /* Capabilities for SKU Control */
3197 #define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
3198 #define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
3199 #define IGP3_CAP_ASF 0x0004 /* Support ASF */
3200 #define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
3201 #define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
3202 #define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
3203 #define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
3204 #define IGP3_CAP_RSS 0x0080 /* Support RSS */
3205 #define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
3206 #define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
3207
3208 #define IGP3_PPC_JORDAN_EN 0x0001
3209 #define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
3210
3211 #define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001
3212 #define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E
3213 #define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
3214 #define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
3215
3216 #define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
3217 #define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
3218
3219 #define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
3220 #define IGP3_KMRN_EC_DIS_INBAND 0x0080
3221
3222 #define IGP03E1000_E_PHY_ID 0x02A80390
3223 #define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
3224 #define IFE_PLUS_E_PHY_ID 0x02A80320
3225 #define IFE_C_E_PHY_ID 0x02A80310
3226
3227 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
3228 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
3229 #define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
3230 #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */
3231 #define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
3232 #define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
3233 #define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
3234 #define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
3235 #define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
3236 #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
3237 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
3238 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
3239 #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
3240
3241 #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */
3242 #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
3243 #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
3244 #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
3245 #define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
3246 #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
3247 #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
3248 #define IFE_PESC_POLARITY_REVERSED_SHIFT 8
3249
3250 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */
3251 #define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
3252 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
3253 #define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
3254 #define IFE_PSC_FORCE_POLARITY_SHIFT 5
3255 #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
3256
3257 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
3258 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
3259 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
3260 #define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */
3261 #define IFE_PMC_MDIX_MODE_SHIFT 6
3262 #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
3263
3264 #define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
3265 #define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
3266 #define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
3267 #define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
3268 #define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
3269 #define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
3270 #define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
3271 #define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
3272 #define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
3273 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
3274 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
3275
3276 #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
3277 #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
3278 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */
3279 #define ICH_FLASH_SEG_SIZE_256 256
3280 #define ICH_FLASH_SEG_SIZE_4K 4096
3281 #define ICH_FLASH_SEG_SIZE_64K 65536
3282
3283 #define ICH_CYCLE_READ 0x0
3284 #define ICH_CYCLE_RESERVED 0x1
3285 #define ICH_CYCLE_WRITE 0x2
3286 #define ICH_CYCLE_ERASE 0x3
3287
3288 #define ICH_FLASH_GFPREG 0x0000
3289 #define ICH_FLASH_HSFSTS 0x0004
3290 #define ICH_FLASH_HSFCTL 0x0006
3291 #define ICH_FLASH_FADDR 0x0008
3292 #define ICH_FLASH_FDATA0 0x0010
3293 #define ICH_FLASH_FRACC 0x0050
3294 #define ICH_FLASH_FREG0 0x0054
3295 #define ICH_FLASH_FREG1 0x0058
3296 #define ICH_FLASH_FREG2 0x005C
3297 #define ICH_FLASH_FREG3 0x0060
3298 #define ICH_FLASH_FPR0 0x0074
3299 #define ICH_FLASH_FPR1 0x0078
3300 #define ICH_FLASH_SSFSTS 0x0090
3301 #define ICH_FLASH_SSFCTL 0x0092
3302 #define ICH_FLASH_PREOP 0x0094
3303 #define ICH_FLASH_OPTYPE 0x0096
3304 #define ICH_FLASH_OPMENU 0x0098
3305
3306 #define ICH_FLASH_REG_MAPSIZE 0x00A0
3307 #define ICH_FLASH_SECTOR_SIZE 4096
3308 #define ICH_GFPREG_BASE_MASK 0x1FFF
3309 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
3310
3311 /* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
3312 /* Offset 04h HSFSTS */
3313 union ich8_hws_flash_status {
3314 struct ich8_hsfsts {
3315 #ifdef __BIG_ENDIAN
3316 u16 reserved2 :6;
3317 u16 fldesvalid :1;
3318 u16 flockdn :1;
3319 u16 flcdone :1;
3320 u16 flcerr :1;
3321 u16 dael :1;
3322 u16 berasesz :2;
3323 u16 flcinprog :1;
3324 u16 reserved1 :2;
3325 #else
3326 u16 flcdone :1; /* bit 0 Flash Cycle Done */
3327 u16 flcerr :1; /* bit 1 Flash Cycle Error */
3328 u16 dael :1; /* bit 2 Direct Access error Log */
3329 u16 berasesz :2; /* bit 4:3 Block/Sector Erase Size */
3330 u16 flcinprog :1; /* bit 5 flash SPI cycle in Progress */
3331 u16 reserved1 :2; /* bit 13:6 Reserved */
3332 u16 reserved2 :6; /* bit 13:6 Reserved */
3333 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
3334 u16 flockdn :1; /* bit 15 Flash Configuration Lock-Down */
3335 #endif
3336 } hsf_status;
3337 u16 regval;
3338 };
3339
3340 /* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */
3341 /* Offset 06h FLCTL */
3342 union ich8_hws_flash_ctrl {
3343 struct ich8_hsflctl {
3344 #ifdef __BIG_ENDIAN
3345 u16 fldbcount :2;
3346 u16 flockdn :6;
3347 u16 flcgo :1;
3348 u16 flcycle :2;
3349 u16 reserved :5;
3350 #else
3351 u16 flcgo :1; /* 0 Flash Cycle Go */
3352 u16 flcycle :2; /* 2:1 Flash Cycle */
3353 u16 reserved :5; /* 7:3 Reserved */
3354 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
3355 u16 flockdn :6; /* 15:10 Reserved */
3356 #endif
3357 } hsf_ctrl;
3358 u16 regval;
3359 };
3360
3361 /* ICH8 Flash Region Access Permissions */
3362 union ich8_hws_flash_regacc {
3363 struct ich8_flracc {
3364 #ifdef __BIG_ENDIAN
3365 u32 gmwag :8;
3366 u32 gmrag :8;
3367 u32 grwa :8;
3368 u32 grra :8;
3369 #else
3370 u32 grra :8; /* 0:7 GbE region Read Access */
3371 u32 grwa :8; /* 8:15 GbE region Write Access */
3372 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
3373 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
3374 #endif
3375 } hsf_flregacc;
3376 u16 regval;
3377 };
3378
3379 /* Miscellaneous PHY bit definitions. */
3380 #define PHY_PREAMBLE 0xFFFFFFFF
3381 #define PHY_SOF 0x01
3382 #define PHY_OP_READ 0x02
3383 #define PHY_OP_WRITE 0x01
3384 #define PHY_TURNAROUND 0x02
3385 #define PHY_PREAMBLE_SIZE 32
3386 #define MII_CR_SPEED_1000 0x0040
3387 #define MII_CR_SPEED_100 0x2000
3388 #define MII_CR_SPEED_10 0x0000
3389 #define E1000_PHY_ADDRESS 0x01
3390 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
3391 #define PHY_FORCE_TIME 20 /* 2.0 Seconds */
3392 #define PHY_REVISION_MASK 0xFFFFFFF0
3393 #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
3394 #define REG4_SPEED_MASK 0x01E0
3395 #define REG9_SPEED_MASK 0x0300
3396 #define ADVERTISE_10_HALF 0x0001
3397 #define ADVERTISE_10_FULL 0x0002
3398 #define ADVERTISE_100_HALF 0x0004
3399 #define ADVERTISE_100_FULL 0x0008
3400 #define ADVERTISE_1000_HALF 0x0010
3401 #define ADVERTISE_1000_FULL 0x0020
3402 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
3403 #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
3404 #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
3405
3406 #endif /* _E1000_HW_H_ */
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