kernel/2.6.29.6-aldebaran-rt/drivers/media/video/ov772x.c

   1 /*
   2  * ov772x Camera Driver
   3  *
   4  * Copyright (C) 2008 Renesas Solutions Corp.
   5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  *
   7  * Based on ov7670 and soc_camera_platform driver,
   8  *
   9  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  10  * Copyright (C) 2008 Magnus Damm
  11  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/i2c.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/videodev2.h>
  24 #include <media/v4l2-chip-ident.h>
  25 #include <media/v4l2-common.h>
  26 #include <media/soc_camera.h>
  27 #include <media/ov772x.h>
  28
  29 /*
  30  * register offset
  31  */
  32 #define GAIN        0x00 /* AGC - Gain control gain setting */
  33 #define BLUE        0x01 /* AWB - Blue channel gain setting */
  34 #define RED         0x02 /* AWB - Red   channel gain setting */
  35 #define GREEN       0x03 /* AWB - Green channel gain setting */
  36 #define COM1        0x04 /* Common control 1 */
  37 #define BAVG        0x05 /* U/B Average Level */
  38 #define GAVG        0x06 /* Y/Gb Average Level */
  39 #define RAVG        0x07 /* V/R Average Level */
  40 #define AECH        0x08 /* Exposure Value - AEC MSBs */
  41 #define COM2        0x09 /* Common control 2 */
  42 #define PID         0x0A /* Product ID Number MSB */
  43 #define VER         0x0B /* Product ID Number LSB */
  44 #define COM3        0x0C /* Common control 3 */
  45 #define COM4        0x0D /* Common control 4 */
  46 #define COM5        0x0E /* Common control 5 */
  47 #define COM6        0x0F /* Common control 6 */
  48 #define AEC         0x10 /* Exposure Value */
  49 #define CLKRC       0x11 /* Internal clock */
  50 #define COM7        0x12 /* Common control 7 */
  51 #define COM8        0x13 /* Common control 8 */
  52 #define COM9        0x14 /* Common control 9 */
  53 #define COM10       0x15 /* Common control 10 */
  54 #define REG16       0x16 /* Register 16 */
  55 #define HSTART      0x17 /* Horizontal sensor size */
  56 #define HSIZE       0x18 /* Horizontal frame (HREF column) end high 8-bit */
  57 #define VSTART      0x19 /* Vertical frame (row) start high 8-bit */
  58 #define VSIZE       0x1A /* Vertical sensor size */
  59 #define PSHFT       0x1B /* Data format - pixel delay select */
  60 #define MIDH        0x1C /* Manufacturer ID byte - high */
  61 #define MIDL        0x1D /* Manufacturer ID byte - low  */
  62 #define LAEC        0x1F /* Fine AEC value */
  63 #define COM11       0x20 /* Common control 11 */
  64 #define BDBASE      0x22 /* Banding filter Minimum AEC value */
  65 #define DBSTEP      0x23 /* Banding filter Maximum Setp */
  66 #define AEW         0x24 /* AGC/AEC - Stable operating region (upper limit) */
  67 #define AEB         0x25 /* AGC/AEC - Stable operating region (lower limit) */
  68 #define VPT         0x26 /* AGC/AEC Fast mode operating region */
  69 #define REG28       0x28 /* Register 28 */
  70 #define HOUTSIZE    0x29 /* Horizontal data output size MSBs */
  71 #define EXHCH       0x2A /* Dummy pixel insert MSB */
  72 #define EXHCL       0x2B /* Dummy pixel insert LSB */
  73 #define VOUTSIZE    0x2C /* Vertical data output size MSBs */
  74 #define ADVFL       0x2D /* LSB of insert dummy lines in Vertical direction */
  75 #define ADVFH       0x2E /* MSG of insert dummy lines in Vertical direction */
  76 #define YAVE        0x2F /* Y/G Channel Average value */
  77 #define LUMHTH      0x30 /* Histogram AEC/AGC Luminance high level threshold */
  78 #define LUMLTH      0x31 /* Histogram AEC/AGC Luminance low  level threshold */
  79 #define HREF        0x32 /* Image start and size control */
  80 #define DM_LNL      0x33 /* Dummy line low  8 bits */
  81 #define DM_LNH      0x34 /* Dummy line high 8 bits */
  82 #define ADOFF_B     0x35 /* AD offset compensation value for B  channel */
  83 #define ADOFF_R     0x36 /* AD offset compensation value for R  channel */
  84 #define ADOFF_GB    0x37 /* AD offset compensation value for Gb channel */
  85 #define ADOFF_GR    0x38 /* AD offset compensation value for Gr channel */
  86 #define OFF_B       0x39 /* Analog process B  channel offset value */
  87 #define OFF_R       0x3A /* Analog process R  channel offset value */
  88 #define OFF_GB      0x3B /* Analog process Gb channel offset value */
  89 #define OFF_GR      0x3C /* Analog process Gr channel offset value */
  90 #define COM12       0x3D /* Common control 12 */
  91 #define COM13       0x3E /* Common control 13 */
  92 #define COM14       0x3F /* Common control 14 */
  93 #define COM15       0x40 /* Common control 15*/
  94 #define COM16       0x41 /* Common control 16 */
  95 #define TGT_B       0x42 /* BLC blue channel target value */
  96 #define TGT_R       0x43 /* BLC red  channel target value */
  97 #define TGT_GB      0x44 /* BLC Gb   channel target value */
  98 #define TGT_GR      0x45 /* BLC Gr   channel target value */
  99 /* for ov7720 */
 100 #define LCC0        0x46 /* Lens correction control 0 */
 101 #define LCC1        0x47 /* Lens correction option 1 - X coordinate */
 102 #define LCC2        0x48 /* Lens correction option 2 - Y coordinate */
 103 #define LCC3        0x49 /* Lens correction option 3 */
 104 #define LCC4        0x4A /* Lens correction option 4 - radius of the circular */
 105 #define LCC5        0x4B /* Lens correction option 5 */
 106 #define LCC6        0x4C /* Lens correction option 6 */
 107 /* for ov7725 */
 108 #define LC_CTR      0x46 /* Lens correction control */
 109 #define LC_XC       0x47 /* X coordinate of lens correction center relative */
 110 #define LC_YC       0x48 /* Y coordinate of lens correction center relative */
 111 #define LC_COEF     0x49 /* Lens correction coefficient */
 112 #define LC_RADI     0x4A /* Lens correction radius */
 113 #define LC_COEFB    0x4B /* Lens B channel compensation coefficient */
 114 #define LC_COEFR    0x4C /* Lens R channel compensation coefficient */
 115
 116 #define FIXGAIN     0x4D /* Analog fix gain amplifer */
 117 #define AREF0       0x4E /* Sensor reference control */
 118 #define AREF1       0x4F /* Sensor reference current control */
 119 #define AREF2       0x50 /* Analog reference control */
 120 #define AREF3       0x51 /* ADC    reference control */
 121 #define AREF4       0x52 /* ADC    reference control */
 122 #define AREF5       0x53 /* ADC    reference control */
 123 #define AREF6       0x54 /* Analog reference control */
 124 #define AREF7       0x55 /* Analog reference control */
 125 #define UFIX        0x60 /* U channel fixed value output */
 126 #define VFIX        0x61 /* V channel fixed value output */
 127 #define AWBB_BLK    0x62 /* AWB option for advanced AWB */
 128 #define AWB_CTRL0   0x63 /* AWB control byte 0 */
 129 #define DSP_CTRL1   0x64 /* DSP control byte 1 */
 130 #define DSP_CTRL2   0x65 /* DSP control byte 2 */
 131 #define DSP_CTRL3   0x66 /* DSP control byte 3 */
 132 #define DSP_CTRL4   0x67 /* DSP control byte 4 */
 133 #define AWB_BIAS    0x68 /* AWB BLC level clip */
 134 #define AWB_CTRL1   0x69 /* AWB control  1 */
 135 #define AWB_CTRL2   0x6A /* AWB control  2 */
 136 #define AWB_CTRL3   0x6B /* AWB control  3 */
 137 #define AWB_CTRL4   0x6C /* AWB control  4 */
 138 #define AWB_CTRL5   0x6D /* AWB control  5 */
 139 #define AWB_CTRL6   0x6E /* AWB control  6 */
 140 #define AWB_CTRL7   0x6F /* AWB control  7 */
 141 #define AWB_CTRL8   0x70 /* AWB control  8 */
 142 #define AWB_CTRL9   0x71 /* AWB control  9 */
 143 #define AWB_CTRL10  0x72 /* AWB control 10 */
 144 #define AWB_CTRL11  0x73 /* AWB control 11 */
 145 #define AWB_CTRL12  0x74 /* AWB control 12 */
 146 #define AWB_CTRL13  0x75 /* AWB control 13 */
 147 #define AWB_CTRL14  0x76 /* AWB control 14 */
 148 #define AWB_CTRL15  0x77 /* AWB control 15 */
 149 #define AWB_CTRL16  0x78 /* AWB control 16 */
 150 #define AWB_CTRL17  0x79 /* AWB control 17 */
 151 #define AWB_CTRL18  0x7A /* AWB control 18 */
 152 #define AWB_CTRL19  0x7B /* AWB control 19 */
 153 #define AWB_CTRL20  0x7C /* AWB control 20 */
 154 #define AWB_CTRL21  0x7D /* AWB control 21 */
 155 #define GAM1        0x7E /* Gamma Curve  1st segment input end point */
 156 #define GAM2        0x7F /* Gamma Curve  2nd segment input end point */
 157 #define GAM3        0x80 /* Gamma Curve  3rd segment input end point */
 158 #define GAM4        0x81 /* Gamma Curve  4th segment input end point */
 159 #define GAM5        0x82 /* Gamma Curve  5th segment input end point */
 160 #define GAM6        0x83 /* Gamma Curve  6th segment input end point */
 161 #define GAM7        0x84 /* Gamma Curve  7th segment input end point */
 162 #define GAM8        0x85 /* Gamma Curve  8th segment input end point */
 163 #define GAM9        0x86 /* Gamma Curve  9th segment input end point */
 164 #define GAM10       0x87 /* Gamma Curve 10th segment input end point */
 165 #define GAM11       0x88 /* Gamma Curve 11th segment input end point */
 166 #define GAM12       0x89 /* Gamma Curve 12th segment input end point */
 167 #define GAM13       0x8A /* Gamma Curve 13th segment input end point */
 168 #define GAM14       0x8B /* Gamma Curve 14th segment input end point */
 169 #define GAM15       0x8C /* Gamma Curve 15th segment input end point */
 170 #define SLOP        0x8D /* Gamma curve highest segment slope */
 171 #define DNSTH       0x8E /* De-noise threshold */
 172 #define EDGE0       0x8F /* Edge enhancement control 0 */
 173 #define EDGE1       0x90 /* Edge enhancement control 1 */
 174 #define DNSOFF      0x91 /* Auto De-noise threshold control */
 175 #define EDGE2       0x92 /* Edge enhancement strength low  point control */
 176 #define EDGE3       0x93 /* Edge enhancement strength high point control */
 177 #define MTX1        0x94 /* Matrix coefficient 1 */
 178 #define MTX2        0x95 /* Matrix coefficient 2 */
 179 #define MTX3        0x96 /* Matrix coefficient 3 */
 180 #define MTX4        0x97 /* Matrix coefficient 4 */
 181 #define MTX5        0x98 /* Matrix coefficient 5 */
 182 #define MTX6        0x99 /* Matrix coefficient 6 */
 183 #define MTX_CTRL    0x9A /* Matrix control */
 184 #define BRIGHT      0x9B /* Brightness control */
 185 #define CNTRST      0x9C /* Contrast contrast */
 186 #define CNTRST_CTRL 0x9D /* Contrast contrast center */
 187 #define UVAD_J0     0x9E /* Auto UV adjust contrast 0 */
 188 #define UVAD_J1     0x9F /* Auto UV adjust contrast 1 */
 189 #define SCAL0       0xA0 /* Scaling control 0 */
 190 #define SCAL1       0xA1 /* Scaling control 1 */
 191 #define SCAL2       0xA2 /* Scaling control 2 */
 192 #define FIFODLYM    0xA3 /* FIFO manual mode delay control */
 193 #define FIFODLYA    0xA4 /* FIFO auto   mode delay control */
 194 #define SDE         0xA6 /* Special digital effect control */
 195 #define USAT        0xA7 /* U component saturation control */
 196 #define VSAT        0xA8 /* V component saturation control */
 197 /* for ov7720 */
 198 #define HUE0        0xA9 /* Hue control 0 */
 199 #define HUE1        0xAA /* Hue control 1 */
 200 /* for ov7725 */
 201 #define HUECOS      0xA9 /* Cosine value */
 202 #define HUESIN      0xAA /* Sine value */
 203
 204 #define SIGN        0xAB /* Sign bit for Hue and contrast */
 205 #define DSPAUTO     0xAC /* DSP auto function ON/OFF control */
 206
 207 /*
 208  * register detail
 209  */
 210
 211 /* COM2 */
 212 #define SOFT_SLEEP_MODE 0x10    /* Soft sleep mode */
 213                                 /* Output drive capability */
 214 #define OCAP_1x         0x00    /* 1x */
 215 #define OCAP_2x         0x01    /* 2x */
 216 #define OCAP_3x         0x02    /* 3x */
 217 #define OCAP_4x         0x03    /* 4x */
 218
 219 /* COM3 */
 220 #define SWAP_MASK       0x38
 221
 222 #define VFIMG_ON_OFF    0x80    /* Vertical flip image ON/OFF selection */
 223 #define HMIMG_ON_OFF    0x40    /* Horizontal mirror image ON/OFF selection */
 224 #define SWAP_RGB        0x20    /* Swap B/R  output sequence in RGB mode */
 225 #define SWAP_YUV        0x10    /* Swap Y/UV output sequence in YUV mode */
 226 #define SWAP_ML         0x08    /* Swap output MSB/LSB */
 227                                 /* Tri-state option for output clock */
 228 #define NOTRI_CLOCK     0x04    /*   0: Tri-state    at this period */
 229                                 /*   1: No tri-state at this period */
 230                                 /* Tri-state option for output data */
 231 #define NOTRI_DATA      0x02    /*   0: Tri-state    at this period */
 232                                 /*   1: No tri-state at this period */
 233 #define SCOLOR_TEST     0x01    /* Sensor color bar test pattern */
 234
 235 /* COM4 */
 236                                 /* PLL frequency control */
 237 #define PLL_BYPASS      0x00    /*  00: Bypass PLL */
 238 #define PLL_4x          0x40    /*  01: PLL 4x */
 239 #define PLL_6x          0x80    /*  10: PLL 6x */
 240 #define PLL_8x          0xc0    /*  11: PLL 8x */
 241                                 /* AEC evaluate window */
 242 #define AEC_FULL        0x00    /*  00: Full window */
 243 #define AEC_1p2         0x10    /*  01: 1/2  window */
 244 #define AEC_1p4         0x20    /*  10: 1/4  window */
 245 #define AEC_2p3         0x30    /*  11: Low 2/3 window */
 246
 247 /* COM5 */
 248 #define AFR_ON_OFF      0x80    /* Auto frame rate control ON/OFF selection */
 249 #define AFR_SPPED       0x40    /* Auto frame rate control speed slection */
 250                                 /* Auto frame rate max rate control */
 251 #define AFR_NO_RATE     0x00    /*     No  reduction of frame rate */
 252 #define AFR_1p2         0x10    /*     Max reduction to 1/2 frame rate */
 253 #define AFR_1p4         0x20    /*     Max reduction to 1/4 frame rate */
 254 #define AFR_1p8         0x30    /* Max reduction to 1/8 frame rate */
 255                                 /* Auto frame rate active point control */
 256 #define AF_2x           0x00    /*     Add frame when AGC reaches  2x gain */
 257 #define AF_4x           0x04    /*     Add frame when AGC reaches  4x gain */
 258 #define AF_8x           0x08    /*     Add frame when AGC reaches  8x gain */
 259 #define AF_16x          0x0c    /* Add frame when AGC reaches 16x gain */
 260                                 /* AEC max step control */
 261 #define AEC_NO_LIMIT    0x01    /*   0 : AEC incease step has limit */
 262                                 /*   1 : No limit to AEC increase step */
 263
 264 /* COM7 */
 265                                 /* SCCB Register Reset */
 266 #define SCCB_RESET      0x80    /*   0 : No change */
 267                                 /*   1 : Resets all registers to default */
 268                                 /* Resolution selection */
 269 #define SLCT_MASK       0x40    /*   Mask of VGA or QVGA */
 270 #define SLCT_VGA        0x00    /*   0 : VGA */
 271 #define SLCT_QVGA       0x40    /*   1 : QVGA */
 272 #define ITU656_ON_OFF   0x20    /* ITU656 protocol ON/OFF selection */
 273                                 /* RGB output format control */
 274 #define FMT_GBR422      0x00    /*      00 : GBR 4:2:2 */
 275 #define FMT_RGB565      0x04    /*      01 : RGB 565 */
 276 #define FMT_RGB555      0x08    /*      10 : RGB 555 */
 277 #define FMT_RGB444      0x0c    /* 11 : RGB 444 */
 278                                 /* Output format control */
 279 #define OFMT_YUV        0x00    /*      00 : YUV */
 280 #define OFMT_P_BRAW     0x01    /*      01 : Processed Bayer RAW */
 281 #define OFMT_RGB        0x02    /*      10 : RGB */
 282 #define OFMT_BRAW       0x03    /* 11 : Bayer RAW */
 283
 284 /* COM8 */
 285 #define FAST_ALGO       0x80    /* Enable fast AGC/AEC algorithm */
 286                                 /* AEC Setp size limit */
 287 #define UNLMT_STEP      0x40    /*   0 : Step size is limited */
 288                                 /*   1 : Unlimited step size */
 289 #define BNDF_ON_OFF     0x20    /* Banding filter ON/OFF */
 290 #define AEC_BND         0x10    /* Enable AEC below banding value */
 291 #define AEC_ON_OFF      0x08    /* Fine AEC ON/OFF control */
 292 #define AGC_ON          0x04    /* AGC Enable */
 293 #define AWB_ON          0x02    /* AWB Enable */
 294 #define AEC_ON          0x01    /* AEC Enable */
 295
 296 /* COM9 */
 297 #define BASE_AECAGC     0x80    /* Histogram or average based AEC/AGC */
 298                                 /* Automatic gain ceiling - maximum AGC value */
 299 #define GAIN_2x         0x00    /*    000 :   2x */
 300 #define GAIN_4x         0x10    /*    001 :   4x */
 301 #define GAIN_8x         0x20    /*    010 :   8x */
 302 #define GAIN_16x        0x30    /* 011 :  16x */
 303 #define GAIN_32x        0x40    /*    100 :  32x */
 304 #define GAIN_64x        0x50    /* 101 :  64x */
 305 #define GAIN_128x       0x60    /* 110 : 128x */
 306 #define DROP_VSYNC      0x04    /* Drop VSYNC output of corrupt frame */
 307 #define DROP_HREF       0x02    /* Drop HREF  output of corrupt frame */
 308
 309 /* COM11 */
 310 #define SGLF_ON_OFF     0x02    /* Single frame ON/OFF selection */
 311 #define SGLF_TRIG       0x01    /* Single frame transfer trigger */
 312
 313 /* EXHCH */
 314 #define VSIZE_LSB       0x04    /* Vertical data output size LSB */
 315
 316 /* DSP_CTRL1 */
 317 #define FIFO_ON         0x80    /* FIFO enable/disable selection */
 318 #define UV_ON_OFF       0x40    /* UV adjust function ON/OFF selection */
 319 #define YUV444_2_422    0x20    /* YUV444 to 422 UV channel option selection */
 320 #define CLR_MTRX_ON_OFF 0x10    /* Color matrix ON/OFF selection */
 321 #define INTPLT_ON_OFF   0x08    /* Interpolation ON/OFF selection */
 322 #define GMM_ON_OFF      0x04    /* Gamma function ON/OFF selection */
 323 #define AUTO_BLK_ON_OFF 0x02    /* Black defect auto correction ON/OFF */
 324 #define AUTO_WHT_ON_OFF 0x01    /* White define auto correction ON/OFF */
 325
 326 /* DSP_CTRL3 */
 327 #define UV_MASK         0x80    /* UV output sequence option */
 328 #define UV_ON           0x80    /*   ON */
 329 #define UV_OFF          0x00    /*   OFF */
 330 #define CBAR_MASK       0x20    /* DSP Color bar mask */
 331 #define CBAR_ON         0x20    /*   ON */
 332 #define CBAR_OFF        0x00    /*   OFF */
 333
 334 /* HSTART */
 335 #define HST_VGA         0x23
 336 #define HST_QVGA        0x3F
 337
 338 /* HSIZE */
 339 #define HSZ_VGA         0xA0
 340 #define HSZ_QVGA        0x50
 341
 342 /* VSTART */
 343 #define VST_VGA         0x07
 344 #define VST_QVGA        0x03
 345
 346 /* VSIZE */
 347 #define VSZ_VGA         0xF0
 348 #define VSZ_QVGA        0x78
 349
 350 /* HOUTSIZE */
 351 #define HOSZ_VGA        0xA0
 352 #define HOSZ_QVGA       0x50
 353
 354 /* VOUTSIZE */
 355 #define VOSZ_VGA        0xF0
 356 #define VOSZ_QVGA       0x78
 357
 358 /*
 359  * bit configure (32 bit)
 360  * this is used in struct ov772x_color_format :: option
 361  */
 362 #define OP_UV       0x00000001
 363 #define OP_SWAP_RGB 0x00000002
 364
 365 /*
 366  * ID
 367  */
 368 #define OV7720  0x7720
 369 #define OV7725  0x7721
 370 #define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
 371
 372 /*
 373  * struct
 374  */
 375 struct regval_list {
 376         unsigned char reg_num;
 377         unsigned char value;
 378 };
 379
 380 struct ov772x_color_format {
 381         char                     *name;
 382         __u32                     fourcc;
 383         const struct regval_list *regs;
 384         unsigned int              option;
 385 };
 386
 387 struct ov772x_win_size {
 388         char                     *name;
 389         __u32                     width;
 390         __u32                     height;
 391         unsigned char             com7_bit;
 392         const struct regval_list *regs;
 393 };
 394
 395 struct ov772x_priv {
 396         struct ov772x_camera_info        *info;
 397         struct i2c_client                *client;
 398         struct soc_camera_device          icd;
 399         const struct ov772x_color_format *fmt;
 400         const struct ov772x_win_size     *win;
 401         int                               model;
 402 };
 403
 404 #define ENDMARKER { 0xff, 0xff }
 405
 406 /*
 407  * register setting for color format
 408  */
 409 static const struct regval_list ov772x_RGB555_regs[] = {
 410         { COM3, 0x00 },
 411         { COM7, FMT_RGB555 | OFMT_RGB },
 412         ENDMARKER,
 413 };
 414
 415 static const struct regval_list ov772x_RGB565_regs[] = {
 416         { COM3, 0x00 },
 417         { COM7, FMT_RGB565 | OFMT_RGB },
 418         ENDMARKER,
 419 };
 420
 421 static const struct regval_list ov772x_YYUV_regs[] = {
 422         { COM3, SWAP_YUV },
 423         { COM7, OFMT_YUV },
 424         ENDMARKER,
 425 };
 426
 427 static const struct regval_list ov772x_UVYY_regs[] = {
 428         { COM3, 0x00 },
 429         { COM7, OFMT_YUV },
 430         ENDMARKER,
 431 };
 432
 433
 434 /*
 435  * register setting for window size
 436  */
 437 static const struct regval_list ov772x_qvga_regs[] = {
 438         { HSTART,   HST_QVGA },
 439         { HSIZE,    HSZ_QVGA },
 440         { VSTART,   VST_QVGA },
 441         { VSIZE,    VSZ_QVGA  },
 442         { HOUTSIZE, HOSZ_QVGA },
 443         { VOUTSIZE, VOSZ_QVGA },
 444         ENDMARKER,
 445 };
 446
 447 static const struct regval_list ov772x_vga_regs[] = {
 448         { HSTART,   HST_VGA },
 449         { HSIZE,    HSZ_VGA },
 450         { VSTART,   VST_VGA },
 451         { VSIZE,    VSZ_VGA },
 452         { HOUTSIZE, HOSZ_VGA },
 453         { VOUTSIZE, VOSZ_VGA },
 454         ENDMARKER,
 455 };
 456
 457 /*
 458  * supported format list
 459  */
 460
 461 #define SETFOURCC(type) .name = (#type), .fourcc = (V4L2_PIX_FMT_ ## type)
 462 static const struct soc_camera_data_format ov772x_fmt_lists[] = {
 463         {
 464                 SETFOURCC(YUYV),
 465                 .depth      = 16,
 466                 .colorspace = V4L2_COLORSPACE_JPEG,
 467         },
 468         {
 469                 SETFOURCC(YVYU),
 470                 .depth      = 16,
 471                 .colorspace = V4L2_COLORSPACE_JPEG,
 472         },
 473         {
 474                 SETFOURCC(UYVY),
 475                 .depth      = 16,
 476                 .colorspace = V4L2_COLORSPACE_JPEG,
 477         },
 478         {
 479                 SETFOURCC(RGB555),
 480                 .depth      = 16,
 481                 .colorspace = V4L2_COLORSPACE_SRGB,
 482         },
 483         {
 484                 SETFOURCC(RGB555X),
 485                 .depth      = 16,
 486                 .colorspace = V4L2_COLORSPACE_SRGB,
 487         },
 488         {
 489                 SETFOURCC(RGB565),
 490                 .depth      = 16,
 491                 .colorspace = V4L2_COLORSPACE_SRGB,
 492         },
 493         {
 494                 SETFOURCC(RGB565X),
 495                 .depth      = 16,
 496                 .colorspace = V4L2_COLORSPACE_SRGB,
 497         },
 498 };
 499
 500 /*
 501  * color format list
 502  */
 503 #define T_YUYV 0
 504 static const struct ov772x_color_format ov772x_cfmts[] = {
 505         [T_YUYV] = {
 506                 SETFOURCC(YUYV),
 507                 .regs   = ov772x_YYUV_regs,
 508         },
 509         {
 510                 SETFOURCC(YVYU),
 511                 .regs   = ov772x_YYUV_regs,
 512                 .option = OP_UV,
 513         },
 514         {
 515                 SETFOURCC(UYVY),
 516                 .regs   = ov772x_UVYY_regs,
 517         },
 518         {
 519                 SETFOURCC(RGB555),
 520                 .regs   = ov772x_RGB555_regs,
 521                 .option = OP_SWAP_RGB,
 522         },
 523         {
 524                 SETFOURCC(RGB555X),
 525                 .regs   = ov772x_RGB555_regs,
 526         },
 527         {
 528                 SETFOURCC(RGB565),
 529                 .regs   = ov772x_RGB565_regs,
 530                 .option = OP_SWAP_RGB,
 531         },
 532         {
 533                 SETFOURCC(RGB565X),
 534                 .regs   = ov772x_RGB565_regs,
 535         },
 536 };
 537
 538
 539 /*
 540  * window size list
 541  */
 542 #define VGA_WIDTH   640
 543 #define VGA_HEIGHT  480
 544 #define QVGA_WIDTH  320
 545 #define QVGA_HEIGHT 240
 546 #define MAX_WIDTH   VGA_WIDTH
 547 #define MAX_HEIGHT  VGA_HEIGHT
 548
 549 static const struct ov772x_win_size ov772x_win_vga = {
 550         .name     = "VGA",
 551         .width    = VGA_WIDTH,
 552         .height   = VGA_HEIGHT,
 553         .com7_bit = SLCT_VGA,
 554         .regs     = ov772x_vga_regs,
 555 };
 556
 557 static const struct ov772x_win_size ov772x_win_qvga = {
 558         .name     = "QVGA",
 559         .width    = QVGA_WIDTH,
 560         .height   = QVGA_HEIGHT,
 561         .com7_bit = SLCT_QVGA,
 562         .regs     = ov772x_qvga_regs,
 563 };
 564
 565
 566 /*
 567  * general function
 568  */
 569
 570 static int ov772x_write_array(struct i2c_client        *client,
 571                               const struct regval_list *vals)
 572 {
 573         while (vals->reg_num != 0xff) {
 574                 int ret = i2c_smbus_write_byte_data(client,
 575                                                     vals->reg_num,
 576                                                     vals->value);
 577                 if (ret < 0)
 578                         return ret;
 579                 vals++;
 580         }
 581         return 0;
 582 }
 583
 584 static int ov772x_mask_set(struct i2c_client *client,
 585                                           u8  command,
 586                                           u8  mask,
 587                                           u8  set)
 588 {
 589         s32 val = i2c_smbus_read_byte_data(client, command);
 590         val &= ~mask;
 591         val |=  set;
 592
 593         return i2c_smbus_write_byte_data(client, command, val);
 594 }
 595
 596 static int ov772x_reset(struct i2c_client *client)
 597 {
 598         int ret = i2c_smbus_write_byte_data(client, COM7, SCCB_RESET);
 599         msleep(1);
 600         return ret;
 601 }
 602
 603 /*
 604  * soc_camera_ops function
 605  */
 606
 607 static int ov772x_init(struct soc_camera_device *icd)
 608 {
 609         struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
 610         int ret = 0;
 611
 612         if (priv->info->link.power) {
 613                 ret = priv->info->link.power(&priv->client->dev, 1);
 614                 if (ret < 0)
 615                         return ret;
 616         }
 617
 618         if (priv->info->link.reset)
 619                 ret = priv->info->link.reset(&priv->client->dev);
 620
 621         return ret;
 622 }
 623
 624 static int ov772x_release(struct soc_camera_device *icd)
 625 {
 626         struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
 627         int ret = 0;
 628
 629         if (priv->info->link.power)
 630                 ret = priv->info->link.power(&priv->client->dev, 0);
 631
 632         return ret;
 633 }
 634
 635 static int ov772x_start_capture(struct soc_camera_device *icd)
 636 {
 637         struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
 638         int                 ret;
 639
 640         if (!priv->win)
 641                 priv->win = &ov772x_win_vga;
 642         if (!priv->fmt)
 643                 priv->fmt = &ov772x_cfmts[T_YUYV];
 644
 645         /*
 646          * reset hardware
 647          */
 648         ov772x_reset(priv->client);
 649
 650         /*
 651          * set color format
 652          */
 653         ret = ov772x_write_array(priv->client, priv->fmt->regs);
 654         if (ret < 0)
 655                 goto start_end;
 656
 657         /*
 658          * set size format
 659          */
 660         ret = ov772x_write_array(priv->client, priv->win->regs);
 661         if (ret < 0)
 662                 goto start_end;
 663
 664         /*
 665          * set COM7 bit ( QVGA or VGA )
 666          */
 667         ret = ov772x_mask_set(priv->client,
 668                               COM7, SLCT_MASK, priv->win->com7_bit);
 669         if (ret < 0)
 670                 goto start_end;
 671
 672         /*
 673          * set UV setting
 674          */
 675         if (priv->fmt->option & OP_UV) {
 676                 ret = ov772x_mask_set(priv->client,
 677                                       DSP_CTRL3, UV_MASK, UV_ON);
 678                 if (ret < 0)
 679                         goto start_end;
 680         }
 681
 682         /*
 683          * set SWAP setting
 684          */
 685         if (priv->fmt->option & OP_SWAP_RGB) {
 686                 ret = ov772x_mask_set(priv->client,
 687                                       COM3, SWAP_MASK, SWAP_RGB);
 688                 if (ret < 0)
 689                         goto start_end;
 690         }
 691
 692         dev_dbg(&icd->dev,
 693                  "format %s, win %s\n", priv->fmt->name, priv->win->name);
 694
 695 start_end:
 696         priv->fmt = NULL;
 697         priv->win = NULL;
 698
 699         return ret;
 700 }
 701
 702 static int ov772x_stop_capture(struct soc_camera_device *icd)
 703 {
 704         struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
 705         ov772x_reset(priv->client);
 706         return 0;
 707 }
 708
 709 static int ov772x_set_bus_param(struct soc_camera_device *icd,
 710                                 unsigned long             flags)
 711 {
 712         return 0;
 713 }
 714
 715 static unsigned long ov772x_query_bus_param(struct soc_camera_device *icd)
 716 {
 717         struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
 718         struct soc_camera_link *icl = priv->client->dev.platform_data;
 719         unsigned long flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_MASTER |
 720                 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_HSYNC_ACTIVE_HIGH |
 721                 priv->info->buswidth;
 722
 723         return soc_camera_apply_sensor_flags(icl, flags);
 724 }
 725
 726 static int ov772x_get_chip_id(struct soc_camera_device *icd,
 727                               struct v4l2_dbg_chip_ident   *id)
 728 {
 729         struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
 730
 731         id->ident    = priv->model;
 732         id->revision = 0;
 733
 734         return 0;
 735 }
 736
 737 #ifdef CONFIG_VIDEO_ADV_DEBUG
 738 static int ov772x_get_register(struct soc_camera_device *icd,
 739                                struct v4l2_dbg_register *reg)
 740 {
 741         struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
 742         int                 ret;
 743
 744         reg->size = 1;
 745         if (reg->reg > 0xff)
 746                 return -EINVAL;
 747
 748         ret = i2c_smbus_read_byte_data(priv->client, reg->reg);
 749         if (ret < 0)
 750                 return ret;
 751
 752         reg->val = (__u64)ret;
 753
 754         return 0;
 755 }
 756
 757 static int ov772x_set_register(struct soc_camera_device *icd,
 758                                struct v4l2_dbg_register *reg)
 759 {
 760         struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
 761
 762         if (reg->reg > 0xff ||
 763             reg->val > 0xff)
 764                 return -EINVAL;
 765
 766         return i2c_smbus_write_byte_data(priv->client, reg->reg, reg->val);
 767 }
 768 #endif
 769
 770 static const struct ov772x_win_size*
 771 ov772x_select_win(u32 width, u32 height)
 772 {
 773         __u32 diff;
 774         const struct ov772x_win_size *win;
 775
 776         /* default is QVGA */
 777         diff = abs(width - ov772x_win_qvga.width) +
 778                 abs(height - ov772x_win_qvga.height);
 779         win = &ov772x_win_qvga;
 780
 781         /* VGA */
 782         if (diff >
 783             abs(width  - ov772x_win_vga.width) +
 784             abs(height - ov772x_win_vga.height))
 785                 win = &ov772x_win_vga;
 786
 787         return win;
 788 }
 789
 790
 791 static int ov772x_set_fmt(struct soc_camera_device *icd,
 792                           __u32                     pixfmt,
 793                           struct v4l2_rect         *rect)
 794 {
 795         struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
 796         int ret = -EINVAL;
 797         int i;
 798
 799         /*
 800          * select format
 801          */
 802         priv->fmt = NULL;
 803         for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
 804                 if (pixfmt == ov772x_cfmts[i].fourcc) {
 805                         priv->fmt = ov772x_cfmts + i;
 806                         ret = 0;
 807                         break;
 808                 }
 809         }
 810
 811         /*
 812          * select win
 813          */
 814         priv->win = ov772x_select_win(rect->width, rect->height);
 815
 816         return ret;
 817 }
 818
 819 static int ov772x_try_fmt(struct soc_camera_device *icd,
 820                           struct v4l2_format       *f)
 821 {
 822         struct v4l2_pix_format *pix = &f->fmt.pix;
 823         const struct ov772x_win_size *win;
 824
 825         /*
 826          * select suitable win
 827          */
 828         win = ov772x_select_win(pix->width, pix->height);
 829
 830         pix->width  = win->width;
 831         pix->height = win->height;
 832         pix->field  = V4L2_FIELD_NONE;
 833
 834         return 0;
 835 }
 836
 837 static int ov772x_video_probe(struct soc_camera_device *icd)
 838 {
 839         struct ov772x_priv *priv = container_of(icd, struct ov772x_priv, icd);
 840         u8                  pid, ver;
 841         const char         *devname;
 842
 843         /*
 844          * We must have a parent by now. And it cannot be a wrong one.
 845          * So this entire test is completely redundant.
 846          */
 847         if (!icd->dev.parent ||
 848             to_soc_camera_host(icd->dev.parent)->nr != icd->iface)
 849                 return -ENODEV;
 850
 851         /*
 852          * ov772x only use 8 or 10 bit bus width
 853          */
 854         if (SOCAM_DATAWIDTH_10 != priv->info->buswidth &&
 855             SOCAM_DATAWIDTH_8  != priv->info->buswidth) {
 856                 dev_err(&icd->dev, "bus width error\n");
 857                 return -ENODEV;
 858         }
 859
 860         icd->formats     = ov772x_fmt_lists;
 861         icd->num_formats = ARRAY_SIZE(ov772x_fmt_lists);
 862
 863         /*
 864          * check and show product ID and manufacturer ID
 865          */
 866         pid = i2c_smbus_read_byte_data(priv->client, PID);
 867         ver = i2c_smbus_read_byte_data(priv->client, VER);
 868
 869         switch (VERSION(pid, ver)) {
 870         case OV7720:
 871                 devname     = "ov7720";
 872                 priv->model = V4L2_IDENT_OV7720;
 873                 break;
 874         case OV7725:
 875                 devname     = "ov7725";
 876                 priv->model = V4L2_IDENT_OV7725;
 877                 break;
 878         default:
 879                 dev_err(&icd->dev,
 880                         "Product ID error %x:%x\n", pid, ver);
 881                 return -ENODEV;
 882         }
 883
 884         dev_info(&icd->dev,
 885                  "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
 886                  devname,
 887                  pid,
 888                  ver,
 889                  i2c_smbus_read_byte_data(priv->client, MIDH),
 890                  i2c_smbus_read_byte_data(priv->client, MIDL));
 891
 892
 893         return soc_camera_video_start(icd);
 894 }
 895
 896 static void ov772x_video_remove(struct soc_camera_device *icd)
 897 {
 898         soc_camera_video_stop(icd);
 899 }
 900
 901 static struct soc_camera_ops ov772x_ops = {
 902         .owner                  = THIS_MODULE,
 903         .probe                  = ov772x_video_probe,
 904         .remove                 = ov772x_video_remove,
 905         .init                   = ov772x_init,
 906         .release                = ov772x_release,
 907         .start_capture          = ov772x_start_capture,
 908         .stop_capture           = ov772x_stop_capture,
 909         .set_fmt                = ov772x_set_fmt,
 910         .try_fmt                = ov772x_try_fmt,
 911         .set_bus_param          = ov772x_set_bus_param,
 912         .query_bus_param        = ov772x_query_bus_param,
 913         .get_chip_id            = ov772x_get_chip_id,
 914 #ifdef CONFIG_VIDEO_ADV_DEBUG
 915         .get_register           = ov772x_get_register,
 916         .set_register           = ov772x_set_register,
 917 #endif
 918 };
 919
 920 /*
 921  * i2c_driver function
 922  */
 923
 924 static int ov772x_probe(struct i2c_client *client,
 925                          const struct i2c_device_id *did)
 926 {
 927         struct ov772x_priv        *priv;
 928         struct ov772x_camera_info *info;
 929         struct soc_camera_device  *icd;
 930         struct i2c_adapter        *adapter = to_i2c_adapter(client->dev.parent);
 931         int                        ret;
 932
 933         info = client->dev.platform_data;
 934         if (!info)
 935                 return -EINVAL;
 936
 937         if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
 938                 dev_err(&adapter->dev,
 939                         "I2C-Adapter doesn't support "
 940                         "I2C_FUNC_SMBUS_BYTE_DATA\n");
 941                 return -EIO;
 942         }
 943
 944         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 945         if (!priv)
 946                 return -ENOMEM;
 947
 948         priv->info   = info;
 949         priv->client = client;
 950         i2c_set_clientdata(client, priv);
 951
 952         icd             = &priv->icd;
 953         icd->ops        = &ov772x_ops;
 954         icd->control    = &client->dev;
 955         icd->width_max  = MAX_WIDTH;
 956         icd->height_max = MAX_HEIGHT;
 957         icd->iface      = priv->info->link.bus_id;
 958
 959         ret = soc_camera_device_register(icd);
 960
 961         if (ret) {
 962                 i2c_set_clientdata(client, NULL);
 963                 kfree(priv);
 964         }
 965
 966         return ret;
 967 }
 968
 969 static int ov772x_remove(struct i2c_client *client)
 970 {
 971         struct ov772x_priv *priv = i2c_get_clientdata(client);
 972
 973         soc_camera_device_unregister(&priv->icd);
 974         i2c_set_clientdata(client, NULL);
 975         kfree(priv);
 976         return 0;
 977 }
 978
 979 static const struct i2c_device_id ov772x_id[] = {
 980         { "ov772x", 0 },
 981         { }
 982 };
 983 MODULE_DEVICE_TABLE(i2c, ov772x_id);
 984
 985 static struct i2c_driver ov772x_i2c_driver = {
 986         .driver = {
 987                 .name = "ov772x",
 988         },
 989         .probe    = ov772x_probe,
 990         .remove   = ov772x_remove,
 991         .id_table = ov772x_id,
 992 };
 993
 994 /*
 995  * module function
 996  */
 997
 998 static int __init ov772x_module_init(void)
 999 {
1000         return i2c_add_driver(&ov772x_i2c_driver);
1001 }
1002
1003 static void __exit ov772x_module_exit(void)
1004 {
1005         i2c_del_driver(&ov772x_i2c_driver);
1006 }
1007
1008 module_init(ov772x_module_init);
1009 module_exit(ov772x_module_exit);
1010
1011 MODULE_DESCRIPTION("SoC Camera driver for ov772x");
1012 MODULE_AUTHOR("Kuninori Morimoto");
1013 MODULE_LICENSE("GPL v2");